Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/10—Programming or data input circuits
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/68—Floating-gate IGFETs
  • H10D30/687—Floating-gate IGFETs having more than two programming levels

Definitions

• the present invention relates to non-volatile memories with variable coupling which can be programmed multiple times.
• the invention has particular applicability to applications where is it desirable to customize electronic circuits.
• OTP time programmable
• MTP multi-time programmable
• OTP one time programmable
• MTP multiple time programmable
• a unique aspect of the device is that the floating gate of the memory cell structure is electrically coupled strongly through one of the S/D junctions of the transistor, whereas traditional single poly nonvolatile memory cells require either an additional interconnect layer to couple to the floating gate, or the floating gate has virtually none or minimal electrical coupling to any of the existing electrical signals.
• Another key feature is that it is implemented with an NMOS device structure, whereas the traditional single-poly OTP is commonly implemented with a PMOS device structure. This means that the device can be formed at the same time as other n-channel devices on a wafer.
• an NMOS device structure behaves similar to an EPROM device, i.e., the device is programmed into a nonconducting state from a conducting state.
• the most commonly used PMOS OTP device is programmed from a non-conducting state into a conducting state). This can eliminate the need of an additional masking step that is commonly associated with a PMOS OTP device in order to make sure that PMOS device is in a non-conducting state coming out of the manufacturing fab.
• an NMOS device's programming mechanism with channel hot electrons injection is self-limiting, unlike that case of a PMOS with channel hot electron programming, the amount of energy consumption during programming is self-limited for this invention.
• NMOS OTP implementation is disclosed by USP 6,920,067, incorporated by reference herein.
• the device in this reference is programmed with channel hot-hole-injection.
• the disclosure teaches that the device is programmed into conducting state, after the channel hot hole injection.
• An NMOS device will conduct a channel current to initiate the hot hole injection only when the floating gate potential is sufficient to turn on the device, or when the threshold voltage is always low initially to allow channel current conduction. The only way to ensure either scenario is to introduce an additional process step to modify the turn on characteristics of the NMOS.
• the channel is conducting initially and hot holes are injected, the holes injected on the floating gate will make the device more conductive. So the device basically goes from a conductive state (in order to initiate channel current for hot hole injection) to a highly conductive state. This is not a very optimal behavior for a memory device.
• An object of the present invention is to overcome the aforementioned limitations of the prior art.
• a first aspect of the invention therefore concerns a programmable multi-state non-volatile device situated on a substrate comprising: a floating gate; wherein the floating gate is comprised of a material that is also used as a gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory; a source region; and a drain region; and an n-channel coupling the source region and the drain region; wherein the drain region overlaps a sufficient portion of the gate such that a programming voltage for the device applied to the drain can be imparted to the floating gate through capacitive coupling; further wherein the device is adapted so that more than one bit of information can be stored by the programming voltage.
• the device is preferably adapted such that during a read operation only a portion of the drain region receives a read voltage. That is, a portion or all of the drain region can be biased during a program operation to vary an amount of information stored in the device.
• the device can be read by a bias voltage applied to the drain region which is adjusted with time to determine a threshold voltage of the floating gate.
• the floating gate can be erased to allow the device to re-programmed.
• the floating gate is eraseable by an erase voltage applied to the source region.
• the device can be integrated as part of a programmable array embedded with separate logic circuits and/or memory circuits in an integrated circuit.
• Such circuit may be one of the following: a data encryption circuit; a reference trimming circuit; a manufacturing ID; a security ID, or any other circuit that requires customized non-volatile data.
• the capacitive coupling can take place in a first trench situated in the substrate. These trenches may be part of an embedded
• the amount of coupling can be tailored as desired based on selective control of a gate - interconnect mask, a source/drain diffusion mask, or both.
• Other configurations can include a second programmable device coupled in a paired latch arrangement such a datum and its compliment are stored in the paired latch.
• a variable programming voltage is preferably used. This allows for multiple bits of data to be written by the programming voltage.
• MOTP multi-level one-time programmable
• the floating gate is comprised of a material that is also shared by an interconnect and/or another gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory; a source region; and a drain region overlapping a portion of the floating gate, and the drain region including at least a first drain region and a second selectable drain region; wherein a variable capacitive coupling between the drain region and the floating gate can be effectuated by one or more selection signals applied to the first drain region and the second drain region respectively; wherein the variable capacitive coupling causes a variable amount of channel hot electrons from the first drain region and from the second drain region to permanently alter a threshold value of the floating gate and store multi-bit data in the O
• a further aspect of the invention concerns the fact that in some embodiments, the device has a multi-level (mulit-bit) programmed state defined by an amount of charge stored on the floating gate by the variable programming voltage.
• aspects of the invention concern methods of forming the aforementioned multi-level non-volatile programmable memory device. Still other aspects of the invention concern methods of operating the aforementioned multi-level non-volatile programmable memory device.
• an amount of capacitive coupling can be adjusted based on altering a number of N (N> 1 ) separate drain regions selected to overlap the floating gate and/or by altering a programming voltage level.
• a read voltage is preferably controlled to have a range of values which vary in time corresponding to threshold states of the floating gate.
• the multi-state device is preferably programmed with channel hot electrons that alter a voltage threshold of a floating gate, and erased with band-band tunneling hot hole injection.
• the device is adapted so that different ones of the first drain region and the second drain region can be coupled to the gate during program and read operations respectively. For example either, none or both the first drain region and the second region can be biased during a program operation, and only one of the first region and the second region can be biased during a read operation. Similarly, either or both of the first region and the second region can be biased during an erase operation.
• Preferred embodiments of the multi-state device are n-channel, but p- channel can also be supported.
• the floating gate can be implemented as a multi-level structure, as part of a thin film transistor, or even oriented in a non-planar configuration.
• Another aspect of the invention concerns a single bit NV memory which shares similar structural, formation and operating characteristics as the multi-state device noted above.
• Still another aspect concerns a one-time programmable (OTP) device comprising: a floating gate; wherein the floating gate is comprised of a material that is also shared by an interconnect and/or another gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory; a source region; and a drain region overlapping a portion of the floating gate, and the drain region including at least a first drain region and a second selectable drain region; wherein a variable capacitive coupling between the drain region and the floating gate can be effectuated by one or more selection signals applied to the first drain region and the second drain region respectively; wherein the variable capacitive coupling causes a variable amount of channel hot electrons from the first drain region and from the second drain region to permanently alter a threshold value of the floating gate and store data in the OTP device.
• OTP one-time programmable
• the OTP device can be similarly configured structurally and operationally as the multi-level device noted above. That is, an amount of capacitive coupling can be adjusted based on controlling/selecting a number of N (N> 1 ) separate drain regions, or the size of an overlap with the floating gate, or using a variable programming voltage.
• the devices are preferably embedded in a computing circuit and formed entirely by masks/CMOS processing used to form other logic and/or memory n-channel devices in the processing circuit.
• the non-volatile programmable memory device is used to store one or more identification codes for die/wafers.
• FIG. 1 is a top down view of a preferred embodiment of a non-volatile memory cell of the present invention
• FIG. 2 is a side cross section view of the preferred non-volatile memory cell
• FIG. 3 is an electrical diagram illustrating the electrical relationship of the structures of the preferred non-volatile memory cell
• FIG. 4 depicts a prior art non-volatile memory cell which uses a floating gate for an OTP application
• FIG. 5 is an electrical diagram showing a preferred embodiment of a latch circuit constructed with the NV memory cells of the present invention.
• FIG. 6 is a top down view of a preferred embodiment of a non-volatile memory cell of the present invention which uses variable coupling;
• FIG. 7 is an electrical diagram illustrating the electrical relationship of the structures of the preferred non-volatile memory cell using variable coupling.
• the present disclosure concerns a new type of non-volatile memory device structure (preferably single poly) that can be operated either as an OTP (one time programmable) or as an MTP (multiple time programmable) memory cell using variable capacitive coupling.
• the preferred device structure is fully compatible with advanced CMOS logic process, and would require, at the worst case, very minimal additional steps to implement.
• a unique aspect of the present device is that the floating gate of the memory cell structure is electrically coupled strongly through a variable number of S/D junctions of the transistor, whereas traditional single poly nonvolatile memory cells require either an additional interconnect layer to couple to the floating gate, or the floating gate has virtually none or minimal electrical coupling to any of the existing electrical signals.
• the coupling ratio can be more specific and precise. That is, by exactly controlling the coupling ratio (through areal means) the amount of charge, and thus the final programmed Vt, are directly proportional to the product of the coupling ratio and the drain voltage. It can be more precisely controlled such that the coupling ratio is dictated or designed by the desired programming threshold level (V t ) of the memory cell. This allows for a design that evolves easily into a multi-level version of an
• FIG. 1 illustrates the top view of the layout of a preferred structure used in the present invention.
• FIG. 2 illustrates a representative cross-sectional view of the device structure. It will be understood that these drawings are not intended to be set out to scale, and some aspects of the device have been omitted for clarity.
• the device includes a typical NMOS transistor 100 which is modified so that the gate (poly in a preferred embodiment) 110 of the device is not electrically connected to a voltage source.
• a drain 120 of the device is bent around and is preferably joined by an N-type well 130 that typically already exists in a conventional advanced CMOS process.
• the N- WeII 130 can be replaced with an n-type diffusion layer introduced so as to be beneath the poly floating gate.
• a conventional source region 125 is also utilized.
• the floating gate poly 110 is extended beyond a typical transistor channel region 135 and includes an overlap region 140 which overlaps an active region extending from the drain junction.
• the active region portion 141 that is surrounded by the N-WeII region serves as an effective capacitive coupling to the floating gate. Thus any voltage applied to the drain junction will be effectively coupled onto the floating gate.
• the floating gate can effectively acquire and have a high percentage of the value of the drain voltage.
• a key advantage of the preferred embodiment is that it is formed from same layers conventionally used to make active n- channel devices in a CMOS process.
• the poly (or metal as the case may be) gate layer is not interconnected with such other formed active devices or coupled to a gate signal.
• the other implants for the source/drain are also part of a CMOS conventional process.
• the invention can be integrated without any additional processing costs, because the only alteration is to an existing mask for each relevant layer of the wafer being processed.
• this device structure is to make the drain-to-gate coupling capacitor area on the sidewall of a trench. This will greatly reduce the area of the drain-to-gate coupling capacitor. This reduction in cell area may come at the expense of significantly increase the manufacturing process complexity. However, again, in applications where the invention is integrated with certain types of DRAM architectures (especially embedded types), it is possible to incorporate the conventional processing steps for such memories to avoid additional processing costs. Other techniques for coupling a voltage to the floating gate and achieving a desired coupling ratio will be apparent to those skilled in the art.
• floating gate is shown as a single polysilicon layer, it will be appreciated by skilled artisans that other materials could be used as well. In some applications for example it may be possible to exploit the formation of other structures/devices which while part of other main underlying logic/memory structures, can be exploited for purposes of making a floating gate of some kind. In this respect it should be noted that floating gates can typically be formed of a number of different materials, including through techniques in which impurities are implanted/diffused into a dielectric/insulating layer.
• the preferred embodiment depicts the NVM cell as part of a conventional lateral - planar FET structure on a substrate
• other geometries/architectures can be used, including non-planar structures.
• the invention could be used in SOI substrates, in thin film structures, at other levels of the device than the substrate, in multi-gate (FINFET type) orientations, and in vertical/non-planar configurations. In such latter instances the floating gate would be embedded and oriented vertically with respect to the substrate.
• the non- volatile device structure preferably has the physical features of a conventional I/O transistor implemented in an advanced CMOS logic process. At present, such I/O transistor is nominally operated at 3.3V but it will be understood that this value will change with successive generations of manufacturing.
• This type of I/O transistor typically has a threshold voltage of 0.5V to 0.7V, with a typical electrical gate oxide thickness of 7OA. With a drain coupling to floating gate ratio of 0.90, and a read drain voltage of 1.0V applied to the device, the floating gate will effectively be coupled with a voltage of about 0.90V. This is sufficient to turn on the un-programmed NMOS device 100, and a channel current can be detected by typical means of sense circuitry to identify the state of the device. It will be understood to those skilled in the art that the particular coupling ratio, read voltage, etc., will vary from application to application and can be configured based on desired device operating characteristics.
• the device is originally in a unprogrammed state, which in the preferred embodiment is characterized by a low resistance coupling between the source and drain through channel region 135. This means that the channel region 135 can be substantially uniform and current flow is reliable. While the preferred embodiment is shown in the form of a symmetric cell/channel, it will be understood that the invention could be used in non- symmetric forms such as shown in the aforementioned 20080186722 publication.
• the device To program the device into a programmed state, the device must be shut off by reducing carriers in the channel region, and increasing the threshold voltage. To do this a drain voltage of 6.0V can be applied and this will effectively couple a voltage of about 5.4V to the floating gate. This bias condition will placed the device into a channel hot electron injection regime. The electrons injected into the floating gate effectively increase the threshold voltage of the device. When a subsequent read voltage of 1.0V is applied again on the drain, the device does not conduct current due to its high threshold voltage, and this second state of the device is thus determined. As with the read characteristics, it will be understood to those skilled in the art that the particular coupling ratio, program voltage, etc., will vary from application to application and can be configured based on desired device operating characteristics.
• the prior art referred to above is primarily a one time programmable device, since there is no disclosed mechanism for removing the charge on the floating gate.
• some embodiments of the present invention can be made to be capable of multiple-time-programming.
• an erase operation can be introduced to remove or neutralize the electrons that have been injected into the floating gate.
• the mechanism for removing or neutralizing electrons is preferably through band-band tunneling hot hole injection from the other non-coupling junction 125 of the device.
• the preferred bias condition would be as followed: the non-coupling junction (source junction) is biased with 6V to cause the junction to initiate band-band tunneling current.
• the band-band tunneling current causes hot holes to be injected into the floating gate and neutralize the electrons that are stored on the floating gate.
• the coupling junction can be supplied with a negative voltage so that the floating gate is made more negative to cause higher band-band tunneling current across the source junction.
• additional protection can be implemented to ensure the OTP and MTP device have sufficient immunity against the loss of charge stored on the floating gate.
• the device can be configured into a paired latch 500 - as shown in FIG. 5 - where the data and its complement are stored into the latch, thus effectively doubling the margin in the stored data.
• a top device 510 couples a node 530 to a first voltage reference (Vcc) while a second bottom device 520 couples the node to a second voltage reference (Vss).
• Vcc first voltage reference
• Vss second voltage reference
• the top device 510 is programmed into a non-conductive state, thus ensuring that node 530 is pulled down by bottom device 520 to Vss, representing a first logical data value (0).
• the bottom device 520 is programmed into a non-conductive state, thus ensuring that node 530 is pulled up by top device 510 to Vcc, representing a second logical data value (1 ).
• Another useful advantage of the present preferred embodiment is that it is implemented with an NMOS device structure, whereas most traditional single-poly OTPs are commonly implemented with a PMOS device structure.
• NMOS device structure behaves similar to an EPROM device, i.e., the device is programmed into a non-conducting state from a conducting state.
• EPROM device i.e., the device is programmed into a non-conducting state from a conducting state.
• PMOS OTP devices - are programmed from a non-conducting state into a conducting state. This aspect of the invention thus can eliminate the need of an additional masking step that is commonly associated with a PMOS OTP device in order to make sure that PMOS device is in a non-conducting state coming out of the manufacturing fab.
• an NMOS device's programming mechanism with channel hot electrons injection is self-limiting, unlike that case of a PMOS with channel hot electron programming, the amount of energy consumption during programming is self-limited for this invention.
• the particular configuration of the floating gate is not critical. All that is required is that it be structurally and electrically configured to control channel conduction and also be capacitively coupled to an electrical source of charge carriers.
• the particular geometry can be varied in accordance with any desired layout or mask. In some instances it may be desirable to implement the floating gate as a multi-level structure for example.
• capacitive coupling is a function of the materials used, the invention allows for significant flexibility as the composition of the floating gate can also be varied as desired to accommodate and be integrated into a particular process.
• An array of cells constructed in accordance with the present teachings could include different shapes and sizes of floating gates so that cells having threshold cells could be created.
• the effective coupling ratio of the device 100 can be made different/varied between read, program and/or erase operations. That is, while not shown in FIGs. 1 , 2, the drain region 120 coupled to the floating gate could be partitioned into one or more separate sub-regions. This is shown in detail in FIGs. 6A and 6B. Each sub-region
• 121 , 122, etc. may be fabricated or controlled to have a different amount of overlap with the floating gate.
• differing types of performance can be achieved for read/program/erase operations. For example it may be desirable to have an ultra low power (but somewhat slower) program or erase operations. This can be achieved by making a coupling area for such first type of operation smaller than the nominal area used during a second type (read) operation.
• variable coupling geometry is done by altering a drain diffusion size (in a diffusion mask) and keeping a floating gate size constant
• the same effective result could be achieved by keeping a drain diffusion constant and altering a floating gate size.
• the floating gate region 122 could be reduced in size to achieve the same result.
• By adjusting floating gate sizes it then becomes possible to share diffusion regions as well, so that an adjacent floating gate 122' (for another cell) could be coupled to drain region 120.
• Other combinations of these techniques will be useable as well and can be selected based on design/performance requirements.
• the variable coupling aspects of the present invention can be used for both PMOS and NMOS OTP. Different coupling ratio options could also be used to impart different voltages on the floating gate, which has the potentially for multi-state storage, i.e., multi-level for an OTP.
• the programming voltage could be adjusted instead of course, so that for a given drain coupling, the programming voltage applied to a particular cell is adjusted to write a different state to the floating gate. Because the drain is coupled to the floating gate the variable programming voltage should be imparted to the floating gate. For example, a drain voltage could be adjusted to have 3, 4 or more different levels. This effectuates a different form of variable capacitive coupling that may be more complex from a write perspective but may be useful in some applications.
• a multi-level OTP variant for an NMOS implementation must take into account that NMOS is programmed to an off state, so a little off is very similar to very much off, unless one uses different level of floating gate voltages through different applied drain voltages to sense the state. In such circumstances, however, the different drain voltage could undesirably degrade the read disturb immunity, so there is a potential trade off here.
• Drain 1 can be set to have a coupling ratio (or overlap) which is some multiple (in this case preferably 2) of that of Drain 2.
• a program voltage which imparts Drain 1 with a voltage of 0 and Drain 2 with a voltage of 6 V would write a first state in the cell, based on a first amount of charge imparted to the gate. If instead all drains are programmed the charge added would be higher, thus corresponding to a second state, and so on.
• the preferable method of reading the state of the cell applies a read voltage on both Drain 1 and Drain 2 as seen in Table 2 below.
• the amount of cell current is then sensed, which current is inversely proportional to the amount of charge on the floating gate.
• the charge on the floating gate as noted above is a direct function of the amount of coupling applied during the programming.
• the state of 0, 1X, 2X and 3X in the cell can be detected by its relationship to the amount of read current.
• the read drain voltage is preferably selected to be on the order of 1 volt. This has the advantage of preventing any kind of read disturb or drain induced leakage contribution.
• the read can always be done on the Drain node with the highest coupling ratio, in our example, the 2X Drain. In such instances it may not be possible to differentiate between all 4 different states, but this may be a desirable trade off in some applications.
• any single one (or combination) of the drains is biased with a varying voltage over time to determine the coupled charge contribution from the collective overlaps.
• the drain is biased with an increasing voltage (from 0 to some target voltage sufficient to trigger the gate in the highest threshold state) with time until the threshold voltage is achieved or decoded within a certain time interval at a particular voltage level to identify the state of the cell.
• the particular range of read drain voltages will be dependent on the particular cell architecture, desired operating characteristics, etc. and can be determined by routine testing. Again in this embodiment may not be possible to differentiate between all 4 different states, but this may be a desirable trade off in some applications. Other examples for programming and reading the cell will be apparent to those skilled in the art.
• ratios are possible, of course, subject to the restriction that by selecting different ratios which are not multiples of 2, the sensing margin/differentiation may not be as great.
• a multi-bit cell may have 3 programmed drain couplings simply of ⁇ 0, Drain 1 , Drain 2 ⁇ thus ignoring ⁇ Drain 1 + Drain
• FIG. 6A While two separate coupling ratios are shown in FIG. 6A and three separate coupling ratios are shown in FIG. 6B, it will be understood that other partitionings and couplings could be implemented in accordance with the present teachings.
• FIG. 6B for example, 8 different programmed states can be achieved by using 3 different levels of charge coupling.
• different combinations of drains having coupling ratios of 1x, 2x and 4x can be combined, or some other set of ratios.
• other selections could be made with fewer logic states in exchange for higher margin between states.
• Other variations of the invention will be apparent to those skilled in the art.

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• 2008
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