JP5554714B2 - 可変結合を有する不揮発性プログラマブルメモリに組み込まれた集積回路 - Google Patents

可変結合を有する不揮発性プログラマブルメモリに組み込まれた集積回路 Download PDF

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JP5554714B2
JP5554714B2 JP2010534250A JP2010534250A JP5554714B2 JP 5554714 B2 JP5554714 B2 JP 5554714B2 JP 2010534250 A JP2010534250 A JP 2010534250A JP 2010534250 A JP2010534250 A JP 2010534250A JP 5554714 B2 JP5554714 B2 JP 5554714B2
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JP
Japan
Prior art keywords
drain region
region
floating gate
drain
gate
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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JP2010534250A
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English (en)
Japanese (ja)
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JP2011503905A5 (enExample
JP2011503905A (ja
Inventor
リウ，デイヴィッド
グロス，ジョン
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インヴェンサス・コーポレイション
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Priority claimed from US12/264,060 external-priority patent/US7787304B2/en
Application filed by インヴェンサス・コーポレイション filed Critical インヴェンサス・コーポレイション
Priority claimed from US12/271,695 external-priority patent/US7787295B2/en
Priority claimed from US12/271,647 external-priority patent/US7852672B2/en
Priority claimed from US12/271,666 external-priority patent/US8580622B2/en
Priority claimed from US12/271,680 external-priority patent/US7876615B2/en
Publication of JP2011503905A publication Critical patent/JP2011503905A/ja
Publication of JP2011503905A5 publication Critical patent/JP2011503905A5/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/687—Floating-gate IGFETs having more than two programming levels

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
JP2010534250A 2007-11-14 2008-11-14 可変結合を有する不揮発性プログラマブルメモリに組み込まれた集積回路 Expired - Fee Related JP5554714B2 (ja)

Applications Claiming Priority (17)

Application Number Priority Date Filing Date Title
US98786907P 2007-11-14 2007-11-14
US60/987,869 2007-11-14
US12/264,076 2008-11-03
US12/264,060 2008-11-03
US12/264,060 US7787304B2 (en) 2007-11-01 2008-11-03 Method of making integrated circuit embedded with non-volatile one-time-programmable and multiple-time programmable memory
US12/264,076 US7787309B2 (en) 2007-11-01 2008-11-03 Method of operating integrated circuit embedded with non-volatile one-time-programmable and multiple-time programmable memory
US12/264,029 2008-11-03
US12/264,029 US7782668B2 (en) 2007-11-01 2008-11-03 Integrated circuit embedded with non-volatile one-time-programmable and multiple-time programmable memory
US12/271,695 US7787295B2 (en) 2007-11-14 2008-11-14 Integrated circuit embedded with non-volatile multiple-time programmable memory having variable coupling
US12/271,647 2008-11-14
US12/271,666 2008-11-14
US12/271,680 2008-11-14
PCT/US2008/083697 WO2009065084A1 (en) 2007-11-14 2008-11-14 Integrated circuit embedded with non-volatile programmable memory having variable coupling
US12/271,647 US7852672B2 (en) 2007-11-14 2008-11-14 Integrated circuit embedded with non-volatile programmable memory having variable coupling
US12/271,695 2008-11-14
US12/271,666 US8580622B2 (en) 2007-11-14 2008-11-14 Method of making integrated circuit embedded with non-volatile programmable memory having variable coupling
US12/271,680 US7876615B2 (en) 2007-11-14 2008-11-14 Method of operating integrated circuit embedded with non-volatile programmable memory having variable coupling related application data

Publications (3)

Publication Number Publication Date
JP2011503905A JP2011503905A (ja) 2011-01-27
JP2011503905A5 JP2011503905A5 (enExample) 2012-03-08
JP5554714B2 true JP5554714B2 (ja) 2014-07-23

Family

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Family Applications (1)

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JP2010534250A Expired - Fee Related JP5554714B2 (ja) 2007-11-14 2008-11-14 可変結合を有する不揮発性プログラマブルメモリに組み込まれた集積回路

Country Status (2)

Country Link
JP (1) JP5554714B2 (enExample)
WO (1) WO2009065084A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9230814B2 (en) * 2011-10-28 2016-01-05 Invensas Corporation Non-volatile memory devices having vertical drain to gate capacitive coupling
US8975685B2 (en) * 2012-08-31 2015-03-10 Maxim Integrated Products, Inc. N-channel multi-time programmable memory devices
CN114300024B (zh) * 2021-12-29 2024-10-01 北京超弦存储器研究院 一种基于非易失性处理器的数据处理方法、装置及介质

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0521809A (ja) * 1991-07-15 1993-01-29 Matsushita Electric Works Ltd 半導体装置
US6965142B2 (en) * 1995-03-07 2005-11-15 Impinj, Inc. Floating-gate semiconductor structures
US5598367A (en) * 1995-06-07 1997-01-28 International Business Machines Corporation Trench EPROM
US6177703B1 (en) * 1999-05-28 2001-01-23 Vlsi Technology, Inc. Method and apparatus for producing a single polysilicon flash EEPROM having a select transistor and a floating gate transistor
JP2001358313A (ja) * 2000-06-14 2001-12-26 Hitachi Ltd 半導体装置
JP4170604B2 (ja) * 2001-04-18 2008-10-22 株式会社東芝 不揮発性半導体メモリ
JP2003197765A (ja) * 2001-12-28 2003-07-11 Texas Instr Japan Ltd 半導体装置およびその製造方法
JP4557950B2 (ja) * 2002-05-10 2010-10-06 株式会社東芝 不揮発性半導体記憶置
US7064978B2 (en) * 2002-07-05 2006-06-20 Aplus Flash Technology, Inc. Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
WO2004015764A2 (en) * 2002-08-08 2004-02-19 Leedy Glenn J Vertical system integration
US6920067B2 (en) * 2002-12-25 2005-07-19 Ememory Technology Inc. Integrated circuit embedded with single-poly non-volatile memory
JP2005038894A (ja) * 2003-07-15 2005-02-10 Sony Corp 不揮発性半導体メモリ装置、および、その動作方法
JP2005057106A (ja) * 2003-08-06 2005-03-03 Sony Corp 不揮発性半導体メモリ装置およびその電荷注入方法
TWI231039B (en) * 2004-04-30 2005-04-11 Yield Microelectronics Corp Non-volatile memory and its operational method

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Publication number Publication date
WO2009065084A1 (en) 2009-05-22
JP2011503905A (ja) 2011-01-27

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