WO2009060567A1 - データ転送制御装置、データ転送装置、データ転送制御方法及び再構成回路を用いた半導体集積回路 - Google Patents

データ転送制御装置、データ転送装置、データ転送制御方法及び再構成回路を用いた半導体集積回路 Download PDF

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Publication number
WO2009060567A1
WO2009060567A1 PCT/JP2008/003016 JP2008003016W WO2009060567A1 WO 2009060567 A1 WO2009060567 A1 WO 2009060567A1 JP 2008003016 W JP2008003016 W JP 2008003016W WO 2009060567 A1 WO2009060567 A1 WO 2009060567A1
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WO
WIPO (PCT)
Prior art keywords
data transfer
unit
transfer control
bus master
semiconductor integrated
Prior art date
Application number
PCT/JP2008/003016
Other languages
English (en)
French (fr)
Inventor
Kouichi Ishino
Takashi Morimoto
Koji Asai
Original Assignee
Panasonic Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corporation filed Critical Panasonic Corporation
Priority to US12/522,490 priority Critical patent/US20100042751A1/en
Priority to JP2009539939A priority patent/JP5373620B2/ja
Publication of WO2009060567A1 publication Critical patent/WO2009060567A1/ja

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types

Abstract

　低コストでメモリバンド幅の確保を行うことができる半導体集積回路を提供する。メモリバンド幅監視部１２１０がメモリバンド幅を算出し、メモリの使用状況を監視し、その使用状況に応じて、再構成部１１１０を、バスマスタ部としての論理部と各バスマスタがメモリにアクセスする際の一時バッファとをスケーラブルに構成するための情報を再構成制御部１１２０に出力する。再構成制御部１１２０が、その情報に従い再構成部１１１０を制御する。論理部に構成されるバスマスタ部は、データ記憶部１００２への高いアクセス優先度が割り当てられたバスマスタ部によるデータ記憶部へのアクセス要求が実行されていない場合であって、メモリバンド幅に空きがある場合に、その空き分のみを使用するバスマスタ部である。
PCT/JP2008/003016 2007-11-09 2008-10-24 データ転送制御装置、データ転送装置、データ転送制御方法及び再構成回路を用いた半導体集積回路 WO2009060567A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/522,490 US20100042751A1 (en) 2007-11-09 2008-10-24 Data transfer control device, data transfer device, data transfer control method, and semiconductor integrated circuit using reconfigured circuit
JP2009539939A JP5373620B2 (ja) 2007-11-09 2008-10-24 データ転送制御装置、データ転送装置、データ転送制御方法及び再構成回路を用いた半導体集積回路

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-291490 2007-11-09
JP2007291490 2007-11-09

Publications (1)

Publication Number Publication Date
WO2009060567A1 true WO2009060567A1 (ja) 2009-05-14

Family

ID=40625477

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/003016 WO2009060567A1 (ja) 2007-11-09 2008-10-24 データ転送制御装置、データ転送装置、データ転送制御方法及び再構成回路を用いた半導体集積回路

Country Status (3)

Country Link
US (1) US20100042751A1 (ja)
JP (1) JP5373620B2 (ja)
WO (1) WO2009060567A1 (ja)

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JP6713410B2 (ja) * 2016-11-21 2020-06-24 日立オートモティブシステムズ株式会社 電子制御装置
JP6810651B2 (ja) * 2017-04-24 2021-01-06 日立オートモティブシステムズ株式会社 電子制御装置、論理回路の制御方法
KR102559581B1 (ko) 2018-05-23 2023-07-25 삼성전자주식회사 재구성 가능 로직을 포함하는 스토리지 장치 및 상기 스토리지 장치의 동작 방법
CN112395245B (zh) * 2019-08-16 2023-04-28 上海寒武纪信息科技有限公司 处理器的访问装置、方法及计算机设备
CN112446473A (zh) * 2019-08-31 2021-03-05 上海寒武纪信息科技有限公司 数据处理装置和方法
JP2022040721A (ja) * 2020-08-31 2022-03-11 富士フイルムビジネスイノベーション株式会社 情報処理装置、及びプログラム

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Also Published As

Publication number Publication date
US20100042751A1 (en) 2010-02-18
JPWO2009060567A1 (ja) 2011-03-17
JP5373620B2 (ja) 2013-12-18

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