WO2007095080A8 - Memory circuit system and method - Google Patents
Memory circuit system and methodInfo
- Publication number
- WO2007095080A8 WO2007095080A8 PCT/US2007/003460 US2007003460W WO2007095080A8 WO 2007095080 A8 WO2007095080 A8 WO 2007095080A8 US 2007003460 W US2007003460 W US 2007003460W WO 2007095080 A8 WO2007095080 A8 WO 2007095080A8
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory
- circuits
- interface circuit
- host system
- circuit
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
Abstract
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DK07750307.6T DK2005303T3 (en) | 2006-02-09 | 2007-02-08 | Memory circuit system as well - method |
EP07750307A EP2005303B1 (en) | 2006-02-09 | 2007-02-08 | Memory circuit system and method |
AT07750307T ATE554447T1 (en) | 2006-02-09 | 2007-02-08 | MEMORY CIRCUIT SYSTEM AND METHOD |
KR1020147007335A KR101404926B1 (en) | 2006-02-09 | 2007-02-08 | Memory circuit system and method |
JP2008554369A JP5205280B2 (en) | 2006-02-09 | 2007-02-08 | Memory circuit system and method |
KR1020137029741A KR101429869B1 (en) | 2006-02-09 | 2007-02-08 | Memory circuit system and method |
KR1020087019582A KR101343252B1 (en) | 2006-02-09 | 2008-08-08 | memory circuit system and method |
Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
USNOTFURNISHED | 1995-09-15 | ||
US77241406P | 2006-02-09 | 2006-02-09 | |
US60/772,414 | 2006-02-09 | ||
US11/461,437 US8077535B2 (en) | 2006-07-31 | 2006-07-31 | Memory refresh apparatus and method |
US11/461,437 | 2006-07-31 | ||
US86562406P | 2006-11-13 | 2006-11-13 | |
US60/865,624 | 2006-11-13 |
Publications (3)
Publication Number | Publication Date |
---|---|
WO2007095080A2 WO2007095080A2 (en) | 2007-08-23 |
WO2007095080A3 WO2007095080A3 (en) | 2008-04-10 |
WO2007095080A8 true WO2007095080A8 (en) | 2008-05-22 |
Family
ID=38372014
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2007/003460 WO2007095080A2 (en) | 2006-02-09 | 2007-02-08 | Memory circuit system and method |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO2007095080A2 (en) |
Families Citing this family (36)
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US8089795B2 (en) | 2006-02-09 | 2012-01-03 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
US9542352B2 (en) | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
US20080082763A1 (en) | 2006-10-02 | 2008-04-03 | Metaram, Inc. | Apparatus and method for power management of memory circuits by a system or component thereof |
US9507739B2 (en) | 2005-06-24 | 2016-11-29 | Google Inc. | Configurable memory circuit system and method |
US7609567B2 (en) | 2005-06-24 | 2009-10-27 | Metaram, Inc. | System and method for simulating an aspect of a memory circuit |
US8397013B1 (en) | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
US8359187B2 (en) | 2005-06-24 | 2013-01-22 | Google Inc. | Simulating a different number of memory circuit devices |
US8244971B2 (en) | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
US9632929B2 (en) | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
US20100293343A1 (en) * | 2007-11-19 | 2010-11-18 | Perego Richard E | Scheduling based on turnaround event |
US8521979B2 (en) | 2008-05-29 | 2013-08-27 | Micron Technology, Inc. | Memory systems and methods for controlling the timing of receiving read data |
JP5292935B2 (en) * | 2008-06-16 | 2013-09-18 | 日本電気株式会社 | Memory module control method, memory module, and data transfer device |
US8289760B2 (en) | 2008-07-02 | 2012-10-16 | Micron Technology, Inc. | Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes |
US7855931B2 (en) * | 2008-07-21 | 2010-12-21 | Micron Technology, Inc. | Memory system and method using stacked memory device dice, and system using the memory system |
US8756486B2 (en) | 2008-07-02 | 2014-06-17 | Micron Technology, Inc. | Method and apparatus for repairing high capacity/high bandwidth memory devices |
US7978721B2 (en) * | 2008-07-02 | 2011-07-12 | Micron Technology Inc. | Multi-serial interface stacked-die memory architecture |
WO2010016817A1 (en) * | 2008-08-08 | 2010-02-11 | Hewlett-Packard Development Company, L.P. | Independently controllable and reconfigurable virtual memory devices in memory modules that are pin-compatible with standard memory modules |
CN102177550B (en) * | 2008-08-08 | 2014-03-12 | 惠普开发有限公司 | Independently controlled virtual memory devices in memory modules |
JP5400886B2 (en) * | 2008-08-13 | 2014-01-29 | ヒューレット−パッカード デベロップメント カンパニー エル.ピー. | Dynamic use of power-down mode in multi-core memory modules |
US8032804B2 (en) * | 2009-01-12 | 2011-10-04 | Micron Technology, Inc. | Systems and methods for monitoring a memory system |
US8572320B1 (en) | 2009-01-23 | 2013-10-29 | Cypress Semiconductor Corporation | Memory devices and systems including cache devices for memory modules |
US8683164B2 (en) * | 2009-02-04 | 2014-03-25 | Micron Technology, Inc. | Stacked-die memory systems and methods for training stacked-die memory systems |
US8364901B2 (en) * | 2009-02-13 | 2013-01-29 | Micron Technology, Inc. | Memory prefetch systems and methods |
WO2010148359A1 (en) | 2009-06-18 | 2010-12-23 | Cypress Semiconductor Corporation | Memory devices and systems including multi-speed access of memory modules |
US9123552B2 (en) | 2010-03-30 | 2015-09-01 | Micron Technology, Inc. | Apparatuses enabling concurrent communication between an interface die and a plurality of dice stacks, interleaved conductive paths in stacked devices, and methods for forming and operating the same |
JP4861497B2 (en) | 2010-05-31 | 2012-01-25 | 株式会社東芝 | Data storage device and memory adjustment method |
US8400808B2 (en) | 2010-12-16 | 2013-03-19 | Micron Technology, Inc. | Phase interpolators and push-pull buffers |
EP2664991A1 (en) | 2011-01-13 | 2013-11-20 | Fujitsu Limited | Memory controller and information processing device |
GB2488516A (en) * | 2011-02-15 | 2012-09-05 | Advanced Risc Mach Ltd | Using priority dependent delays to ensure that the average delay between accesses to a memory remains below a threshold |
US9679615B2 (en) * | 2013-03-15 | 2017-06-13 | Micron Technology, Inc. | Flexible memory system with a controller and a stack of memory |
US9171597B2 (en) | 2013-08-30 | 2015-10-27 | Micron Technology, Inc. | Apparatuses and methods for providing strobe signals to memories |
US10303235B2 (en) * | 2015-03-04 | 2019-05-28 | Qualcomm Incorporated | Systems and methods for implementing power collapse in a memory |
US10679722B2 (en) | 2016-08-26 | 2020-06-09 | Sandisk Technologies Llc | Storage system with several integrated components and method for use therewith |
KR20210131391A (en) * | 2019-02-22 | 2021-11-02 | 마이크론 테크놀로지, 인크. | Memory device interfaces and methods |
Family Cites Families (12)
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US4592019A (en) * | 1983-08-31 | 1986-05-27 | At&T Bell Laboratories | Bus oriented LIFO/FIFO memory |
US5798961A (en) * | 1994-08-23 | 1998-08-25 | Emc Corporation | Non-volatile memory module |
US5903500A (en) * | 1997-04-11 | 1999-05-11 | Intel Corporation | 1.8 volt output buffer on flash memories |
US6526484B1 (en) * | 1998-11-16 | 2003-02-25 | Infineon Technologies Ag | Methods and apparatus for reordering of the memory requests to achieve higher average utilization of the command and data bus |
DE10131939B4 (en) * | 2001-07-02 | 2014-12-11 | Qimonda Ag | Electronic circuit board with a plurality of housing-type housing semiconductor memories |
US6781911B2 (en) * | 2002-04-09 | 2004-08-24 | Intel Corporation | Early power-down digital memory device and method |
US7143298B2 (en) * | 2002-04-18 | 2006-11-28 | Ge Fanuc Automation North America, Inc. | Methods and apparatus for backing up a memory device |
KR100510521B1 (en) * | 2003-03-04 | 2005-08-26 | 삼성전자주식회사 | Double data rate synchronous dynamic random access memory semiconductor device |
US7143236B2 (en) * | 2003-07-30 | 2006-11-28 | Hewlett-Packard Development Company, Lp. | Persistent volatile memory fault tracking using entries in the non-volatile memory of a fault storage unit |
US7023700B2 (en) * | 2003-12-24 | 2006-04-04 | Super Talent Electronics, Inc. | Heat sink riveted to memory module with upper slots and open bottom edge for air flow |
US20050204111A1 (en) * | 2004-03-10 | 2005-09-15 | Rohit Natarajan | Command scheduling for dual-data-rate two (DDR2) memory devices |
US7079446B2 (en) * | 2004-05-21 | 2006-07-18 | Integrated Device Technology, Inc. | DRAM interface circuits having enhanced skew, slew rate and impedance control |
-
2007
- 2007-02-08 WO PCT/US2007/003460 patent/WO2007095080A2/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2007095080A2 (en) | 2007-08-23 |
WO2007095080A3 (en) | 2008-04-10 |
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