WO2009057003A1 - Transistor bipolaire à niveau de bruit thermique et de bruit de grenaille réduits - Google Patents

Transistor bipolaire à niveau de bruit thermique et de bruit de grenaille réduits Download PDF

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Publication number
WO2009057003A1
WO2009057003A1 PCT/IB2008/054124 IB2008054124W WO2009057003A1 WO 2009057003 A1 WO2009057003 A1 WO 2009057003A1 IB 2008054124 W IB2008054124 W IB 2008054124W WO 2009057003 A1 WO2009057003 A1 WO 2009057003A1
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WO
WIPO (PCT)
Prior art keywords
base
emitter
zone
bipolar transistor
semiconductor substrate
Prior art date
Application number
PCT/IB2008/054124
Other languages
English (en)
Inventor
Sönke HABENICHT
Original Assignee
Nxp B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp B.V. filed Critical Nxp B.V.
Publication of WO2009057003A1 publication Critical patent/WO2009057003A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/7302—Bipolar junction transistors structurally associated with other devices
    • H01L29/7304—Bipolar junction transistors structurally associated with other devices the device being a resistive element, e.g. ballasting resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors

Definitions

  • the invention relates to a bipolar transistor, in particular to a vertical bipolar transistor, having a base and emitter zone in a semiconductor substrate.
  • Bipolar transistors of the type specified are known from the prior art where these exhibit noisy behavior.
  • Noise in electronic components constitutes a fluctuation in the current and voltage behavior and forms a lower limit for the signal level which can still be processed by a corresponding electronic component.
  • the noise behavior therefore restricts the area of usage of the electronic function and low-noise behavior therefore results in a greater spectrum of usage of the electronic component.
  • Shot noise originates from the statistical energy distribution of the charge carriers of a component and is therefore always associated with a current flow whose magnitude also determines the magnitude of the shot noise level.
  • Flicker noise or so-called 1/f noise originates from traps which capture charge carriers and release them again. This contribution is therefore correlated with impurities and defects in the crystal pattern of the electronic component.
  • Thermal noise is formed in the ohmic resistances of electronic components as a result of the thermal electron motion. This contribution is therefore proportional to the temperature of the component but independent of current since the thermal energy of the charge carriers is substantially higher than the drift energy of the charge carriers.
  • Popcorn noise is caused by sharp variations in the current flow which originate from impurities such as, for example, metal ions. This effect is exacerbated at high voltages and low frequencies.
  • Flicker noise and popcorn noise can be primarily reduced by high-quality processes with few impurities and defect-free circuits but are only slightly dependent or not dependent at all on the type of construction and the design of the component.
  • Shot noise and thermal noise on the other hand can be influenced by special constructions in the design of the component. In bipolar transistors of the type specified initially this is in particular the base bulk resistance and the base control current. Whereas the base bulk resistance primarily influences the thermal contribution to the noise, the level of the small-signal current gain is primarily important for minimizing the shot noise.
  • a low base bulk resistance results in low thermal noise whilst a high small-signal current gain results in a lower base control current and therefore a low shot noise level.
  • the patent US 5,723,897 describes a so-called multi- emitter structure to lower the base resistance and therefore the thermal noise level.
  • the design described allows this reduction but has no influence on the shot noise level which is primarily promoted by a low base control current.
  • the design used significantly reduces the emitter area and thus leads to increased current-crowding and injection behavior of the transistor which reduces the current gain and therefore significantly increases the base control current and the shot noise level.
  • the patent US 5,455,449 primarily describes a bipolar transistor which increases the effective active area of the transistor by means of its mesh structure of base terminals and thus allows better surface usage of the silicon surface.
  • a side effect, as described in the patent, is that the thermal noise is reduced as a result of the lowering of the base resistance.
  • the patent does not describe which technical parameters - the effective base length under the emitter - determine this reduction. It is not possible to optimize this base length in their approach, since they would thereby further significantly reduce the surface usage of the transistor - however this is described as the major advantage of the invention in their patent specification. They also merely describe the lowering of the thermal noise level as a result of the reduction in the effective base resistance. The shot noise level which is determined by the base control current is not optimized.
  • the emitter zone is incorporated in the base zone in such a manner that the emitter zone and the base zone are arranged in a regularly recurrent manner in the semiconductor substrate.
  • the advantage of the invention can be seen in that as a result of the periodic arrangement of emitter and base regions, the thermal noise level is reduced significantly as a result of an appreciable reduction in the base bulk resistance, especially in the small signal range at low collector currents in which the spreading resistance of the base extending far below the emitter zone is lowered.
  • the shot noise level is also reduced significantly due to appreciable homogenization of the emitter current density and the associated suppressing of current crowding and injection effects.
  • the bipolar transistor according to the invention reduces the noise level without introducing additional mask or process steps.
  • the invention can easily be applied to any fabrication of bipolar transistors and is merely limited by the minimum structure widths used in the respective process.
  • the bipolar transistor is capable of achieving a low-noise product without any appreciable investment in defect-free process steps. This makes it possible to process components having increasingly specifications in significantly more cost-effective processes than hitherto.
  • the bipolar transistor is scalable in its size so that the corresponding design can be scaled periodically in different sizes to achieve different transistor specifications. Components having corresponding noise properties can thus be constructed in different sizes.
  • a low base bulk resistance and a high small-signal current gain which is constant over a broad parameter space is achieved by the bipolar transistor according to the invention.
  • the base bulk resistance can be reduced by means of the base triggering of the emitter having the shortest possible path whilst for optimizing the small-signal current gain it is possible to maximize the base-emitter edge length and thereby suppress current-crowding and injection effects with increasing current density in the emitter for a higher parameter space.
  • the invention provides a scalable solution which is capable of implementing various electrical transistor specifications such as, for example, various maximum currents IC, breakdown voltages BVCEO or saturation voltages VCEsat. In general, this is implemented in discrete and integrated transistors by scaling the magnitude of the electrical function.
  • a design which achieves a low noise level is also suitably scalable for implementing these specifications so that individually tuned solutions can be provided for various functional sizes.
  • the base zone is incorporated in the semiconductor substrate in a trough shape.
  • the base zone is doped with the result that the base bulk resistance is further reduced.
  • the emitter zone is doped.
  • the emitter zone is incorporated in the form of a structure comprising periodic structures - such as, for examples, stripes, rings, rectangles, triangles or other polygons such that the base doping is guided in periodic contact regions between the emitter zones to the semiconductor surface. From these contact regions the base and emitter potential is guided to the bond pads by a metallization following the contact surface.
  • the magnitude of the base bulk resistance is substantially dependent on the periodicity and the spacing of the base zones between the periodic emitter structures.
  • the technically attainable minimum of the spacing of the base contact holes is therefore dependent on the capability of the process architectures used to produce small structures, in this case holes and feed-throughs in structuring layers.
  • the technical progress in photolithography and the specification of the lithographic technique used in the respective process substantially determines the lower limit of the base bulk resistance.
  • the depth of penetration of the emitter zone in the semiconductor substrate is lower than the depth of penetration of the base zone in the semiconductor substrate.
  • Fig. 1 shows a bipolar transistor according to prior art
  • Fig. 2 shows a bipolar transistor according to the present invention
  • Fig. 3 to 4 show further embodiments of the present invention.
  • FIG. 1 shows the bipolar transistor 100 from the prior art.
  • Base and emitter zones 10, 11 are incorporated in a trough shape in the weakly doped semiconductor substrate 12.
  • the collector region 13 is either mediated via the semiconductor substrate 12 or achieved by a deeply embedded sub-collector in the semiconductor substrate 12.
  • the base bulk resistance 14 - minus the metallic lead-in on the surface 15 of the bipolar transmitter 100 - is now determined by the spreading resistance of the base zone 11 in the bipolar transmitter 100. This is determined by the doping profile of the base zone 11, the depth of the inserted base and emitter zone 10, 11 and the average range of the base space charge zone under the emitter zone 10 among the respective working parameters of the transmitter 100.
  • the magnitude of the small-signal current gain is determined by the thickness and the concentration profile of the remaining base doping layer under the emitter zone 10. The smaller the thickness, the greater is the small- signal current gain.
  • the constant nature of the small-signal gain over a broad parameter, say current/voltage range, is mediated by the emitter surface 16 and the base-emitter edge length 17 which is proportional to the number of edges of the emitter profile in this cross- section.
  • FIG. 2 shows a first embodiment of a bipolar transistor 100 according to the invention.
  • the emitter zone 11 is incorporated in the base zone 10 layer in the form of a periodic structure in such a manner that at regular intervals the base doping is used for contacting at the surface 15. This regular arrangement of base and emitter surfaces 16, 17,
  • the base bulk resistance 14 is significantly reduced since the average spreading length of the base spreading resistance is significantly reduced.
  • the base- emitter edge length 17 is significantly increased. This minimizes current-crowding and injection effects and results in a constant current gain over higher current/voltage ranges.
  • FIG. 3 shows a view in a further preferred embodiment.
  • the base zone 10 is inserted in the semiconductor substrate 12 in a trough shape
  • the emitter zone 11 is inserted in the base zone 10 in the form of a net-like structure 19 so that the base doping extends to the surface 15 in periodic contact regions.
  • these contact surfaces 19 are surrounded by emitter-doped region in both dimensions of the surface 15.
  • each base contact region supplies a concentric emitter surface 21 around the base contact region. From these contact surface 21 the base and emitter position is guided to the bond pads via a metallization following the contact surface.
  • either a finger-shaped structure or a full-surface contacting of the emitter can be provided by means of a multiple-layer metallization technique.
  • the magnitude of the base bulk resistance 14 is substantially dependent on the periodicity and the spacing of the base zones 10.
  • the technically attainable minimum of the spacing of the base contact holes is therefore dependent on the capability of the process architectures used to produce small structures, in this case holes and feed-throughs in structuring layers.
  • the technical progress in photolithography and the specification of the lithographic technique used in the respective process substantially determines the lower limit of the base bulk resistance 14.
  • Figure 4 show a view of another embodiment of the invention described.
  • the emitter zone 11 is incorporated in the form of a structure comprising periodic structures - such as, for examples, stripes, rings, rectangles, triangles or other polygons such that the base doping is guided in periodic contact regions 22 between the emitter zones 11 to the semiconductor surface 15. From these contact regions the base and emitter potential is guided to the bond pads by a metallization following the contact surface.
  • the magnitude of the base bulk resistance 14 is substantially dependent on the periodicity and the spacing of the base zones 10 between the periodic emitter structures.
  • the technically attainable minimum of the spacing of the base contact holes is therefore dependent on the capability of the process architectures used to produce small structures, in this case holes and feed-throughs in structuring layers. In this case, the technical progress in photolithography and the specification of the lithographic technique used in the respective process substantially determines the lower limit of the base bulk resistance 14.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

L'invention concerne un transistor bipolaire (100) qui possède une zone d'émission et une zone de base (10, 11) dans un substrat semi-conducteur (12). Afin de minimiser simultanément le bruit thermique et le bruit de grenaille, l'invention propose que la zone d'émission (10) et la zone de base (11) soient disposées d'une manière régulièrement récurrente dans le substrat semi-conducteur (12).
PCT/IB2008/054124 2007-11-01 2008-10-08 Transistor bipolaire à niveau de bruit thermique et de bruit de grenaille réduits WO2009057003A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP07119823.8 2007-11-01
EP07119823 2007-11-01

Publications (1)

Publication Number Publication Date
WO2009057003A1 true WO2009057003A1 (fr) 2009-05-07

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Application Number Title Priority Date Filing Date
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5958864A (ja) * 1982-09-28 1984-04-04 Fujitsu Ltd 半導体装置の製造方法
EP0126611A2 (fr) * 1983-05-16 1984-11-28 Fujitsu Limited Résistance thermique dans les dispositifs semi-conducteurs
EP0716456A1 (fr) * 1994-12-05 1996-06-12 Sharp Kabushiki Kaisha Transistor de puissance comprenant plusieurs transistors unitaires
US5723897A (en) * 1995-06-07 1998-03-03 Vtc Inc. Segmented emitter low noise transistor
US20020024114A1 (en) * 2000-06-05 2002-02-28 Kazuhisa Sakamoto Semiconductor device
US20020135046A1 (en) * 2001-03-26 2002-09-26 Winbond Electronics Corp. Bipolar junction transistor with high ESD robustness and low load-capacitance
EP1432041A2 (fr) * 2002-12-17 2004-06-23 STMicroelectronics S.r.l. Transitor bipolaire à courant latéral et émetteur ayant un rapport perimètre/surface élevé
US20060006498A1 (en) * 2004-07-06 2006-01-12 Ranadeep Dutta Bipolar transistor with geometry optimized for device performance, and method of making same

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5958864A (ja) * 1982-09-28 1984-04-04 Fujitsu Ltd 半導体装置の製造方法
EP0126611A2 (fr) * 1983-05-16 1984-11-28 Fujitsu Limited Résistance thermique dans les dispositifs semi-conducteurs
EP0716456A1 (fr) * 1994-12-05 1996-06-12 Sharp Kabushiki Kaisha Transistor de puissance comprenant plusieurs transistors unitaires
US5723897A (en) * 1995-06-07 1998-03-03 Vtc Inc. Segmented emitter low noise transistor
US20020024114A1 (en) * 2000-06-05 2002-02-28 Kazuhisa Sakamoto Semiconductor device
US20020135046A1 (en) * 2001-03-26 2002-09-26 Winbond Electronics Corp. Bipolar junction transistor with high ESD robustness and low load-capacitance
EP1432041A2 (fr) * 2002-12-17 2004-06-23 STMicroelectronics S.r.l. Transitor bipolaire à courant latéral et émetteur ayant un rapport perimètre/surface élevé
US20060006498A1 (en) * 2004-07-06 2006-01-12 Ranadeep Dutta Bipolar transistor with geometry optimized for device performance, and method of making same

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