WO2009041471A1 - 半導体記憶装置 - Google Patents

半導体記憶装置 Download PDF

Info

Publication number
WO2009041471A1
WO2009041471A1 PCT/JP2008/067249 JP2008067249W WO2009041471A1 WO 2009041471 A1 WO2009041471 A1 WO 2009041471A1 JP 2008067249 W JP2008067249 W JP 2008067249W WO 2009041471 A1 WO2009041471 A1 WO 2009041471A1
Authority
WO
WIPO (PCT)
Prior art keywords
power supply
potential
word line
storage device
semiconductor storage
Prior art date
Application number
PCT/JP2008/067249
Other languages
English (en)
French (fr)
Inventor
Koichi Takeda
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to JP2009534344A priority Critical patent/JPWO2009041471A1/ja
Publication of WO2009041471A1 publication Critical patent/WO2009041471A1/ja

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Static Random-Access Memory (AREA)

Abstract

半導体記憶装置において、ＳＲＡＭセルの電源電位を保持しつつ、読み出しマージン及び書き込みマージンを増加させる。半導体記憶装置は、ＳＲＡＭセル１１からなるＳＲＡＭセルアレー１００と、行アドレスに対応するワード線のそれぞれに対して設けられ、ワード線を活性化するように構成されたワード線ドライバ１４と、ワード線ドライバ１４の電源電位を低電位と高電位との間で切り換えるように構成された電源セレクタ１５と、列アドレスに対応するビット線対のそれぞれに対して設けられたラッチ型のセンスアンプ１２と、を備える。読み出し動作時に、電源セレクタ１５がワード線ドライバ１４の電源電位を低電位とした後、センスアンプ１２は検出した電位差を自身に対する活性化信号に同期して増幅し、電源セレクタ１５はその活性化信号に同期してワード線ドライバ１４の電源電位を低電位から高電位に切り換える。
PCT/JP2008/067249 2007-09-25 2008-09-25 半導体記憶装置 WO2009041471A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009534344A JPWO2009041471A1 (ja) 2007-09-25 2008-09-25 半導体記憶装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-247573 2007-09-25
JP2007247573 2007-09-25

Publications (1)

Publication Number Publication Date
WO2009041471A1 true WO2009041471A1 (ja) 2009-04-02

Family

ID=40511354

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/067249 WO2009041471A1 (ja) 2007-09-25 2008-09-25 半導体記憶装置

Country Status (2)

Country Link
JP (1) JPWO2009041471A1 (ja)
WO (1) WO2009041471A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014041668A (ja) * 2012-08-21 2014-03-06 Fujitsu Semiconductor Ltd 半導体記憶装置及び半導体記憶装置の制御方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006040466A (ja) * 2004-07-29 2006-02-09 Renesas Technology Corp 半導体記憶装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006040466A (ja) * 2004-07-29 2006-02-09 Renesas Technology Corp 半導体記憶装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014041668A (ja) * 2012-08-21 2014-03-06 Fujitsu Semiconductor Ltd 半導体記憶装置及び半導体記憶装置の制御方法
US9013914B2 (en) 2012-08-21 2015-04-21 Fujitsu Semiconductor Limited Semiconductor memory device and method for controlling semiconductor memory device

Also Published As

Publication number Publication date
JPWO2009041471A1 (ja) 2011-01-27

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