WO2009041102A1 - 位相比較器およびそれを用いたクロック・データ再生回路 - Google Patents

位相比較器およびそれを用いたクロック・データ再生回路 Download PDF

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Publication number
WO2009041102A1
WO2009041102A1 PCT/JP2008/057745 JP2008057745W WO2009041102A1 WO 2009041102 A1 WO2009041102 A1 WO 2009041102A1 JP 2008057745 W JP2008057745 W JP 2008057745W WO 2009041102 A1 WO2009041102 A1 WO 2009041102A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
phase
pulse
regenerative
generating means
Prior art date
Application number
PCT/JP2008/057745
Other languages
English (en)
French (fr)
Inventor
Hidemi Noguchi
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to JP2009534205A priority Critical patent/JP5062260B2/ja
Publication of WO2009041102A1 publication Critical patent/WO2009041102A1/ja

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Manipulation Of Pulses (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

　識別手段は、入力信号をクロック信号のタイミングで識別することにより再生信号を生成し、再生信号を調整可能な位相で出力する。誤差パルス生成手段は、入力信号と識別手段から出力された再生信号との位相差に応じたパルス幅を有する誤差パルス信号を生成する。リファレンスパルス生成手段は、誤差パルス生成手段で生成される誤差パルス信号に対応し、一定のパルス幅を有するリファレンスパルス信号を生成する。差分信号生成手段は、誤差パルス信号とリファレンスパルス信号の差分をとることにより、位相比較の結果を示す位相比較信号を生成する。位相調整手段は、識別手段が再生信号を出力する位相を調整する。
PCT/JP2008/057745 2007-09-27 2008-04-22 位相比較器およびそれを用いたクロック・データ再生回路 WO2009041102A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009534205A JP5062260B2 (ja) 2007-09-27 2008-04-22 位相比較器およびそれを用いたクロック・データ再生回路

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007251123 2007-09-27
JP2007-251123 2007-09-27

Publications (1)

Publication Number Publication Date
WO2009041102A1 true WO2009041102A1 (ja) 2009-04-02

Family

ID=40511004

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/057745 WO2009041102A1 (ja) 2007-09-27 2008-04-22 位相比較器およびそれを用いたクロック・データ再生回路

Country Status (2)

Country Link
JP (1) JP5062260B2 (ja)
WO (1) WO2009041102A1 (ja)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0918307A (ja) * 1995-06-30 1997-01-17 Nec Corp 位相比較器
JPH10112639A (ja) * 1996-10-04 1998-04-28 Matsushita Electric Ind Co Ltd 位相比較器
JPH11112335A (ja) * 1997-10-08 1999-04-23 Nec Corp 位相比較回路並びにこれを用いた位相同期ループ回路及びシリアル―パラレル変換回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0918307A (ja) * 1995-06-30 1997-01-17 Nec Corp 位相比較器
JPH10112639A (ja) * 1996-10-04 1998-04-28 Matsushita Electric Ind Co Ltd 位相比較器
JPH11112335A (ja) * 1997-10-08 1999-04-23 Nec Corp 位相比較回路並びにこれを用いた位相同期ループ回路及びシリアル―パラレル変換回路

Also Published As

Publication number Publication date
JPWO2009041102A1 (ja) 2011-01-20
JP5062260B2 (ja) 2012-10-31

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