WO2009005257A2 - Procédé de fabrication d'un jeu de del - Google Patents

Procédé de fabrication d'un jeu de del Download PDF

Info

Publication number
WO2009005257A2
WO2009005257A2 PCT/KR2008/003728 KR2008003728W WO2009005257A2 WO 2009005257 A2 WO2009005257 A2 WO 2009005257A2 KR 2008003728 W KR2008003728 W KR 2008003728W WO 2009005257 A2 WO2009005257 A2 WO 2009005257A2
Authority
WO
WIPO (PCT)
Prior art keywords
lead frame
frame strip
mold
led chips
dummy
Prior art date
Application number
PCT/KR2008/003728
Other languages
English (en)
Other versions
WO2009005257A3 (fr
Inventor
Jung Hoo Seo
Do Hyung Kim
Moon Ho Cho
Min Gyu Jeon
Original Assignee
Seoul Semiconductor Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seoul Semiconductor Co., Ltd. filed Critical Seoul Semiconductor Co., Ltd.
Publication of WO2009005257A2 publication Critical patent/WO2009005257A2/fr
Publication of WO2009005257A3 publication Critical patent/WO2009005257A3/fr

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
    • B29C45/14—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles
    • B29C45/14639—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components
    • B29C45/14655—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components connected to or mounted on a carrier, e.g. lead frame
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
    • B29C45/17—Component parts, details or accessories; Auxiliary operations
    • B29C45/26—Moulds
    • B29C45/2608—Mould seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations

Definitions

  • the present invention relates to a method for manufacturing light emitting diode
  • LED packages and more particularly, to a method for manufacturing LED packages based on a batch encapsulation process in which a plurality of encapsulation members are simultaneously formed to protect LED chips disposed in respective LED packages in manufacturing the plurality of LED packages on a lead frame strip.
  • LEDs light emitting diodes
  • the LEDs are manufactured in a package structure, generally called an "LED package", in which an LED chip is mounted.
  • the LED package is configured to emit light upon application of an electric current from an exterior power source.
  • PCB printed circuit board
  • LED package wherein an LED chip is mounted on a conductive pattern of a PCB to receive an electric current supplied from the exterior
  • a lead frame type LED package wherein the electric current is applied through a lead frame.
  • a plurality of LED chips are formed on a single large PCB and encapsulation members are then provided to cover the plurality of LED chips, followed by cutting the PCB into a plurality of individual LED packages.
  • a plurality of LED chips are mounted at several locations on a plate-shaped lead frame strip which has a hole pattern for defining a plurality of lead frames, and encapsulation members and/or housings are then formed to cover the LED chips, followed by cutting the lead frame strip to provide a plurality of LED packages.
  • the applicant of the present invention has developed a technique for forming a plurality of encapsulation members in a batch process.
  • this technique called "transfer molding”
  • an epoxy tablet is liquefied via application of pressure and heat, and is then simultaneously supplied around each of LED chips located at several locations on a PCB.
  • the present invention has been made in view of the above problems of the conventional technique, and an object of the present invention is to provide a method for manufacturing LED packages based on batch formation of a plurality of encapsulation members on a lead frame strip with pattern-holes closed.
  • the above and other objects of the present invention can be achieved by the provision of a method for manufacturing LED packages, including: preparing a lead frame strip having a plurality of lead frames defined by pattern-holes and connected to each other; mounting LED chips on predetermined regions of the lead frame strip; disposing a dummy frame on the lead frame strip to overlap each other, the dummy frame closing the pattern-holes while exposing the predetermined regions of the lead frame strip; positioning the lead frame strip overlapping the dummy frame inside a mold; and simultaneously encapsulating the LED chips located on the predetermined regions of the lead frame strip by injecting a liquefied resin into the mold.
  • the lead frame strip may be formed with housings including cavities each surrounding the corresponding predetermined region, and in the encapsulating of the LED chips, the liquefied resin injected into the mold may fill the cavities to encapsulate the LED chips located inside the respective cavities.
  • the dummy frame may be a plate-shaped frame having exposure holes fitted onto the housings to expose the predetermined regions.
  • the mold may be configured to define a runner communicating with the cavities between the mold and the dummy frame.
  • the mold may include a plurality of molding shapes determining shapes of encapsulation members which encapsulate the LED chips.
  • the resin may be a silicone resin.
  • Fig. 1 is a plan view illustrating a single lead frame strip on which LED packages are formed
  • Fig. 2 is a cross-sectional view taken along line I-I in Fig. 1;
  • FIGs. 3 to 6 are sectional views illustrating a batch process of encapsulating LED chips mounted on plural regions of a lead frame strip with a resin
  • FIG. 7 is views of exemplary dummy frames placed to overlap the lead frame strip for the batch process of encapsulating LED chips with a liquid resin.
  • Fig. 1 is a plan view illustrating a single lead frame strip on which LED packages are formed.
  • Fig. 2 is a cross-sectional view taken along line I-I in Fig. 1.
  • a lead frame strip 10 has a substantially plate-shaped structure and is formed with a plurality of pattern-holes 12. Further, a plurality of LED packages 20 are integrated with the lead frame strip 10. The pattern-holes 12 define lead frames 14, which will be cut from the lead frame strip 10. The lead frame strip 10 is cut to constitute a portion of a separate LED package 20.
  • the LED package 20 includes a housing 22 which supports the lead frame 14.
  • the housing 22 has a cavity 22a, which accommodates the corresponding one of LED chips 24 mounted on plural regions of the lead frame strip 10.
  • each of the cavities 22a may accommodate plural LED chips 24.
  • the LED chip 24 is mounted on a single lead frame 14, which is electrically wired to other adjacent lead frames 14 via boding wires. By cutting the respective lead frames 14 at predetermined locations from the lead frame strip 10, the respective LED packages 20 are separated from the lead frame strip 10.
  • encapsulation members 26 are formed inside the cavities
  • the encapsulation members 26 are simultaneously formed by injecting a liquid resin into a mold, which will be described below in detail. Next, the method for simultaneously forming the encapsulation members 26 will be described in detail with reference to Figs. 3 to 6.
  • a plate-shaped lead frame strip 10 is prepared.
  • the lead frame strip 10 has LED chips 24 mounted on predetermined regions thereof and hous ings 22 each having a cavity 22a for accommodating the corresponding LED chip 24.
  • the lead frame strip 10 is formed with a plurality of pattern-holes 12, and includes a plurality of lead frames 14 which are connected to each other and have predetermined shapes defined by the pattern-holes 12.
  • a plate-shaped dummy frame 30 is positioned on the top of the lead frame strip 10 to overlap each other.
  • the dummy frame 30 includes exposure holes 32, which will be fitted onto the housings 22 such that the cavities 22a of the housings 22 can be exposed upward through the exposure holes 32, respectively.
  • the encapsulation member it can be contemplated to allow the encapsulation member to act as the housing instead of providing the housing 22, and in this case, the exposure holes 32 expose the plural regions of the lead frame strip 10 on which the LED chips 24 are mounted.
  • the exposure hole 32 has a rectangular shape corresponding to an outer shape of the housing 22, as shown in Fig. 7 (a). However, when the housing 22 has a circular shape 22, the exposure hole 32 may also have a circular shape as shown in Fig. 7 (b). Further, the exposure holes 32 may have various geometrical shapes corresponding to the shapes of the housings 22. While overlapping the lead frame strip 10, the dummy frame 30 entirely closes the plurality of pattern-holes 12 formed on the lead frame strip 10.
  • the lead frame strip 10 is placed inside a mold 40 used for molding encapsulation members 26 (see Fig. 2).
  • the mold 40 may be composed of an upper mold 42 and a lower mold 44 which can be open or closed by a certain drive means. In a closed state, the mold 40 defines a space for accommodating the dummy frame 30 and the lead frame strip 10 which overlap each other.
  • the shape and size of the space defined inside the mold 40 are determined by the shapes and sizes of the lead frame strip 10, dummy frame 30, and housings 22.
  • the upper mold 42 is formed with substantially semicircular molding shapes 422 which will determine respective shapes of the encapsulation members 26. Further, a runner 424 is provided between the upper mold 42 and the dummy frame 30 and communicates with all spaces defined between the molding shapes and the cavities 22a. The runner 424 communicates with a resin injection port 425 formed through the upper mold 42.
  • the encapsulation members 26 are formed inside the cavities 22a with a liquid resin, preferably, a silicone resin, as shown in Fig. 6.
  • a liquid resin preferably, a silicone resin
  • the silicone resin is liquefied by heat and injected into the mold 40 through the resin injection port 425.
  • the liquid resin is supplied to respective predetermined regions on the lead frame strip 10, on which the LED chips 24 are located, through the runner 424, and fills the cavities 22a, so that the liquid resin is formed into semicircular shapes by the molding shapes 422.
  • the encapsulation members 26 are formed as shown in Figs. 1 and 2.
  • the upper mold 42 and/or the lower mold 44 are shifted to open the mold 40, and the lead frame strip 10 with the plural encapsulation members 26 covering the respective LED chips 24 is removed from the mold 40.
  • the lead frames 14 of the lead frame strip 10 are cut at predetermined locations, thereby providing LED packages, each of which has two lead frames 14.
  • the LED chip 24 is mounted on one of the two lead frames 14 and is encapsulated by the encapsulation member 26.
  • the encapsulation members 26 are simultaneously formed by a batch encapsulation process using the dummy frame 30 as described above.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

Procédé de fabrication de jeux de DEL selon un procédé d'encapsulation par lots dans lequel une pluralité d'éléments d'encapsulation sont simultanément formés pou protéger des puces de DEL dans les jeux de DEL lors de leur fabrication sur une bande de grille de connexion. Le procédé consiste: à réaliser une bande de grille de connexion comportant une pluralité de grilles de connexion définies par des motifs de trous et connectées les unes aux autres; à monter des puces de DEL en des points prédéterminés de la bande de grille de connexion; à disposer un faux cadre sur la bande de grille de connexion en faisant se chevaucher ces deux éléments, le faux cadre fermant les motifs de trous tout en exposant des points prédéterminés de la bande de grille de connexion; à positionner la bande de grille de connexion chevauchant le faux cadre dans un moule; et simultanément à encapsuler les puces de DEL situées en des points prédéterminés de la bande de grille de connexion par injection d'une résine liquéfiée dans le moule.
PCT/KR2008/003728 2007-06-29 2008-06-27 Procédé de fabrication d'un jeu de del WO2009005257A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020070065097A KR101380385B1 (ko) 2007-06-29 2007-06-29 일괄 봉지 기술을 이용하는 ｌｅｄ 패키지 제조방법
KR10-2007-0065097 2007-06-29

Publications (2)

Publication Number Publication Date
WO2009005257A2 true WO2009005257A2 (fr) 2009-01-08
WO2009005257A3 WO2009005257A3 (fr) 2009-03-05

Family

ID=40226646

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2008/003728 WO2009005257A2 (fr) 2007-06-29 2008-06-27 Procédé de fabrication d'un jeu de del

Country Status (3)

Country Link
KR (1) KR101380385B1 (fr)
TW (1) TWI451594B (fr)
WO (1) WO2009005257A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104290253A (zh) * 2014-09-04 2015-01-21 瑞安市明光灯饰有限公司 Led灯条管道加工机

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR200488998Y1 (ko) * 2014-09-02 2019-04-15 네이버비즈니스플랫폼 주식회사 실내 지도 구축 장치
KR102172632B1 (ko) * 2015-06-30 2020-11-03 삼성전기주식회사 반도체 패키지 모듈 제조장치 및 제조방법

Citations (4)

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Publication number Priority date Publication date Assignee Title
JPS62290156A (ja) * 1986-06-09 1987-12-17 Kyocera Corp 半導体素子収納用パツケ−ジの製造法
US5828000A (en) * 1996-11-14 1998-10-27 Fujitsu Limited Semiconductor device with heat radiating plate and positioning dummy lead and lead frame therefor
KR20050084080A (ko) * 2002-12-06 2005-08-26 크리, 인코포레이티드 복합 리드프레임 ｌｅｄ 패키지 및 그 제조 방법
KR20060002282A (ko) * 2004-07-01 2006-01-09 서울반도체 주식회사 일체형 열전달 슬러그가 형성된 발광다이오드 패키지 및그 제조방법

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Publication number Priority date Publication date Assignee Title
JP2002009349A (ja) 2000-06-26 2002-01-11 Koha Co Ltd Ｌｅｄ面発光装置およびその製造方法
US7824937B2 (en) * 2003-03-10 2010-11-02 Toyoda Gosei Co., Ltd. Solid element device and method for manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62290156A (ja) * 1986-06-09 1987-12-17 Kyocera Corp 半導体素子収納用パツケ−ジの製造法
US5828000A (en) * 1996-11-14 1998-10-27 Fujitsu Limited Semiconductor device with heat radiating plate and positioning dummy lead and lead frame therefor
KR20050084080A (ko) * 2002-12-06 2005-08-26 크리, 인코포레이티드 복합 리드프레임 ｌｅｄ 패키지 및 그 제조 방법
KR20060002282A (ko) * 2004-07-01 2006-01-09 서울반도체 주식회사 일체형 열전달 슬러그가 형성된 발광다이오드 패키지 및그 제조방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104290253A (zh) * 2014-09-04 2015-01-21 瑞安市明光灯饰有限公司 Led灯条管道加工机

Also Published As

Publication number Publication date
TW200913325A (en) 2009-03-16
TWI451594B (zh) 2014-09-01
WO2009005257A3 (fr) 2009-03-05
KR101380385B1 (ko) 2014-04-10
KR20090001036A (ko) 2009-01-08

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