WO2009001450A1 - メモリアクセス制御装置 - Google Patents

メモリアクセス制御装置 Download PDF

Info

Publication number
WO2009001450A1
WO2009001450A1 PCT/JP2007/062918 JP2007062918W WO2009001450A1 WO 2009001450 A1 WO2009001450 A1 WO 2009001450A1 JP 2007062918 W JP2007062918 W JP 2007062918W WO 2009001450 A1 WO2009001450 A1 WO 2009001450A1
Authority
WO
WIPO (PCT)
Prior art keywords
packet
data
clock
reading
memory
Prior art date
Application number
PCT/JP2007/062918
Other languages
English (en)
French (fr)
Inventor
Hidenori Kiuchi
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/062918 priority Critical patent/WO2009001450A1/ja
Priority to JP2009520251A priority patent/JP4941557B2/ja
Publication of WO2009001450A1 publication Critical patent/WO2009001450A1/ja
Priority to US12/632,964 priority patent/US8312208B2/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9042—Separate storage for different parts of the packet, e.g. header and payload

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Information Transfer Systems (AREA)

Abstract

　パケットデータ読み出しのレイテンシ量に依存せずに自由度を向上させる。 　パケットメモリ（１１）は、データ（ｄ１）と、クロック（ｃｋ１）とを並走出力するクロック並走出力機能を持ち、パケットを格納する。読み出し制御部（１３）は、データ（ｄ１）を読み出す。クロック乗り換え部（１４）は、クロック（ｃｋ１）を用いてデータ（ｄ１）を書き込み、システムクロック（ｃｋ２）でデータ（ｄ２）を読み出してクロック乗り換えを行う。パケット組み立て部（１５）は、データ（ｄ２）を受信して、パケットの再構築を行う。情報メモリ（１２）は、パケットの先頭データが格納されている読み出し開始アドレスと、パケットの長さを示すパケット長情報とを格納し、読み出し制御部（１３）は、読み出し開始アドレスとパケット長情報とを受信して、１パケットを読み出すために必要な読み出しアドレスを生成してパケットメモリ（１１）からデータ（ｄ）を読み出す。
PCT/JP2007/062918 2007-06-27 2007-06-27 メモリアクセス制御装置 WO2009001450A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2007/062918 WO2009001450A1 (ja) 2007-06-27 2007-06-27 メモリアクセス制御装置
JP2009520251A JP4941557B2 (ja) 2007-06-27 2007-06-27 メモリアクセス制御装置
US12/632,964 US8312208B2 (en) 2007-06-27 2009-12-08 Memory access controller and method implementing packet processing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/062918 WO2009001450A1 (ja) 2007-06-27 2007-06-27 メモリアクセス制御装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/632,964 Continuation US8312208B2 (en) 2007-06-27 2009-12-08 Memory access controller and method implementing packet processing

Publications (1)

Publication Number Publication Date
WO2009001450A1 true WO2009001450A1 (ja) 2008-12-31

Family

ID=40185284

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/062918 WO2009001450A1 (ja) 2007-06-27 2007-06-27 メモリアクセス制御装置

Country Status (3)

Country Link
US (1) US8312208B2 (ja)
JP (1) JP4941557B2 (ja)
WO (1) WO2009001450A1 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10074409B2 (en) * 2017-01-31 2018-09-11 Intel Corporation Configurable storage blocks having simple first-in first-out enabling circuitry
CN115315921A (zh) * 2021-02-26 2022-11-08 西恩泰克有限公司 支持机器间连接的物联网通信系统

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02287739A (ja) * 1989-04-28 1990-11-27 Moji Zukei Center:Kk メモリアクセス方法
JP2003015943A (ja) * 2002-05-13 2003-01-17 Hitachi Ltd 半導体装置
JP2005117206A (ja) * 2003-10-06 2005-04-28 Hitachi Ltd ネットワークプロセッサアクセラレータ

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997033227A1 (fr) * 1996-03-07 1997-09-12 Nippon Telegraph And Telephone Corporation Procede et appareil de transfert de fichiers sequentiels a grande vitesse, et support d'enregistrement pour le stockage d'un programme en charge dudit transfert
JP3191701B2 (ja) * 1996-10-29 2001-07-23 日本電気株式会社 伝送フレームフォーマット変換回路
JP3190847B2 (ja) 1997-02-12 2001-07-23 甲府日本電気株式会社 データ転送制御装置
JPH11249978A (ja) * 1998-03-04 1999-09-17 Nippon Telegr & Teleph Corp <Ntt> データ転送方法および装置
WO2001058066A1 (fr) * 2000-02-01 2001-08-09 Fujitsu Limited Dispositif de transfert d'information
JP4154213B2 (ja) * 2002-11-01 2008-09-24 富士通株式会社 パケット処理装置
JP4037811B2 (ja) * 2003-09-10 2008-01-23 富士通株式会社 Ｓｏｎｅｔ／ｓｄｈ装置の監視制御通信方式

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02287739A (ja) * 1989-04-28 1990-11-27 Moji Zukei Center:Kk メモリアクセス方法
JP2003015943A (ja) * 2002-05-13 2003-01-17 Hitachi Ltd 半導体装置
JP2005117206A (ja) * 2003-10-06 2005-04-28 Hitachi Ltd ネットワークプロセッサアクセラレータ

Also Published As

Publication number Publication date
JPWO2009001450A1 (ja) 2010-08-26
JP4941557B2 (ja) 2012-05-30
US8312208B2 (en) 2012-11-13
US20100088479A1 (en) 2010-04-08

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