WO2008149407A1 - ジッタ制御装置 - Google Patents

ジッタ制御装置 Download PDF

Info

Publication number
WO2008149407A1
WO2008149407A1 PCT/JP2007/000618 JP2007000618W WO2008149407A1 WO 2008149407 A1 WO2008149407 A1 WO 2008149407A1 JP 2007000618 W JP2007000618 W JP 2007000618W WO 2008149407 A1 WO2008149407 A1 WO 2008149407A1
Authority
WO
WIPO (PCT)
Prior art keywords
order group
low
group signals
reading clock
justification
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/000618
Other languages
English (en)
French (fr)
Inventor
Yuichiro Sakamoto
Hisayuki Ojima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to PCT/JP2007/000618 priority Critical patent/WO2008149407A1/ja
Priority to JP2009517627A priority patent/JP4733766B2/ja
Publication of WO2008149407A1 publication Critical patent/WO2008149407A1/ja
Priority to US12/629,413 priority patent/US8488622B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1652—Optical Transport Network [OTN]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

　複数の低次群信号は、非同期多重部が備えるバッファメモリを利用して多重化される。各低次群信号は、それぞれ対応する書込みクロックを利用してバッファメモリに書き込まれ、共通の読出しクロックを利用して読み出される。制御回路は、読出しクロックを切り替えながら、各低次群信号についてジャスティフィケーションの発生頻度を検出する。制御回路は、ジャスティフィケーションの発生頻度に基づいて、各低次群信号のジッタが閾値よりも小さくなるようなクロック信号を選択して読出しクロックとして非同期多重部に供給する。
PCT/JP2007/000618 2007-06-08 2007-06-08 ジッタ制御装置 Ceased WO2008149407A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2007/000618 WO2008149407A1 (ja) 2007-06-08 2007-06-08 ジッタ制御装置
JP2009517627A JP4733766B2 (ja) 2007-06-08 2007-06-08 ジッタ制御装置
US12/629,413 US8488622B2 (en) 2007-06-08 2009-12-02 Jitter control apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/000618 WO2008149407A1 (ja) 2007-06-08 2007-06-08 ジッタ制御装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/629,413 Continuation US8488622B2 (en) 2007-06-08 2009-12-02 Jitter control apparatus

Publications (1)

Publication Number Publication Date
WO2008149407A1 true WO2008149407A1 (ja) 2008-12-11

Family

ID=40093244

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/000618 Ceased WO2008149407A1 (ja) 2007-06-08 2007-06-08 ジッタ制御装置

Country Status (3)

Country Link
US (1) US8488622B2 (ja)
JP (1) JP4733766B2 (ja)
WO (1) WO2008149407A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010212890A (ja) * 2009-03-09 2010-09-24 Fujitsu Ltd フレーム生成装置およびフレーム生成方法
WO2011151892A1 (ja) * 2010-06-01 2011-12-08 富士通株式会社 通信システム、フレーム同期検出装置およびフレーム同期検出方法
JP2016072857A (ja) * 2014-09-30 2016-05-09 富士通株式会社 光伝送装置および伝送フレーム生成方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5595313B2 (ja) * 2011-03-16 2014-09-24 三菱電機株式会社 光ネットワークシステムおよびｗｄｍ装置
US9474492B2 (en) 2012-05-22 2016-10-25 Siemens Medical Solutions Usa, Inc. Adaptive ECG trigger signal jitter detection and compensation for imaging systems
US9819436B2 (en) 2013-08-26 2017-11-14 Coriant Operations, Inc. Intranodal ROADM fiber management apparatuses, systems, and methods
US9723385B2 (en) * 2013-11-06 2017-08-01 Coriant Operations, LLC Procedures, apparatuses, systems, and computer programs for providing optical network channel protection
CN107124244B (zh) * 2017-05-12 2018-12-18 杭州一隅千象科技有限公司 异步数据复接方法和装置
US12489540B2 (en) * 2022-09-25 2025-12-02 Infinera Corp. Systems and methods for enabling point-to-multi-point applications in common management interface specification

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0338931A (ja) * 1989-07-05 1991-02-20 Matsushita Electric Ind Co Ltd スタッフ同期方式によるデータ伝送装置
JPH05130064A (ja) * 1991-03-25 1993-05-25 Nec Corp デスタツフ回路
JPH0685778A (ja) * 1992-09-04 1994-03-25 Fujitsu Ltd 平滑化回路におけるジッタ抑圧方式
JP2004282632A (ja) * 2003-03-18 2004-10-07 Fujitsu Ltd ジッタ抑制方法及び装置

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US4397017A (en) * 1981-03-02 1983-08-02 Nippon Electric Co., Ltd. Stuff synchronization device with reduced sampling jitter
JPH01180142A (ja) 1988-01-12 1989-07-18 Fujitsu Ltd 同期式位相比較回路
DE4101270A1 (de) * 1991-01-17 1992-07-23 Siemens Ag Verfahren zur uebertragung von digitalsignalen
EP0500243B1 (en) 1991-02-08 1999-03-31 Nec Corporation Distributed bit-by-bit destuffing circuit for byte-stuffed multiframe data
EP0630127B1 (en) * 1993-06-18 1999-01-13 Alcatel Digital phase locked loop arrangement
US7042908B1 (en) * 2000-07-10 2006-05-09 Nortel Networks Limited Method and apparatus for transmitting arbitrary electrical signals over a data network
US8274892B2 (en) * 2001-10-09 2012-09-25 Infinera Corporation Universal digital framer architecture for transport of client signals of any client payload and format type
US7023942B1 (en) * 2001-10-09 2006-04-04 Nortel Networks Limited Method and apparatus for digital data synchronization
JP2003188919A (ja) * 2001-12-19 2003-07-04 Nec Corp ネットワーク、スイッチ装置及びそれに用いるｏｔｎフレーム処理方法並びにその回路及び集積回路
US20070019687A1 (en) * 2002-06-04 2007-01-25 Eci Telecom Ltd. Technique for converting bit rates
US7369578B2 (en) * 2003-07-01 2008-05-06 Nortel Networks Limited Digital processing of SONET pointers
US8699886B2 (en) * 2005-11-23 2014-04-15 Ciena Corporation Externally synchronized optical transport network systems and associated methods
JP4991270B2 (ja) * 2006-12-13 2012-08-01 株式会社日立製作所 送信装置および受信装置
JP5130064B2 (ja) 2008-01-25 2013-01-30 パナソニック株式会社 建築用パネル材の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0338931A (ja) * 1989-07-05 1991-02-20 Matsushita Electric Ind Co Ltd スタッフ同期方式によるデータ伝送装置
JPH05130064A (ja) * 1991-03-25 1993-05-25 Nec Corp デスタツフ回路
JPH0685778A (ja) * 1992-09-04 1994-03-25 Fujitsu Ltd 平滑化回路におけるジッタ抑圧方式
JP2004282632A (ja) * 2003-03-18 2004-10-07 Fujitsu Ltd ジッタ抑制方法及び装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010212890A (ja) * 2009-03-09 2010-09-24 Fujitsu Ltd フレーム生成装置およびフレーム生成方法
WO2011151892A1 (ja) * 2010-06-01 2011-12-08 富士通株式会社 通信システム、フレーム同期検出装置およびフレーム同期検出方法
US9203603B2 (en) 2010-06-01 2015-12-01 Fujitsu Limited Communication system, frame synchronization detection apparatus, and frame synchronization detection method
JP2016072857A (ja) * 2014-09-30 2016-05-09 富士通株式会社 光伝送装置および伝送フレーム生成方法

Also Published As

Publication number Publication date
US20100074386A1 (en) 2010-03-25
US8488622B2 (en) 2013-07-16
JP4733766B2 (ja) 2011-07-27
JPWO2008149407A1 (ja) 2010-08-19

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