WO2008142857A1 - 半導体集積回路 - Google Patents

半導体集積回路 Download PDF

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Publication number
WO2008142857A1
WO2008142857A1 PCT/JP2008/001222 JP2008001222W WO2008142857A1 WO 2008142857 A1 WO2008142857 A1 WO 2008142857A1 JP 2008001222 W JP2008001222 W JP 2008001222W WO 2008142857 A1 WO2008142857 A1 WO 2008142857A1
Authority
WO
WIPO (PCT)
Prior art keywords
comb
integrated circuit
tooth portions
semiconductor integrated
accuracy
Prior art date
Application number
PCT/JP2008/001222
Other languages
English (en)
French (fr)
Inventor
Daisuke Nomasaki
Koji Oka
Toshiaki Ozeki
Original Assignee
Panasonic Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corporation filed Critical Panasonic Corporation
Priority to US12/600,094 priority Critical patent/US20110254125A1/en
Priority to CN2008800121051A priority patent/CN101663746B/zh
Priority to JP2009515089A priority patent/JPWO2008142857A1/ja
Publication of WO2008142857A1 publication Critical patent/WO2008142857A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H03H2001/0014—Capacitor filters, i.e. capacitors whose parasitic inductance is of relevance to consider it as filter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Analogue/Digital Conversion (AREA)
  • Networks Using Active Elements (AREA)

Abstract

　本発明にかかる半導体集積回路は、櫛形容量（１０）を備えるアナログマクロを複数搭載し、櫛形容量（１０）は、櫛形形状の電極（１１）及び電極（１２）を有し、電極（１１）の櫛歯部（１３）と電極（１２）の櫛歯部（１４）とが交互に平行に並ぶように、電極（１１）の櫛歯部（１３）と電極（１２）の櫛歯部（１４）とが噛み合わされて形成され、実際の容量値と理想の容量値との誤差を示す絶対精度、または、近接する櫛形容量間の容量値の差を示す相対精度に応じて、その櫛歯部間隔Ｓが異なることを特徴とする。 　高い容量精度を確保した櫛形容量を備える高精度なアナログマクロ、及び高集積なアナログマクロを搭載する半導体集積回路を提供することができる。
PCT/JP2008/001222 2007-05-16 2008-05-16 半導体集積回路 WO2008142857A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/600,094 US20110254125A1 (en) 2007-05-16 2008-05-16 Semiconductor integrated circuit
CN2008800121051A CN101663746B (zh) 2007-05-16 2008-05-16 半导体集成电路
JP2009515089A JPWO2008142857A1 (ja) 2007-05-16 2008-05-16 半導体集積回路

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-129951 2007-05-16
JP2007129951 2007-05-16

Publications (1)

Publication Number Publication Date
WO2008142857A1 true WO2008142857A1 (ja) 2008-11-27

Family

ID=40031576

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/001222 WO2008142857A1 (ja) 2007-05-16 2008-05-16 半導体集積回路

Country Status (4)

Country Link
US (1) US20110254125A1 (ja)
JP (1) JPWO2008142857A1 (ja)
CN (2) CN101663746B (ja)
WO (1) WO2008142857A1 (ja)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103762040B (zh) * 2014-01-18 2016-01-27 尹晓春 箔片梳状电极的制作方法
US9813659B1 (en) * 2016-05-11 2017-11-07 Drone Racing League, Inc. Diversity receiver
US10737781B2 (en) 2017-09-14 2020-08-11 Drone Racing League, Inc. Three-dimensional pathway tracking system
KR102357832B1 (ko) * 2019-05-08 2022-02-03 삼성에스디아이 주식회사 배터리 팩
CN111175574B (zh) * 2020-01-02 2021-03-05 中国科学院半导体研究所 一种测量系统及测量方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61263251A (ja) * 1985-05-17 1986-11-21 Nec Corp 半導体装置
JP2003297926A (ja) * 2002-03-28 2003-10-17 Fujitsu Quantum Devices Ltd インタディジタルキャパシタ及びその容量調整方法
JP2005072233A (ja) * 2003-08-25 2005-03-17 Renesas Technology Corp 半導体装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003335951A (ja) * 2002-05-20 2003-11-28 Mitsubishi Rayon Co Ltd 熱可塑性樹脂組成物、その製造方法および成形体
JP2006261455A (ja) * 2005-03-17 2006-09-28 Fujitsu Ltd 半導体装置およびｍｉｍキャパシタ
US7675138B2 (en) * 2005-09-30 2010-03-09 Broadcom Corporation On-chip capacitor structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61263251A (ja) * 1985-05-17 1986-11-21 Nec Corp 半導体装置
JP2003297926A (ja) * 2002-03-28 2003-10-17 Fujitsu Quantum Devices Ltd インタディジタルキャパシタ及びその容量調整方法
JP2005072233A (ja) * 2003-08-25 2005-03-17 Renesas Technology Corp 半導体装置

Also Published As

Publication number Publication date
CN101663746A (zh) 2010-03-03
US20110254125A1 (en) 2011-10-20
JPWO2008142857A1 (ja) 2010-08-05
CN101663746B (zh) 2011-09-14
CN102263106A (zh) 2011-11-30

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