WO2008126264A1 - 半導体集積回路装置 - Google Patents

半導体集積回路装置 Download PDF

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Publication number
WO2008126264A1
WO2008126264A1 PCT/JP2007/057152 JP2007057152W WO2008126264A1 WO 2008126264 A1 WO2008126264 A1 WO 2008126264A1 JP 2007057152 W JP2007057152 W JP 2007057152W WO 2008126264 A1 WO2008126264 A1 WO 2008126264A1
Authority
WO
WIPO (PCT)
Prior art keywords
mos transistor
integrated circuit
channel mos
circuit device
stress film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/057152
Other languages
English (en)
French (fr)
Inventor
Satoshi Nakai
Masato Suga
Jusuke Ogura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Priority to CN200780052411.3A priority Critical patent/CN101641778B/zh
Priority to PCT/JP2007/057152 priority patent/WO2008126264A1/ja
Priority to JP2009508812A priority patent/JP5299268B2/ja
Publication of WO2008126264A1 publication Critical patent/WO2008126264A1/ja
Priority to US12/561,719 priority patent/US8884375B2/en
Anticipated expiration legal-status Critical
Priority to US14/033,166 priority patent/US8790974B2/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

　半導体集積回路装置は半導体基板と、前記半導体基板上に形成された複数の半導体素子とよりなり、前記複数の半導体素子は、ｎチャネルＭＯＳトランジスタとｐチャネルＭＯＳトランジスタを含み、前記nチャネルＭＯＳトランジスタは引張り応力膜により覆われ、前記ｐチャネルＭＯＳトランジスタは圧縮応力膜により覆われ、前記半導体基板表面には、その全面が前記引張り応力膜および前記圧縮応力膜のいずれかよりなるダミー領域が形成されている。
PCT/JP2007/057152 2007-03-30 2007-03-30 半導体集積回路装置 Ceased WO2008126264A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN200780052411.3A CN101641778B (zh) 2007-03-30 2007-03-30 半导体集成电路装置
PCT/JP2007/057152 WO2008126264A1 (ja) 2007-03-30 2007-03-30 半導体集積回路装置
JP2009508812A JP5299268B2 (ja) 2007-03-30 2007-03-30 半導体集積回路装置およびその製造方法
US12/561,719 US8884375B2 (en) 2007-03-30 2009-09-17 Semiconductor integrated circuit device
US14/033,166 US8790974B2 (en) 2007-03-30 2013-09-20 Method of manufacturing semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/057152 WO2008126264A1 (ja) 2007-03-30 2007-03-30 半導体集積回路装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/561,719 Continuation US8884375B2 (en) 2007-03-30 2009-09-17 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
WO2008126264A1 true WO2008126264A1 (ja) 2008-10-23

Family

ID=39863444

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/057152 Ceased WO2008126264A1 (ja) 2007-03-30 2007-03-30 半導体集積回路装置

Country Status (4)

Country Link
US (2) US8884375B2 (ja)
JP (1) JP5299268B2 (ja)
CN (1) CN101641778B (ja)
WO (1) WO2008126264A1 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104734695B (zh) * 2013-12-24 2018-05-04 澜起科技（上海）有限公司 信号发生器、电子系统以及产生信号的方法
KR102294323B1 (ko) * 2014-07-09 2021-08-26 삼성전자주식회사 스트레스 검출 방법, 컴팩트 모델 트레이닝 방법, 스트레스 완화 방법 및 컴퓨팅 시스템

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007005626A (ja) * 2005-06-24 2007-01-11 Sony Corp 半導体装置及びその製造方法

Family Cites Families (18)

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Publication number Priority date Publication date Assignee Title
JPH02206160A (ja) * 1989-02-06 1990-08-15 Matsushita Electron Corp 半導体装置の製造方法
JP4845299B2 (ja) * 2001-03-09 2011-12-28 富士通セミコンダクター株式会社 半導体装置の製造方法
JP4173672B2 (ja) * 2002-03-19 2008-10-29 株式会社ルネサステクノロジ 半導体装置及びその製造方法
US8008724B2 (en) * 2003-10-30 2011-08-30 International Business Machines Corporation Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers
US7176522B2 (en) * 2003-11-25 2007-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having high drive current and method of manufacturing thereof
US20050214998A1 (en) * 2004-03-26 2005-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. Local stress control for CMOS performance enhancement
JP4102334B2 (ja) * 2004-06-16 2008-06-18 株式会社東芝 半導体装置及びその製造方法
JP5002891B2 (ja) * 2004-12-17 2012-08-15 富士通セミコンダクター株式会社 半導体装置の製造方法
US7470943B2 (en) * 2005-08-22 2008-12-30 International Business Machines Corporation High performance MOSFET comprising a stressed gate metal silicide layer and method of fabricating the same
US7709317B2 (en) * 2005-11-14 2010-05-04 International Business Machines Corporation Method to increase strain enhancement with spacerless FET and dual liner process
KR100724574B1 (ko) * 2006-01-10 2007-06-04 삼성전자주식회사 식각저지막을 갖는 반도체 소자 및 그의 제조방법
US7416931B2 (en) * 2006-08-22 2008-08-26 Advanced Micro Devices, Inc. Methods for fabricating a stress enhanced MOS circuit
US7675118B2 (en) * 2006-08-31 2010-03-09 International Business Machines Corporation Semiconductor structure with enhanced performance using a simplified dual stress liner configuration
US7521763B2 (en) * 2007-01-03 2009-04-21 International Business Machines Corporation Dual stress STI
US7632724B2 (en) * 2007-02-12 2009-12-15 International Business Machines Corporation Stressed SOI FET having tensile and compressive device regions
JP4586843B2 (ja) * 2007-11-15 2010-11-24 ソニー株式会社 半導体装置
CN101855703B (zh) * 2007-12-27 2013-03-13 夏普株式会社 半导体装置的制造方法
US7932563B2 (en) * 2009-01-30 2011-04-26 Xilinx, Inc. Techniques for improving transistor-to-transistor stress uniformity

Patent Citations (1)

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Publication number Priority date Publication date Assignee Title
JP2007005626A (ja) * 2005-06-24 2007-01-11 Sony Corp 半導体装置及びその製造方法

Also Published As

Publication number Publication date
CN101641778A (zh) 2010-02-03
JP5299268B2 (ja) 2013-09-25
US8884375B2 (en) 2014-11-11
US8790974B2 (en) 2014-07-29
CN101641778B (zh) 2014-12-17
US20100001350A1 (en) 2010-01-07
JPWO2008126264A1 (ja) 2010-07-22
US20140024224A1 (en) 2014-01-23

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