WO2008126255A1 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
WO2008126255A1
WO2008126255A1 PCT/JP2007/057114 JP2007057114W WO2008126255A1 WO 2008126255 A1 WO2008126255 A1 WO 2008126255A1 JP 2007057114 W JP2007057114 W JP 2007057114W WO 2008126255 A1 WO2008126255 A1 WO 2008126255A1
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Prior art keywords
insulating film
gate insulating
silicon substrate
oxygen
semiconductor device
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Ceased
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PCT/JP2007/057114
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English (en)
French (fr)
Inventor
Sekikin Sho
Kazuto Ikeda
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Fujitsu Semiconductor Ltd
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Fujitsu Semiconductor Ltd
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Priority to JP2009508805A priority Critical patent/JPWO2008126255A1/ja
Priority to PCT/JP2007/057114 priority patent/WO2008126255A1/ja
Publication of WO2008126255A1 publication Critical patent/WO2008126255A1/ja
Priority to US12/568,751 priority patent/US20100022080A1/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
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    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H10P14/6927—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
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    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/0134—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor
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    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/01344—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid in a nitrogen-containing ambient, e.g. N2O oxidation
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    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
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    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
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    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
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    • H10P14/6519—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer the substance being oxygen
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    • H10P14/6524—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer the substance being nitrogen
    • H10P14/6526—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer the substance being nitrogen introduced into an oxide material, e.g. changing SiO to SiON
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    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
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Landscapes

  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

　シリコン基板１０を加熱しながらアンモニアで窒化する工程と、次いで、シリコン基板１０を窒素と酸素を含む雰囲気中で加熱して、窒素と酸素を含むシリコン系絶縁膜を有するゲート絶縁膜２２を形成する工程と、次いで、シリコン基板１０を酸素雰囲気中でアニールする工程と、ゲート絶縁膜２２上に、ゲート電極２４を形成する工程とを有する。これにより、ゲート絶縁膜２２とシリコン基板２４の界面或いはゲート絶縁膜２２中の欠陥を低減し、ゲート絶縁膜２２の実効的な膜厚を増加することなく、膜質や界面特性を向上することができる。
PCT/JP2007/057114 2007-03-30 2007-03-30 半導体装置の製造方法 Ceased WO2008126255A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009508805A JPWO2008126255A1 (ja) 2007-03-30 2007-03-30 半導体装置の製造方法
PCT/JP2007/057114 WO2008126255A1 (ja) 2007-03-30 2007-03-30 半導体装置の製造方法
US12/568,751 US20100022080A1 (en) 2007-03-30 2009-09-29 Method of manufacturing semiconductor device

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Application Number Priority Date Filing Date Title
PCT/JP2007/057114 WO2008126255A1 (ja) 2007-03-30 2007-03-30 半導体装置の製造方法

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WO2008126255A1 true WO2008126255A1 (ja) 2008-10-23

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2025530064A (ja) * 2023-08-23 2025-09-11 ウォニク アイピーエス カンパニー リミテッド 薄膜のエッチング方法

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Publication number Priority date Publication date Assignee Title
US9578626B2 (en) 2013-03-15 2017-02-21 Qualcomm Incorporated Systems and methods for sharing context information in a neighbor aware network

Citations (4)

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Publication number Priority date Publication date Assignee Title
JPH01248561A (ja) * 1988-03-29 1989-10-04 Seiko Instr Inc 半導体装置の製造方法
JPH05251439A (ja) * 1991-10-22 1993-09-28 Oki Electric Ind Co Ltd 半導体装置の絶縁膜形成方法
JPH07335641A (ja) * 1994-06-03 1995-12-22 Sony Corp シリコン酸化膜の形成方法及び半導体装置の酸化膜
JP2004247528A (ja) * 2003-02-14 2004-09-02 Sony Corp 半導体装置の製造方法

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Publication number Priority date Publication date Assignee Title
JP2004022902A (ja) * 2002-06-18 2004-01-22 Fujitsu Ltd 半導体装置の製造方法
US7514376B2 (en) * 2003-04-30 2009-04-07 Fujitsu Microelectronics Limited Manufacture of semiconductor device having nitridized insulating film
JP2009076605A (ja) * 2007-09-19 2009-04-09 Fujitsu Microelectronics Ltd 半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01248561A (ja) * 1988-03-29 1989-10-04 Seiko Instr Inc 半導体装置の製造方法
JPH05251439A (ja) * 1991-10-22 1993-09-28 Oki Electric Ind Co Ltd 半導体装置の絶縁膜形成方法
JPH07335641A (ja) * 1994-06-03 1995-12-22 Sony Corp シリコン酸化膜の形成方法及び半導体装置の酸化膜
JP2004247528A (ja) * 2003-02-14 2004-09-02 Sony Corp 半導体装置の製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SONG S.C. ET AL.: "Ultra Thin high quality stack nitride/oxide gate dielectrics prepared by in-situ rapid thermal N2O oxidation of NH3-nitrided Si", SYMPOSIUM ON VLSI TECHNOLOGY DIGEST OF TECHNICAL PAPERS, 1999, pages 137 - 138, XP000894547 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2025530064A (ja) * 2023-08-23 2025-09-11 ウォニク アイピーエス カンパニー リミテッド 薄膜のエッチング方法

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