WO2008123542A1

WO2008123542A1 - Pll circuit device and control device

Info

Publication number: WO2008123542A1
Application number: PCT/JP2008/056538
Authority: WO
Inventors: Hitoshi Kondoh; Fuminori Kobayashi; Manabu Inoue
Original assignee: System Lsi Co. Ltd.; Kyushu Institute Of Technology
Priority date: 2007-03-29
Filing date: 2008-03-26
Publication date: 2008-10-16
Also published as: JP4681667B2; JPWO2008123542A1

Abstract

Provided are a PLL circuit and a control device in which a jitter is reduced. The PLL circuit (10A) outputs an oscillation clock (32) obtained by multiplying a reference clock (24) and corrects the oscillation clock (32) by using a first correction signal (28) based on a phase difference between the reference clock (24) and an oscillation clock (32). Furthermore, the PLL circuit (10A) includes: a signal generation unit (12) which generates a first waveform signal (36) synchronized with the reference clock (24); a sampling unit (14) which samples a first waveform signal (36) by using a higher frequency than the reference signal (24) so as to obtain a first sample value (26); a comparison unit (16) which compares the first sample value (26) to a second sample value (34) obtained by sampling a second waveform signal (38) based on a waveform when the PLL circuit (10A) is in a stable state and outputs a first correction signal based on a difference between them; and an output unit (20) which outputs the oscillation clock (32) adjusted according to the second correction signal (correction signal).

Description

PC Leakage 55538 _Description

P L L circuit oppi control device

Technical field

The present invention relates to a PLL circuit that corrects an oscillation clock based on a difference between a reference clock and an oscillation clock. Furthermore, the present invention relates to a control device that corrects an output signal based on a difference between the input signal and the output signal. Background art

The conventional PLL circuit (phase 'locked' loop circuit) will be described with reference to Fig. 16.

The PLL circuit 1 0 0 shown in this figure includes a phase comparison circuit 1 0 1, a low-pass filter circuit 1 0 2, a VC Ο circuit (voltage controlled oscillation circuit) 1 0 3, and a frequency divider circuit 1 0 4. ing. Then, the oscillation frequency of the VCO circuit 103 is controlled based on the external reference clock signal to generate a clock signal having a predetermined frequency synchronized with the external reference clock signal, and outputs this to the outside. Further, when the external reference clock signal and the feedback signal are supplied, the phase comparison circuit 101 generates a signal corresponding to the phase difference between the external reference clock signal and the feedback signal, and outputs this signal. Supply to one-pass filter circuit 1 0 2. The low-pass filter circuit 10 2 smoothes the signal output from the phase comparison circuit 1 0 1 to generate a frequency control signal, and supplies this to the V C 0 1 circuit 3.

The VCO circuit 10 3 oscillates at a frequency according to the frequency control signal output from the mouth-pass filter circuit 10 2, generates a clock signal, outputs the clock signal to the outside, and the frequency dividing circuit 1 0 Supply to 4. The frequency divider circuit 104 divides the clock signal output from the VCO circuit 103 by a preset frequency division ratio to generate a feedback signal, and supplies this to the phase comparator circuit 101.

In this way, in a general PLL circuit, the phase of the feedback signal obtained by dividing the clock signal output from the VCO circuit 103 is compared with the phase of the external reference clock signal. Yes. Then, the oscillation frequency of the VCO circuit 103 is controlled so that the phases of the two coincide with each other, and the queuing signal having the frequency and the phase determined by this control operation is output to the outside.

For example, a conventional PLL circuit is described in Japanese Patent Laid-Open No. 0 1-2 3 2 8 2 8. T JP2008 / 056538.

In the PLL circuit configured as described above, the frequency of the clock signal is corrected using the phase difference between the external reference clock signal and the feedback signal. That is, the output signal is corrected using the difference between the input signal and the output signal. Such correction is also performed by other devices. For example, the same method is basically applied to a motor rotation speed control device and a temperature control device. Disclosure of the invention

In the general PLL with the above configuration, the multiplication factor is determined by two combinations (N / M) of the reference clock divider (1 / M) and the feed pack clock divider (1 / N). It was. Therefore, when a multiplication factor that increases the value of N or M is selected as a numerical value that can be realized by the combination of these two integers (NZM), the phase comparison unit is reached when the reference clock is constant. There was a problem that the frequency of the signal was lowered.

In the sample value system such as P L L, the sample frequency is decisive for the upper limit of the frequency of the signal that can be handled. Therefore, the cutoff frequency of the P L L loop filter (hereinafter referred to as L PF) is inevitably lowered. When the L PF cut-off decreases, the entire circuit becomes insensitive to loop noise caused by V C O (oscillator) and the like, which causes an increase in jitter. Furthermore, because the divider was asynchronous, there was a problem that the temperature characteristics of the phase delay were poor and clock rise interference occurred.

Further, the above-described problem may occur in other control devices such as a device for controlling the rotation of a motor or a temperature control device.

The present invention has been made in view of the above-described problems. A main object of the present invention is to provide a PLL circuit and a control device with reduced jitter.

The present invention provides a PLL circuit that outputs an oscillation clock multiplied by a reference clock and corrects the oscillation clock using a correction signal based on a phase difference between the reference clock and the oscillation clock. A signal generating unit that generates a first waveform signal having synchronism with the reference clock; a sample unit that samples the first waveform signal at a frequency higher than the reference clock to obtain a first sample value; and the PLL A comparison unit that compares the first sample value with a second sample value obtained by sampling a second waveform signal based on a waveform when the circuit is in a stable state, and outputs the correction signal based on a difference between the two sample values; Based on And an output unit for outputting the corrected oscillation clock. The present invention relates to a control device that corrects the characteristics of the output signal using a correction signal that indicates a difference between the input signal and the output signal, and that generates a first waveform signal that is synchronized with the input signal. A generating unit; a sample unit that samples the first waveform signal at a frequency higher than a cycle of the input signal to obtain a first sample value; and a second waveform based on a waveform when the control device is in a stable state. A comparison unit that compares the second sample value obtained by sampling the signal with the first sample value and outputs the correction signal based on the difference between the second sample value and the output signal that is corrected based on the correction signal; And an output unit for outputting. According to the present invention, first, a first waveform signal having periodicity with an input signal is generated, and an output signal is corrected using a sample value obtained by sampling the first waveform signal with high frequency. Therefore, since the output signal is corrected more frequently than before, the jitter can be reduced and the characteristics of the output signal (for example, frequency) can be set to a predetermined value.

Furthermore, since the PLL circuit according to the present invention does not require a clock frequency divider, the cutoff frequency of LPF does not decrease. As a result, a PLL with further reduced jitter is provided.

Secondly, since the oscillation frequency of the oscillator is controlled by the digital circuit regardless of the clock period, it is possible to generate a plurality of oscillation clocks having different frequencies from one reference clock. Therefore, by using a common crystal that oscillates the reference clock, the number of crystals can be reduced and the cost required to construct the PLL circuit can be reduced.

Third, since there are few restrictions on the sensitivity function and the complementary sensitivity function, it is easy to design a device that incorporates PLL, such as an audio device.

Fourth, since the V C O control circuit is controlled by a digital circuit, the operating state can be changed by adjusting the gain according to the situation.

Fifth, since the divider required in the conventional PLL circuit is not required, the asynchronous circuit is eliminated and the temperature characteristics of transport delay are good. Furthermore, for the same reason, clock rise interference is reduced. Brief Description of Drawings

FIG. 1 is a block diagram showing the configuration of a PLL circuit which is an example of the control device of the present invention, FIG. 2 is a diagram for explaining the PLL circuit of the present invention, and (A) is a block diagram , (B) and (C) FIG. 3 is a diagram for explaining the PLL circuit of the present invention, (A) is a block diagram, (B) is a waveform diagram, and FIG. 4 is a diagram of the present invention. FIG. 5 is a diagram for explaining a PLL circuit, (A) is a block diagram, (B) is a waveform diagram, and FIG. 5 is a diagram for explaining a PLL circuit of the present invention. (A) is a block diagram, (B) is a waveform diagram, FIG. 6 is a waveform diagram for explaining the PLL circuit of the present invention, and FIG. 7 is a diagram illustrating the PLL circuit of the present invention. (A) is a block diagram, (B) is a block diagram, FIG. 8 is a diagram for explaining the PLL circuit of the present invention, and (A) is a block diagram. (B) is a graph, FIG. 9 is a diagram for explaining the PLL circuit of the present invention, (A) is a diagram partially showing the PLL circuit, and (B) and ( C) is a waveform diagram. FIG. 10 is a block diagram for explaining another PLL circuit of the present invention, FIG. 11 is a block diagram for explaining another PLL circuit of the present invention, and FIG. 12 is a block diagram of the present invention. It is a figure for demonstrating a PLL circuit, (A)-(C) It is a figure which shows the signal production | generation part contained in a PLL circuit, (D) is a waveform diagram, FIG. 13 is (A) Is a graph showing the results of an experiment performed using a conventional PLL circuit, and (B) to (D) are graphs showing the results of an experiment performed using the PLL circuit of the present invention. In the figure, (A) is a graph showing the results of an experiment conducted using a conventional PLL circuit, and (B) is a graph showing the results of an experiment conducted using the PLL circuit of the present invention. FIG. 16 is a graph showing the results obtained by using the conventional PLL circuit of the present invention, and FIG. 16 is a block diagram for explaining the PLL circuit of the background art. BEST MODE FOR CARRYING OUT THE INVENTION

A PLL circuit according to an embodiment of the present invention will be described below with reference to the drawings. Here, in the following embodiment, a PLL circuit is illustrated as an embodiment of the control device, but the present invention can also be applied to other control devices. Specifically, the PLL circuit of this embodiment can be applied to an AV amplifier, a TV receiver, a DVD player, a high-precision measuring device, a temperature management device, a motor rotation control device, a turbine control device, and the like. By applying the PLL circuit of this embodiment to these devices, these devices can be operated stably at high speed. .

Referring to FIG. 1, the PLL circuit 10 A of the present embodiment outputs an oscillation clock 32 that is multiplied by the reference clock 24, and the first circuit based on the phase difference between the reference clock 24 and the oscillation clock 32. This is a PLL circuit that corrects the oscillation clock 32 using the correction signal 28 (correction signal). In addition, PLL circuit 10

A includes a signal generator 12 that generates a first waveform signal 36 that is synchronized with the reference clock 24, and a reference clock. Sample part 1 4 that samples the first waveform signal 3 6 to obtain the first sample value 2 6 more frequently than the lock 2 4 and the second waveform based on the waveform when the PLL circuit 10 A is in a stable state The second sampling value 3 4 sampled from the signal 3 8 is compared with the first sampling value 2 6 and the first correction signal (correction signal) based on the difference between them is output. And an output circuit 20 that outputs an oscillation clock 32 adjusted based on a correction signal (correction signal).

Further, the general function of the PLL circuit 1 OA of the present embodiment will be described. The PLL circuit 10 A is configured such that fr is a predetermined multiple (based on the frequency (fr) of the reference clock 24 input from the outside. The oscillation clock 3 2 of the frequency (ί ο) that is multiplied is output to the outside. In addition? When the circuit 10 is turned on, the frequency of the oscillation clock 3 2 output from the output unit 20 is corrected to a predetermined value using the phase difference between the reference clock 2 4 and the oscillation clock 3 2 (that is, Jitter contained in oscillation clock 3 2 is reduced).

The characteristic parts of the P L L circuit 10 0 に are in the signal generation unit 12, the sample unit 14, the storage unit 2 2, and the comparison unit 16. The first waveform signal 36 is generated by the signal generation unit 12, and the first sample value 26 is generated by sampling the first waveform signal 36 by the sampling unit 14. On the other hand, the storage unit 2 2 stores the second waveform signal 38 when the PLL circuit 1 O A is in a stable state. Then, the second sample value 34 obtained by sampling the second waveform signal 38 is transmitted to the comparison unit 16. In the comparison unit 16, the first sample value 26 and the second sample value 34 are compared, and a first correction signal 28 indicating the phase difference between the two is transmitted to the control unit 18.

When comparing a general P L L circuit and the P L L circuit 1 O A of this embodiment,? The point that O circuit 1 0 can eliminate the frequency divider is very different. That is, in the conventional example, since the oscillation clock to be fed-packed is divided by the frequency divider, the frequency of correcting the oscillation clock frequency is reduced accordingly, and the jitter value is increased. In the present embodiment, by eliminating the frequency divider, the frequency of correcting the oscillation clock is increased and the jitter is reduced. Therefore, the error between the actually measured value and the design value of the frequency of the oscillation clock 32 can be extremely reduced.

Next, with reference to FIGS. 2 and subsequent figures, the configuration and function of each part constituting the PLL circuit 10 A will be described in detail. Fig. 2 (A) is a block diagram showing the PLL circuit 1 OA, Fig. 2 (B) is a waveform diagram showing the first waveform signal 36, etc., and Fig. 2 (C) is another diagram. FIG. 6 is a waveform diagram showing one waveform signal 3 6 A. Referring to FIG. 2 (A), the reference clock 24 is input to the signal generator 12 and the input reference is input. A first waveform signal 36 having synchronism with the reference clock 24 is output from the signal generator 12. The input reference clock 24 is digital data having a square waveform. Furthermore, the frequency of the reference clock 24 is 5 MHz to 50 MHz when the PLL circuit 1 OA is used for an audio circuit, and 27 MHz to 10 when it is used for a video signal. 8 MH z, 3 GH z to l O GH z when used in a DVD player or S-ATA.

In FIG. 2 (B), the reference clock 24 input to the PLL circuit 1 OA, the oscillation clock 3 2 output from the PLL circuit 10 A, and the first waveform signal generated by the signal generation unit 12 3 6 Waveform diagrams are shown. In these waveform diagrams, the horizontal axis is the time axis, and the vertical axis indicates the voltage value or current value (level).

Here, as an example, the frequency of the oscillation clock is four times that of the reference clock 24, and K = 4. Therefore, there are eight rising edges of the oscillation clock 32 signal within the period in which two rising edges of the reference clock signal 24 exist. Here, in an actual model, the value of the multiplication factor is about 2 5 6 or 5 1 2 for example.

The first waveform signal 36 generated based on the reference clock 24 is an analog signal (continuous signal) having a waveform that increases and decreases at least once in one cycle of the reference clock 24. is there. Here, an analog signal having one waveform shape in one cycle of the reference clock 24 is used as the first waveform signal 36. Here, the first waveform signal 36 does not necessarily have a smooth shape, and may have a slightly irregular shape such as a curve shown in the figure. The first waveform signal 36 is a waveform that exhibits a repetitive shape at the same timing as the reference clock 24.

Here, having synchronism means that the cycle in which the value (voltage value or current value) of the reference clock 24 changes is equal to the cycle in which the first waveform signal 36 changes. That is, while the reference clock is turned on and off once, the first waveform signal 36 draws a carp for one cycle.

Referring to FIG. 2 (C), the first waveform signal 36 A can have various waveforms as long as it increases and decreases in synchronization with the reference clock 24. As the waveform shape of the first waveform signal 36 A, a saw shape, a sine wave, a cosine wave, a triangular wave, etc. as shown in this figure, or a combination thereof is adopted. Here, if the first waveform signal 3 6 A is a sawtooth shape, sine wave, cosine wave or triangular wave, the storage unit 2 2 shown in FIG. 2 (A) can be made unnecessary. These waveforms are calculated by the calculation unit. Here, as the waveform of the first waveform signal 36, a curved shape is preferable to a linear shape. The reason is that it is not easy to realize a waveform having a vertical shape as shown in Fig. 2 (C) with an electric circuit. Curved waveform signals can be generated more easily with fewer errors than linear ones.

The first waveform signal 36 generated by the signal generator 12 is transmitted to the sampler 14 for sampling.

The sample section 14 will be described with reference to FIG. FIG. 3 (A) is a block diagram showing the PLL circuit 10 A, and FIG. 3 (B) is a waveform diagram showing sampling.

Referring to FIG. 3 (A), the first waveform signal 36 generated by the signal generation unit 12 is input to the sample unit 14 and also output from the output unit 20 to the outside of the circuit. The oscillation clock 3 2 is fed back. In the sampler section 14, the first waveform signal 36 is sampled by the oscillation clock 32 having a higher frequency (shorter cycle) than that of the reference clock 24. In other words, at all times when the oscillation clock 32 rises, the first waveform signal 36 is sampled to obtain sample values. Here, as will be described later, the number of samplings can be reduced by dividing the oscillation clock 32 to be fed back by the frequency divider.

Referring to FIG. 3 (B), here, sampling is performed eight times at the timing when the oscillation clock 3 2 rises within one cycle of the reference clock 24. Therefore, by this sampling, eight first sample values 26 are obtained.

The plurality of first sample values 26 generated by the sample unit 1 are transmitted to the comparison unit 16.

The storage unit 22 will be described with reference to FIG. FIG. 4A is a block diagram of the PLL circuit 1 O A, and FIG. 4B is a waveform diagram showing details of the second sample value 34.

Referring to FIG. 4 (A), the first sample value 26 when the PLL circuit 1OA is in a stable state is input from the sample unit 14 to the storage unit 22. This first sample value 2 6 force is stored in the storage unit 22 as the second sample value 3 4 to be compared. Also, the second sample value 3 4 generated by sampling the (calculated) second waveform signal 3 8 generated at another part may be stored in the storage unit 2 2. Furthermore, the storage unit 22 may function as a waveform generation unit that generates a second waveform signal that is an ideal waveform by calculation. The second sample value 3 4 is transmitted to the comparison unit 16.

Here, the stable state is a state where the PLL circuit 1 OA is locked, and further, there is no jitter. (Almost) No state. Here, the storage unit 22 is a semiconductor memory or a disk-type storage medium. The storage unit 22 stores the second waveform signal 38 or the second sample value 34 obtained by sampling the second waveform signal 38.

Referring to FIG. 4 (B), the second sample value 34 can be obtained by sampling the second waveform signal 38 having an ideal waveform shape at the timing when the oscillation clock 32 rises. . Here, the timing at which the second waveform signal 38 is sampled is the same as the timing at which the first waveform signal 36 is sampled at the sample unit 14. Further, the number of the first sample value 26 sampled in the sample unit 14 is the same as the number of the second sample value 34 stored in the storage unit 22.

Here, the second sample value 34 is not necessarily generated together with the first sample value 26 using the oscillation clock 32. That is, the second sample value 34 based on the second waveform signal 38 prepared in advance may be stored in the storage unit 22. The second waveform signal 38 can be calculated by a theoretical value, a numerical value, or a mathematical formula by calculation or computer calculation. Furthermore, the sample waveform obtained from the stable PLL circuit 1 O A can also be used. Furthermore, a waveform obtained by performing smoothing or the like on the waveform obtained by these methods can be used.

A comparison unit 16 that compares the first sample value 26 and the second sample value 34 will be described with reference to FIGS. Fig. 5 (A) is a block diagram showing PLL circuit 1 OA, Fig. 5 (B) is a waveform diagram showing the waveform of each signal, and Fig. 6 is a waveform diagram showing details of comparison. .

Referring to FIG. 5 (A), the comparison unit 16 compares the levels (voltage value or current value) of the first sample value 26 and the second sample value 3 4 according to the difference between the levels. The first correction signal 28 is output from the comparison unit 16.

Referring to FIG. 5 (B), in comparison section 16, reference clock 24, oscillation clock 3 2, first waveform signal 36 and second waveform signal 38 are shown. Here, the case where the phase of the first waveform signal 36 is advanced as compared with the second waveform signal 38 which is an ideal waveform in a stable state will be described.

In the comparison unit 16, at each timing when the oscillation clock 3 2 rises, the first sample value 2 6 A included in the first waveform signal 3 6 and the second sample value 3 included in the second waveform signal 3 8 The level is compared with 4. In this example, the first sample value 2 6 A and the second sample value 3 4 are compared at the timing when the fifth oscillation clock 3 2 rises from the left side of the page (the timing indicated by the alternate long and short dash line). explain. FIG. 6 is a waveform diagram for explaining the comparison between the first sample value 26 A sampled from the first waveform signal and the second sample value 34 A sampled from the second waveform signal 38. . In this figure, the first waveform signal 3 6 and the second waveform signal 3 8 are superimposed on one waveform diagram, and the first waveform signal 3 6 is indicated by a solid line, and the second waveform signal 3 8 is indicated by a dotted line. The timing at which both signals are sampled is indicated by a one-dot chain line vertically on the paper.

With reference to this figure, the comparison unit 16 first subtracts the first sample value 2 6 A and the second sample value 3 4 A to obtain the difference between them (level difference 4 4). Next, the phase difference 46 (time difference) is calculated from the level difference 44 based on the rate of change of the first waveform signal 36 at the time when both sample values were sampled. Further, here, the relationship between the level difference 4 4 and the phase difference 4 6 during the increase period of the first waveform signal 36 is different from the relationship between the two during the decrease period of the first waveform signal 36. In other words, the sign of the coefficient of the conversion formula between the two during the increase period and that of the conversion formula during the decrease period are opposite.

The comparison unit 16 outputs a first correction signal 28 based on the converted phase difference to the control unit 18.

The control unit 18 will be described with reference to FIG. FIG. 7 (A) is a block diagram showing the PLL circuit 1 O A and FIG. 7 (B) is a block diagram showing the inside of the control unit 18.

Referring to FIG. 7 (A), first correction signal 28 indicating a phase difference is input to control unit 18. Further, the second correction signal 30 obtained by converting the first correction signal 28 is transmitted from the control unit 18 to the output unit 20.

Referring to FIG. 7 (B), the control unit 18 includes a linear compensation unit 48, a filter 50, and an integration unit 52. The linear compensation unit 48 is a part for linearizing the nonlinear shape when the input first correction signal 28 has a nonlinear property. The filter 50 employs a normal ^second- order low-pass filter, third-order low-pass filter, and lag-lead filter, and removes a signal in a predetermined frequency band. Further, the signal passing through the filter is integrated by the integrating unit 52 and transmitted to the output unit 20 as the second correction signal 30.

Referring to FIG. 8 (A) and FIG. 8 (B), the output unit 20 (variable frequency oscillator) has a frequency corresponding to the magnitude of the input control amount (the voltage of the second correction signal). Outputs oscillation clock 3 2 to the outside. There is a positive linear correlation between the voltage value applied to the output section and the frequency of the oscillation clock 32. Referring to FIG. 8 (A), if the phase of the first sample value 26 is ahead of the phase of the second sample value 34, the second correction applied from the control unit 18 to the output unit The voltage value of the signal 30 is lowered, and the frequency of the oscillation clock 32 is lowered. On the other hand, if the relationship between the two is opposite, the voltage value of the second correction signal 30 is Increased, the frequency of the oscillation clock 32 is increased.

This completes the description of the P L L circuit 1 O A.

With reference to FIG. 9, the items for realizing the overall magnification using the first waveform signal 36 will be described in detail. FIG. 9 (A) is a block diagram partially showing the PLL circuit of the present invention, and FIG. 9 (B) is a waveform diagram of the first waveform signal when the power factor is 4, FIG. C) is a waveform diagram of the first waveform signal when the power factor is 4 Z 3.

Referring to FIG. 9 (A), in the present invention, the first sample value 2 6 generated by the sample unit 14 is compared with the second sample value 34 read from the memory 2 2 B. By outputting the phase difference between the two, a predetermined common magnification is achieved.

The first sample value 26 is obtained by sampling the first waveform signal 36 generated by the signal generator 12 in synchronization with the reference clock 24 at the sampling clock timing at the sampler 14.

On the other hand, the second sample value 34 is a value obtained by sampling an ideal waveform signal containing no jitter at a predetermined timing, and is stored in the memory 22 B in advance. Then, the address signal output from the address incrementer 2 2 A for incrementing the address signal is input to the memory 2 2 B, and the second sample value 34 stored in the memory indicated by the address signal is output.

The comparison unit 16 compares the input first sample value 26 and the second sample value 34, and outputs a phase difference signal indicating the difference therebetween. Based on the output indicating the phase difference, the frequency of the signal generated by V C O is increased or decreased.

FIG. 9 (B) shows the first waveform signal 36 when the total magnification M is 4. FIG. In this case, the first waveform signal 36 is sampled at the timing of the output oscillation clock, and the first sample value 26 is obtained. On the other hand, the memory 22 B stores a second sample value 34 obtained by sampling the ideally shaped first waveform signal at a timing obtained by dividing the reference clock 24 by four. Then, each first sample value 26 and the corresponding second sample value 34 are compared by the comparison unit 16, and the frequency of V CO is controlled based on the phase difference between them. As a result, an oscillation clock with a frequency four times that of the reference clock 24 can be obtained.

Next, referring to FIG. 9 (C), sampling in the case where the total magnification is 43 will be described. In this case, the first waveform signal 36 is sampled at the timing of the output oscillation clock, and the first sample value 26 is obtained. Also, the first waveform signal 3 6 for 3 cycles is stored in memory 2 2 B. The second sample value 3 4 sampled at the divided timing is stored. Then, compare each first sample value 26 with the corresponding second sample value 34, and adjust the output of the VCO based on the phase difference between them to obtain a frequency 4 times 3 times that of the reference clock. The provided oscillation clock can be obtained.

With the above-described configuration, an oscillation clock having a predetermined common magnification is generated without using the previously used minute period.

With reference to FIG. 10, the configuration of another form of PLL circuit 10 B will be described. The basic configuration of the PLL circuit 10 B shown in this figure is the same as that of the PLL circuit 10 A described above, and the difference is that the PLL circuit 10 B includes a frequency divider 54.

Specifically, a frequency division unit 54 is provided in the middle of the path of the oscillation clock 32 fed from the output unit to the sample unit 14. Further, a frequency division unit 56 is provided in the previous stage of the signal generation unit 12, and the reference clock 24 is divided by the frequency division unit 56 and then input to the signal generation unit 12.

By providing both frequency dividers as described above, the ratio (multiplier) between the reference clock 24 and the oscillation clock 32 can be set to a predetermined value. For example, for convenience, the frequency of the reference clock is f r and the frequency of the oscillation clock is f o. Furthermore, suppose that the frequency is set to 1 ZN in frequency divider 54 and the frequency is set to 1 / M in frequency divider 56. Between these variables,

The relation of f o = M ■ f r / N holds.

Here, the natural numbers M and N are generally called division ratios.

That is, by using two frequency dividers, the ratio of f r and f o can be set to a predetermined value. As a result, an oscillation clock 32 having a predetermined frequency is output from the PLL circuit 10 B force. Further, the frequency dividing unit 56 that divides the reference clock 24 may be omitted from the configuration shown in FIG. 10, and only the frequency dividing unit 54 may be provided as a frequency dividing function. By doing so, the oscillation clock 3 2 force S whose frequency is reduced by the frequency divider 5 4 is feed-packed to the sample unit 1 4. Therefore, compared to the PLL circuit 1 OA, which has directly input the oscillation clock 3 2 to the sample section 14, the amount of calculation required for sampling in the sampler section 14 is reduced and the circuit scale is reduced. Can be. Furthermore, the number of second sample values 34 to be stored in the storage unit 22 and the amount of calculation in the comparison unit 16 are also reduced.

The configuration of another form of PLL circuit 10 C will be described with reference to FIG. The configuration of the PLL circuit 10 C shown in this figure is basically the same as that of the PLL circuit 1 OA described above. In PLL circuit 10 C, follow The next model? 1 ^ The circuit 7 8 was supplemented with a compensator 6 6 that generates the first waveform signal 3 6 and a comparator 6 8 that detects the jitter of the oscillation clock 3 2 using the first waveform signal 3 6. It has a configuration. When a new PLL circuit based on the present invention is newly designed, the configuration of the PLL circuit 10 A shown in FIG. 1 is used. However, when the present invention is applied to an existing PLL circuit, the configuration shown in FIG. A configuration of the PLL circuit 10 C is preferable.

In the P L L circuit 1 OC shown in this figure, a conventional P L L circuit 78 is incorporated. The PLL circuit 78 has the same configuration as the above-described conventional type, and specifically includes a phase comparison unit 60, a loop filter 62, an output unit 64, and a frequency division unit 70. .

In the PLL circuit 78, first, the phase comparison unit 60 compares the input reference clock 24 with the oscillation clock 32 through the frequency dividing unit 70. Then, the first correction signal 72 based on the phase difference between the oscillation clock 32 and the reference clock 24 is input to the loop filter 62 (low-pass filter). The second correction signal 74 from which the high-frequency component has been removed by the loop filter 62 is input to the output unit 64, which is a VCO, and an oscillation clock having a frequency corresponding to the potential of the input second correction signal 74. 3 2 is output.

Here, for example, if the frequency of the oscillation clock 3 2 is divided by 1/4 in the frequency divider, the oscillation clock 3 2 whose frequency is 1/4 and the reference clock 2 4 are synchronized. As a result, an oscillation clock 32 having a frequency four times that of the reference clock is obtained.

On the other hand, the reference clock 24 is also input to the compensator 66, and the compensator 66 generates the first waveform signal 36 synchronized with the reference clock 24. The generated first waveform signal 36 and oscillation clock 32 are input to the comparison unit 68. Here, the compensator 66 is equivalent to the signal generator 12 shown in FIG.

The comparison unit 68 samples the first waveform signal 36 at the timing of the oscillation clock 32 to obtain a sample value (first sample value). The comparison unit 68 also stores a sample value (second sample value) when an ideal first waveform signal without jitter is sampled at a predetermined timing. Then, the comparison unit 68 compares the first sample value and the second sample value, and generates a third correction signal 76 based on the phase difference between the two. The generated third correction signal 76 is input to the output unit 64 together with the second correction signal 74, and the frequency of the oscillation clock 32 oscillated from the output unit 64 is adjusted.

The path through which the oscillation clock 3 2 is input from the output unit 6 4 to the comparison unit 68 and the third correction signal 7 6 is input from the comparison unit 68 to the output unit 6 4 forms one loop. ing. Therefore, the PLL circuit 10 C can be regarded as a configuration obtained by adding this loop to the conventional PLL circuit 78. In addition to the second correction signal 74, the third correction signal 76 is also input to the output unit 64, whereby the jitter included in the oscillation clock 32 is reduced. Specifically, in the conventional PLL circuit 78, since the comparison by the phase comparison unit 60 is performed at the timing of the reference clock 24, the number of comparisons per unit time is not sufficient, and jitter is reduced. There were limits. Here, in addition to the phase comparison unit 60, the frequency of the oscillation clock 32 output from the output unit 64 is also adjusted by the comparison unit 6 8. Then, the comparator 68 detects the jitter of the oscillation clock 32 at the timing of the oscillation clock 32 whose frequency is higher than that of the reference clock 24, and generates a third correction signal 76 for correcting this jitter. Has been. Furthermore, in the present embodiment, the restriction on the sensitivity function and the phase sensitivity function can be reduced. Here, the sensitivity function is a function representing the degree to which the noise generated inside the loop is given to the output. The phase capture sensitivity function is a function that represents the degree to which the noise contained in the input reference clock is given to the output, and is a function that becomes 1 when added to the sensitivity function.

Specifically, in this embodiment, since oversampling is performed at the timing of the oscillation clock, the loop gain can be increased. Therefore, the sensitivity function to noise is reduced, and the influence of noise inside the loop on the output is reduced.

However, when the value of the sensitivity function is reduced in this way, the value of the complementary sensitivity function, which has the property of 1 when added to this sensitivity function, increases, and the effect of the noise included in the reference clock on the output increases.

In order to alleviate the problem of this complementary sensitivity function, it is effective to remove noise contained in the reference clock using a smoothing filter. In the present embodiment, adjusting the waveform of the first waveform signal 36 in the signal generator 12 produces the same effect as having a smoothing filter. The problem is mitigated.

However, if the signal generation unit 12 having the same properties as the filter is provided, there arises a problem that the signal generation unit 12 cannot quickly follow the fluctuation of the original reference clock. Furthermore, there was a problem that the lock-up time, which is the biggest problem at startup, is slow.

Therefore, in the present embodiment, a signal generation unit 12 having a configuration described below with reference to FIG. 12 is employed.

Details of the signal generator 12 shown in FIG. 1 will be described with reference to FIG. Fig. 12 (A), Fig. 12 (B) and Fig. 12 (C) show signal generators 1 2 A, 1 2 B, and 1 2 C having different configurations. FIG. 12 (D) is a waveform diagram showing waveforms of the first waveform signal 36 and the like. Here, the first waveform signal 36 6 shows a saw-shaped digital signal with a constant increment. Here, an analog signal may be employed as the first waveform signal 36 as described above.

As described above, in this Rakumei, the first waveform signal 36 is generated by the signal generator 12 shown in FIG. 1, and this signal is sampled by the oscillation clock 32 to detect the phase difference. And have a feed pack. Therefore, in the present invention, the shape of the first waveform signal 36 is important. If this signal has a predetermined shape, the jitter becomes extremely small. If this signal has an error, the phase difference is calculated. This also includes errors, and jitter characteristics deteriorate.

Therefore, in the present invention, the value at the end of one cycle of the generated first waveform signal 36 is compared with a predetermined value, and the first waveform signal in the next cycle is compared based on the difference between the two values. 3 The increment of 6 is adjusted. This matter is specifically explained below.

Referring to FIG. 12 (A), signal generation unit 12 A includes a period measurement unit 80, an inverse operation unit 8 2, and an integration unit 8 4. The period measuring unit 80 is a part that measures the period T of the input reference clock 24, and the reciprocal (1 / T) of the measured period T is calculated by the reciprocal computing unit 8 2. Then, by integrating the reciprocal 1 "T over the period T, the integration unit 84 generates a sawtooth first waveform signal 3 6.

According to the signal generation unit 1 2 の having the above-described configuration, it is possible to simply generate the first waveform signal 36. However, in the integrator described above, the first waveform signal 36 is generated by integrating 1 / T, which is the reciprocal of the period. Bit division is required. If multi-bit division is performed, the circuit scale may increase or the time required for calculation may increase.

Therefore, in the present invention, in order to improve the accuracy of the first waveform signal 36, the calculation processing of the reciprocal calculation unit 82 is not complicated, but the error of the generated first waveform signal 36 is fed-packed. It is said. The configuration of the signal generation unit 12 B shown in FIG. 12 (B) is the same as the configuration in which the comparison unit 86 is added after the integration unit 84 in addition to the signal generation unit 12 A described above. . The comparator 8 6 compares the peak value of the sawtooth wave generated by the integrator 8 4 (the value at the end of the reference clock 24) with a predetermined value (2 π) to determine the error between the two. Is feed-packed in the integration part 8 4. In other words, the increment (1 ZT) in the integration unit 84 is corrected according to the value of the feed-packed error. By performing the correction using the feed pack in this way, even if the division accuracy of the reciprocal calculation unit 82 is not high, if the frequency of the input reference clock 24 is constant, the correction by the comparison unit 86 causes the integration unit 84 to perform correction. Thus, the accuracy of the first waveform signal 36 generated is improved. In addition, the circuit scale required for the above-mentioned feed pack is smaller than the circuit required for configuring a high-precision divider, so that the circuit scale of the entire apparatus can be reduced. it can.

In addition, the accuracy of the first waveform signal 36 is not guaranteed immediately after the frequency of the input reference clock 24 changes. However, jitter does not matter immediately after the frequency of the reference clock 24 changes.

The configuration of the signal generator 12 C shown in FIG. 12 (C) is basically the same as that of the signal generator 12 B described above. The difference is that the error detected by the comparator 86 is applied to the reciprocal calculator 82. It is to be feed-packed. In this way, when an error is detected by the comparator 86, the time until the peak value of the first waveform signal 36, which is a sawtooth wave, becomes a predetermined value (2π) can be shortened. is there. That is, as shown in the waveform diagram of FIG. 12 (D), even if the peak value of the first waveform signal 36 becomes larger than a predetermined value (2π) in a certain period of the reference clock 24, By performing the feed pack shown in FIG. 12 (C), the peak value of the first waveform signal 36 can be corrected to a predetermined value (2π) in the next cycle.

Details of this will be described below with reference to FIGS. 12 (C) and 12 (D). First, suppose that the result of the reciprocal calculation of the reciprocal number calculation unit 82 is not 1 / T with respect to the period leap second of the reference clock 24 measured by the period measurement unit 80, and an error occurs τ. If an error occurs in the reciprocal calculation unit 82 in this way, the peak value of the first waveform signal 36 does not become 2π at the timing T1 shown in FIG. 12 (D), and a larger value ( Or a small value).

And by integrating this _τ for leap seconds, the difference from 2π is obtained as follows.

Equation 1: 2 π τ Τ— 2 π = 2 π (τΤ— 1)

Furthermore, after dividing the value obtained by Equation 1 by 2 πΤ with a divider and subtracting it from τ, Equation 2: τ— 2π (τΤ-1) / 2 π Τ = τ-τ + 1 / Τ = 1 / Τ

It becomes. That is, even if an error is included in the calculation result calculated by the reciprocal calculation unit 82, the increment of the integration unit 84 is converged to 1ΖΤ by the one correction operation described above. That is, the peak value of the first waveform signal 36 at the end (終端 2) of the next period in which the error has occurred is set to a predetermined value of 2π. The above principle is similar to the measurement of weight using, for example, a balance. Specifically, with a balance, the weight of the weight is equal to the weight of the object to be measured when the balance is horizontally leveled while observing the inclination of the balance. In the above, the weight of the weight, τ is integrated for T seconds and 2 π is subtracted, and it can be regarded as the inclination of the balance. The value [2π (ττ-1)] obtained by the above equation 1 is the error of the peak value of the first waveform signal 36 when an error occurs in the result of the reciprocal calculation. In Equation 2, the value calculated in Equation 1 is divided by 2πΤ using a divider (reciprocal calculation unit 82) to calculate the total correction amount. By doing so, the weight of the weight is corrected appropriately by a single correction, and the balance is always level. Even if the frequency of the reference clock changes, the signal generation unit 12 having the above-described configuration can make the first waveform signal follow the change at high speed and can make a sound.

When the PLL circuit locks and stabilizes, the correction of the signal generator 12 by the first waveform signal 36 is reduced, and the effect as a smoothing filter is increased to return to the normal filter characteristics. . As described above, in the present embodiment, the problem of the complementary sensitivity function is solved, and the effect of talent sampling is derived.

Next, the effect of the PLL circuit of the present invention having the above configuration will be described with reference to FIGS. 13 to 15. FIG.

Referring to FIG. 13, the PLL circuit of the present invention is compared with the conventional PLL circuit from the viewpoint of step response. Here, the experiment is performed by measuring the value of the voltage applied to the VCO (output section shown in Fig. 1) when the frequency of the reference clock input to the PLL circuit is changed. Here, in each figure of FIG. 13, the horizontal axis shows the elapsed time from when the frequency of the input reference clock is changed, and the vertical axis shows the voltage value applied to the VCO. If the voltage applied to the VCO is constant, the frequency of the oscillation clock output from the VCO is stable. If the voltage value fluctuates, the frequency of the oscillation clock output from V co is unstable. It shows that there is.

Figure 13 (A) shows the results of the above experiment for a conventional PLL circuit. Figures 13 (B) to 13 (D) show the common magnifications of 4 and 8 respectively. The experimental results for the PLL circuit of the present invention of 16 times are shown. Here, in the PLL circuit of the present invention, sampling is performed at the same timing as the oscillation clock to be output, so the above-described power factor is equal to the ratio of the number of samplings.

Referring to Fig. 13 (A), in the conventional PLL circuit, when the frequency of the input reference clock changes, the voltage value rises and is not stable at a constant value. Specifically, the frequency of the reference clock changes The voltage value is not stable even after 0.035 sec. From this, it can be understood that it is difficult to set the natural angular frequency high in the conventional PLL circuit.

Referring to Fig. 13 (B), in the PLL circuit of the present invention in which the total magnification is 4, the voltage value becomes unstable immediately after the frequency of the reference clock changes, but about 0. lsec has elapsed. At that point, the voltage value is stable. Thus, the reason why the voltage of the PLL circuit of the present invention is stabilized earlier than that of the conventional PLL circuit is that the number of times of correction by sampling is larger than that of the conventional example.

Referring to FIG. 13 (C), in the PLL circuit of the present invention in which the power factor is 8, the voltage value stabilizes when 0.005 seconds have elapsed since the frequency of the reference clock changed. Yes.

Furthermore, referring to FIG. 13 (D), in the present invention in which the total magnification is 16, the time until the voltage value is stabilized is further shortened, and the voltage value is stabilized when 0.002 sec elapses.

From the above, according to the PLL circuit of the present invention, since the time from when the frequency of the reference clock changes until the voltage value applied to VC O stabilizes, the natural angular frequency is set high. it can. That is, the PLL circuit of the present invention has a better frequency step response than the conventional circuit.

Referring to FIG. 14, an experiment in which the relationship between the phase comparison frequency and the jitter was examined for both the conventional PLL circuit and the PLL circuit of the present invention will be described. Here, FIG. 14 (A) shows the experimental results of the conventional PLL circuit, and FIG. 14 (B) shows the experimental results of the PLL circuit of the present invention. In the graphs shown in Figs. 14 (A) and 14 (B), the horizontal axis shows the frequency of the oscillation clock output from the VCO, and the vertical axis shows the jitter ratio.

And here, we experimented by changing the damping factor ζ of the low-pass filter provided in the PLL circuit. Specifically, we changed the value of ζ to 0.1, 0.7 and 1.2. An experiment was conducted. Here, the damping factor is an index indicating the characteristics of the low-pass filter, and the damping factor of the low-pass filter built in the PLL circuit is generally about 0.7.

Comparing the experimental results using the conventional PLL circuit shown in Fig. 14 (Α) with the experimental results using the PLL circuit of the present invention shown in Fig. 14 (B), It can be seen that there is little jitter. Note that the experimental results shown in FIG. 14 (B) are obtained by using the PLL circuit of the present invention in which the magnification is 8 times.

Specifically, referring to FIG. 14 (A), it is shown that the jitter increases when the damping factor ζ is large. In particular, when ζ = 1.2, the divisor included in the VCO output is It is shown that the percentage of scatter is 20% or more. Furthermore, this jitter ratio does not depend on the frequency. The jitter ratio is high even when the frequency of the oscillation clock output from the VCO is 15 kHz, and it is also high at 35 kHz.

On the other hand, referring to FIG. 14 (B), the jitter ratio is smaller than that of the conventional example in any case of ζ. In particular, in the case of ζ = 1.2, the ratio of jitter is less than 1/4 compared to the conventional example shown in Fig. 14 (iii).

From the above experimental results, it became clear that the amount of jitter contained in the output of the VCO can be reduced with the PLL circuit of the present invention regardless of the value of ζ.

Referring to Fig. 15, the results of experiments conducted by applying the conventional PLL circuit and the PLL circuit of the present invention to a digital-to-analog converter (DAC) will be described. . In the graph shown in this figure, the horizontal axis represents the frequency of the audio signal output from the audio with the built-in DAC including the PLL circuit. The vertical axis shows total harmonic distortion (referred to as THD). THD indicates the amount of jitter contained in the output signal. Here, we conducted experiments by changing the amount of jitter applied to the input and the frequency of the audio signal for both the conventional PLL circuit and the PLL circuit of the present invention. In this graph, the results of experiments performed on a conventional PLL circuit are indicated by dotted lines, and the results of experiments performed on the PLL circuit of the present invention are indicated by solid lines.

As is apparent from this graph, in the conventional PLL circuit, the THD value increases as the audio frequency increases. In addition, the input jitter increases and the THD value also increases. For this reason, in an audio device incorporating a conventional PLL circuit, if jitter is included in the input, noise will be prominent, especially in the high frequency band.

-On the other hand, the experimental results of the equipment using the PLL circuit of the present invention are indicated by a solid line in the graph, and the THD value is extremely small as compared with the above-mentioned conventional example. For this reason, when the PLL circuit of the present invention is applied to an audio device, the adverse effect of input jitter on the output can be well eliminated.

Claims

The scope of the claims

1. In a PLL circuit that outputs an oscillation clock multiplied by a reference clock and corrects the oscillation clock using a correction signal based on a phase difference between the reference clock and the oscillation clock.

A signal generator for generating a first waveform signal having synchronism with the reference clock;

A sample unit that samples the first waveform signal at a frequency higher than the reference clock to obtain a first sample value;

A comparison unit that compares the first sample value with a second sample value obtained by sampling a second waveform signal based on a waveform when the PLL circuit is in a stable state, and outputs the correction signal based on a difference between the two sample values; An output unit that outputs the oscillation clock corrected based on a correction signal. A PLL circuit comprising:

2. The PLL circuit according to claim 1, wherein the first waveform signal is sampled by the oscillation clock in the sample unit.

3. The PLL circuit according to claim 1, wherein the first waveform signal has a waveform that increases or decreases during one cycle of the reference clock.

4. The PLL circuit according to claim 1, further comprising a storage unit that stores the waveform of the stable state or the second sample value obtained by sampling the waveform of the stable state.

5. The PLL circuit according to claim 1, further comprising a control unit that converts the correction signal and controls the output unit.

6. The PLL circuit according to claim 1, wherein the first waveform signal has a curvilinear shape.

7. The PLL circuit according to claim 1, wherein the first waveform signal has a sine wave, cosine wave, triangular wave or sawtooth wave shape.

8. The method further comprises a first frequency dividing unit that divides the oscillation clock that is fed back from the output unit to the sample unit and used for sampling the first waveform signal. PLL circuit described in the first section of the range.

9. A first frequency divider that divides the oscillation clock that is fed back from the output unit to the sample unit and used to sample the first waveform signal; 2. The PLL circuit according to claim 1, further comprising: a second frequency dividing unit that divides the reference clock input to the signal generating unit.

10. The PLL circuit according to claim 1, wherein the first waveform signal is an analog waveform or a digital waveform.

1 1. The first waveform signal is a signal having a constant increment,

The range of the first waveform signal in the next period is made different when the value of the first waveform signal at the end of one period of the reference clock is different from a predetermined value. The PLL circuit according to item 1.

1 2. The signal generation unit is configured to perform an integration based on the reciprocal, a period measurement unit that measures the period of the input reference clock, an reciprocal operation unit that calculates the reciprocal of the measured period, and An integration unit that generates the first waveform signal having a sawtooth shape by an error calculating unit that calculates an error of the first waveform signal at the end of one cycle of the reference clock.

2. The PLL circuit according to claim 1, wherein an increment of the sawtooth wave in the integrating unit is adjusted based on the error.

1 3. In a control device for correcting the characteristics of the output signal using a correction signal indicating a difference between the input signal and the output signal,

A signal generator for generating a first waveform signal having synchronism with the input signal;

A sampler section that samples the first waveform signal at a frequency higher than the cycle of the input signal to obtain a first sample value;

A comparator that compares the first sample value with a second sample value obtained by sampling a second waveform signal based on a waveform when the control device is in a stable state, and outputs the correction signal based on the difference between the two sample values;

An output unit that outputs the output signal corrected based on the correction signal. A control device comprising: