WO2008120387A1 - 容量セル、集積回路、集積回路設計方法および集積回路製造方法 - Google Patents

容量セル、集積回路、集積回路設計方法および集積回路製造方法 Download PDF

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Publication number
WO2008120387A1
WO2008120387A1 PCT/JP2007/056968 JP2007056968W WO2008120387A1 WO 2008120387 A1 WO2008120387 A1 WO 2008120387A1 JP 2007056968 W JP2007056968 W JP 2007056968W WO 2008120387 A1 WO2008120387 A1 WO 2008120387A1
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
capacitor cell
manufacturing
capacitor
cell
Prior art date
Application number
PCT/JP2007/056968
Other languages
English (en)
French (fr)
Inventor
Katsunao Kanari
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to JP2009507376A priority Critical patent/JP5077343B2/ja
Priority to CN2007800523962A priority patent/CN101647111B/zh
Priority to KR1020097016621A priority patent/KR101146201B1/ko
Priority to PCT/JP2007/056968 priority patent/WO2008120387A1/ja
Priority to EP07740406.9A priority patent/EP2133911B1/en
Publication of WO2008120387A1 publication Critical patent/WO2008120387A1/ja
Priority to US12/461,301 priority patent/US8185855B2/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H01L27/0811—MIS diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

　本発明の一実施形態に係る容量セルは、セル枠２における電源配線位置および接地配線位置まで、静電容量を蓄積するためのゲートポリ６を拡大する。なお、セル枠２における電源配線位置および接地配線位置までゲートポリ６を拡大する場合に限られるものではなく、電源配線位置または接地配線位置のどちらか一方にゲートポリ６を拡大するようにしてもよい。このように、容量セルにおいて静電容量の蓄積量に主に関係する拡散層３とゲートポリ６との重複部分の面積（Ｘ×Ｙ）が拡大される。
PCT/JP2007/056968 2007-03-29 2007-03-29 容量セル、集積回路、集積回路設計方法および集積回路製造方法 WO2008120387A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2009507376A JP5077343B2 (ja) 2007-03-29 2007-03-29 容量セル、集積回路、集積回路設計方法および集積回路製造方法
CN2007800523962A CN101647111B (zh) 2007-03-29 2007-03-29 电容单元、集成电路、集成电路设计方法以及集成电路制造方法
KR1020097016621A KR101146201B1 (ko) 2007-03-29 2007-03-29 용량 셀, 집적회로, 집적회로 설계 방법 및 집적회로 제조 방법
PCT/JP2007/056968 WO2008120387A1 (ja) 2007-03-29 2007-03-29 容量セル、集積回路、集積回路設計方法および集積回路製造方法
EP07740406.9A EP2133911B1 (en) 2007-03-29 2007-03-29 Capacitor cell, integrated circuit, integrated circuit designing method, and integrated circuit manufacturing method
US12/461,301 US8185855B2 (en) 2007-03-29 2009-08-06 Capacitor-cell, integrated circuit, and designing and manufacturing methods

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/056968 WO2008120387A1 (ja) 2007-03-29 2007-03-29 容量セル、集積回路、集積回路設計方法および集積回路製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/461,301 Continuation US8185855B2 (en) 2007-03-29 2009-08-06 Capacitor-cell, integrated circuit, and designing and manufacturing methods

Publications (1)

Publication Number Publication Date
WO2008120387A1 true WO2008120387A1 (ja) 2008-10-09

Family

ID=39807978

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/056968 WO2008120387A1 (ja) 2007-03-29 2007-03-29 容量セル、集積回路、集積回路設計方法および集積回路製造方法

Country Status (6)

Country Link
US (1) US8185855B2 (ja)
EP (1) EP2133911B1 (ja)
JP (1) JP5077343B2 (ja)
KR (1) KR101146201B1 (ja)
CN (1) CN101647111B (ja)
WO (1) WO2008120387A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019110205A (ja) * 2017-12-18 2019-07-04 富士通株式会社 回路素子及び回路素子の使用方法
JP2021153078A (ja) * 2020-03-24 2021-09-30 株式会社東芝 半導体装置

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012222065A (ja) 2011-04-06 2012-11-12 Panasonic Corp 半導体集積回路装置
US11347925B2 (en) * 2017-05-01 2022-05-31 Advanced Micro Devices, Inc. Power grid architecture and optimization with EUV lithography
US11211330B2 (en) 2017-05-01 2021-12-28 Advanced Micro Devices, Inc. Standard cell layout architectures and drawing styles for 5nm and beyond
US11658250B2 (en) * 2020-11-03 2023-05-23 Qualcomm Incorporated Metal-oxide semiconductor (MOS) capacitor (MOSCAP) circuits and MOS device array bulk tie cells for increasing MOS device array density

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002313937A (ja) * 2001-04-16 2002-10-25 Sony Corp 集積回路装置
JP2004335902A (ja) 2003-05-12 2004-11-25 Matsushita Electric Ind Co Ltd 半導体集積回路の設計方法

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Publication number Priority date Publication date Assignee Title
JPS61294834A (ja) 1985-06-24 1986-12-25 Nec Corp 半導体集積回路ブロツク
JPH02144936A (ja) * 1988-11-28 1990-06-04 Hitachi Ltd 半導体集積回路装置
JPH04111462A (ja) 1990-08-31 1992-04-13 Fujitsu Ltd 半導体装置
JP2682397B2 (ja) * 1993-10-07 1997-11-26 日本電気株式会社 セルベース設計半導体集積回路装置
JP2001007293A (ja) * 1999-06-25 2001-01-12 Mitsubishi Electric Corp 半導体集積回路装置
JP4156827B2 (ja) * 2001-11-21 2008-09-24 松下電器産業株式会社 半導体装置、半導体装置用パターンの生成方法、半導体装置の製造方法、および半導体装置用パターン生成装置
US6775812B2 (en) * 2002-07-17 2004-08-10 Hewlett-Packard Development Company, L.P. Layout design process and system for providing bypass capacitance and compliant density in an integrated circuit
JP2004186417A (ja) * 2002-12-03 2004-07-02 Renesas Technology Corp 半導体集積回路装置
JP4111462B2 (ja) 2004-01-28 2008-07-02 株式会社リコー 画像形成装置
US7309906B1 (en) * 2004-04-01 2007-12-18 Altera Corporation Apparatus and methods for providing highly effective and area efficient decoupling capacitance in programmable logic devices
JP2006202923A (ja) * 2005-01-19 2006-08-03 Nec Electronics Corp 半導体装置の設計方法、半導体装置の設計プログラム
JP4725155B2 (ja) * 2005-03-25 2011-07-13 日本電気株式会社 半導体集積回路のレイアウト設計方法及び設計装置
US7728362B2 (en) * 2006-01-20 2010-06-01 International Business Machines Corporation Creating integrated circuit capacitance from gate array structures

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002313937A (ja) * 2001-04-16 2002-10-25 Sony Corp 集積回路装置
JP2004335902A (ja) 2003-05-12 2004-11-25 Matsushita Electric Ind Co Ltd 半導体集積回路の設計方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019110205A (ja) * 2017-12-18 2019-07-04 富士通株式会社 回路素子及び回路素子の使用方法
JP2021153078A (ja) * 2020-03-24 2021-09-30 株式会社東芝 半導体装置
US11532545B2 (en) 2020-03-24 2022-12-20 Kabushiki Kaisha Toshiba Semiconductor device
JP7286581B2 (ja) 2020-03-24 2023-06-05 株式会社東芝 半導体装置

Also Published As

Publication number Publication date
CN101647111B (zh) 2011-04-13
KR101146201B1 (ko) 2012-05-24
KR20100004953A (ko) 2010-01-13
US20090302422A1 (en) 2009-12-10
JPWO2008120387A1 (ja) 2010-07-15
EP2133911A1 (en) 2009-12-16
EP2133911A4 (en) 2012-08-01
US8185855B2 (en) 2012-05-22
CN101647111A (zh) 2010-02-10
EP2133911B1 (en) 2014-11-19
JP5077343B2 (ja) 2012-11-21

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