WO2008117355A1 - 半導体基板製造装置、半導体基板製造方法及び半導体基板 - Google Patents

半導体基板製造装置、半導体基板製造方法及び半導体基板 Download PDF

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Publication number
WO2008117355A1
WO2008117355A1 PCT/JP2007/055877 JP2007055877W WO2008117355A1 WO 2008117355 A1 WO2008117355 A1 WO 2008117355A1 JP 2007055877 W JP2007055877 W JP 2007055877W WO 2008117355 A1 WO2008117355 A1 WO 2008117355A1
Authority
WO
WIPO (PCT)
Prior art keywords
light
semiconductor
semiconductor substrate
substrate
substrate manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/055877
Other languages
English (en)
French (fr)
Inventor
Hideo Ochi
Atsushi Yoshizawa
Hideo Satoh
Takashi Chuman
Satoru Ohta
Chihiro Harada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Corp filed Critical Pioneer Corp
Priority to PCT/JP2007/055877 priority Critical patent/WO2008117355A1/ja
Priority to US12/450,229 priority patent/US20100044890A1/en
Priority to JP2009506068A priority patent/JPWO2008117355A1/ja
Publication of WO2008117355A1 publication Critical patent/WO2008117355A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/50—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for positioning, orientation or alignment
    • H10P72/53—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for positioning, orientation or alignment using optical controlling means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/40—Thermal treatment, e.g. annealing in the presence of a solvent vapour
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0241—Manufacture or treatment of multiple TFTs using liquid deposition, e.g. printing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroluminescent Light Sources (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

プラスチック基板などの伸縮性を有する基板の表面に広範囲に亘って形成される多数の半導体形成領域に対して、基板が伸縮しても、アニール処理や半導体材料の塗布などの所定の処理を高精度に行う半導体基板製造装置を提供する。 トラッキングしながら基板表面に光を照射する発光部（３４）と、この発光部（３４）から照射されて前記基板表面に反射した光を受光する受光部（３５）と、受光した光のスペクトルまたは強度に基づいて前記基板上の半導体形成領域の位置を検出する位置検出部（３６）と、を有するトラッキング手段（３３）と、前記トラッキング手段（３３）からの位置情報に基づき、前記半導体形成領域のそれぞれに対して所定の処理を行う半導体処理手段として、例えばアニール光照射手段（３７）やインクジェットノズルを備えた構成とする。
PCT/JP2007/055877 2007-03-22 2007-03-22 半導体基板製造装置、半導体基板製造方法及び半導体基板 Ceased WO2008117355A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2007/055877 WO2008117355A1 (ja) 2007-03-22 2007-03-22 半導体基板製造装置、半導体基板製造方法及び半導体基板
US12/450,229 US20100044890A1 (en) 2007-03-22 2007-03-22 Semiconductor substrate manufacture apparatus, semiconductor substrate manufacture method, and semiconductor substrate
JP2009506068A JPWO2008117355A1 (ja) 2007-03-22 2007-03-22 半導体基板製造装置、半導体基板製造方法及び半導体基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/055877 WO2008117355A1 (ja) 2007-03-22 2007-03-22 半導体基板製造装置、半導体基板製造方法及び半導体基板

Publications (1)

Publication Number Publication Date
WO2008117355A1 true WO2008117355A1 (ja) 2008-10-02

Family

ID=39788100

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/055877 Ceased WO2008117355A1 (ja) 2007-03-22 2007-03-22 半導体基板製造装置、半導体基板製造方法及び半導体基板

Country Status (3)

Country Link
US (1) US20100044890A1 (ja)
JP (1) JPWO2008117355A1 (ja)
WO (1) WO2008117355A1 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100154870A1 (en) * 2008-06-20 2010-06-24 Nicholas Bateman Use of Pattern Recognition to Align Patterns in a Downstream Process

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04186725A (ja) * 1990-11-21 1992-07-03 Hitachi Ltd レーザアニール装置及びアライメント法
JP2000277451A (ja) * 1999-03-26 2000-10-06 Seiko Epson Corp 半導体製造装置
JP2003243304A (ja) * 2001-12-11 2003-08-29 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2004295121A (ja) * 2003-03-13 2004-10-21 Konica Minolta Holdings Inc Ｔｆｔシートおよびその製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01137238A (ja) * 1987-11-25 1989-05-30 Matsushita Electric Ind Co Ltd アクティブマトリックスアレイ
JPH02234116A (ja) * 1989-03-08 1990-09-17 Hitachi Ltd フラットディスプレイ装置の製造方法
JP3241251B2 (ja) * 1994-12-16 2001-12-25 キヤノン株式会社 電子放出素子の製造方法及び電子源基板の製造方法
JP3970546B2 (ja) * 2001-04-13 2007-09-05 沖電気工業株式会社 半導体装置及び半導体装置の製造方法
US7214573B2 (en) * 2001-12-11 2007-05-08 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device that includes patterning sub-islands
JP4956987B2 (ja) * 2005-12-16 2012-06-20 株式会社島津製作所 レーザー結晶化装置及び結晶化方法
TWI294185B (en) * 2006-04-14 2008-03-01 Au Optronics Corp Manufacturing method of a pixel structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04186725A (ja) * 1990-11-21 1992-07-03 Hitachi Ltd レーザアニール装置及びアライメント法
JP2000277451A (ja) * 1999-03-26 2000-10-06 Seiko Epson Corp 半導体製造装置
JP2003243304A (ja) * 2001-12-11 2003-08-29 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2004295121A (ja) * 2003-03-13 2004-10-21 Konica Minolta Holdings Inc Ｔｆｔシートおよびその製造方法

Also Published As

Publication number Publication date
US20100044890A1 (en) 2010-02-25
JPWO2008117355A1 (ja) 2010-07-08

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