WO2008111135A1 - デバイス間接続試験回路生成方法、生成装置、および生成プログラム - Google Patents

デバイス間接続試験回路生成方法、生成装置、および生成プログラム Download PDF

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Publication number
WO2008111135A1
WO2008111135A1 PCT/JP2007/000230 JP2007000230W WO2008111135A1 WO 2008111135 A1 WO2008111135 A1 WO 2008111135A1 JP 2007000230 W JP2007000230 W JP 2007000230W WO 2008111135 A1 WO2008111135 A1 WO 2008111135A1
Authority
WO
WIPO (PCT)
Prior art keywords
test
test circuit
creation
devices
connection
Prior art date
Application number
PCT/JP2007/000230
Other languages
English (en)
French (fr)
Inventor
Kohichi Tamai
Original Assignee
Fujitsu Microelectronics Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Microelectronics Limited filed Critical Fujitsu Microelectronics Limited
Priority to PCT/JP2007/000230 priority Critical patent/WO2008111135A1/ja
Priority to JP2009503778A priority patent/JP5099119B2/ja
Publication of WO2008111135A1 publication Critical patent/WO2008111135A1/ja
Priority to US12/538,460 priority patent/US7984343B2/en

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31707—Test strategies

Abstract

　単純な試験パターンデータを使用することができ、基板毎にカスタマイズする必要がない試験回路の生成を可能とし、試験の準備工程を大幅に短縮する。 　複数のデバイスのうちで相互に配線接続されるデバイスを示す接続関係と、その接続関係のそれぞれに対応する接続配線の本数と、試験結果を出力するデバイスとを示すデータの入力を受け取り、出力デバイスの出力端子側から接続相手先デバイスを順次探索し、試験ルート上に試験回路モジュールを埋め込んで接続試験回路を生成する。
PCT/JP2007/000230 2007-03-15 2007-03-15 デバイス間接続試験回路生成方法、生成装置、および生成プログラム WO2008111135A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2007/000230 WO2008111135A1 (ja) 2007-03-15 2007-03-15 デバイス間接続試験回路生成方法、生成装置、および生成プログラム
JP2009503778A JP5099119B2 (ja) 2007-03-15 2007-03-15 デバイス間接続試験回路生成方法、生成装置、および生成プログラム
US12/538,460 US7984343B2 (en) 2007-03-15 2009-08-10 Inter-device connection test circuit generating method, generation apparatus, and its storage medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/000230 WO2008111135A1 (ja) 2007-03-15 2007-03-15 デバイス間接続試験回路生成方法、生成装置、および生成プログラム

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/538,460 Continuation US7984343B2 (en) 2007-03-15 2009-08-10 Inter-device connection test circuit generating method, generation apparatus, and its storage medium

Publications (1)

Publication Number Publication Date
WO2008111135A1 true WO2008111135A1 (ja) 2008-09-18

Family

ID=39759086

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/000230 WO2008111135A1 (ja) 2007-03-15 2007-03-15 デバイス間接続試験回路生成方法、生成装置、および生成プログラム

Country Status (3)

Country Link
US (1) US7984343B2 (ja)
JP (1) JP5099119B2 (ja)
WO (1) WO2008111135A1 (ja)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105425088B (zh) * 2014-09-22 2018-08-28 神讯电脑(昆山)有限公司 基座的同轴通路测试装置
US9495496B2 (en) * 2014-12-18 2016-11-15 International Business Machines Corporation Non-invasive insertion of logic functions into a register-transfer level (‘RTL’) design
GB2581861B (en) * 2018-09-14 2022-10-05 Sino Ic Tech Co Ltd IC Test Information Management System Based on Industrial Internet

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07174821A (ja) * 1993-12-20 1995-07-14 Toshiba Corp バウンダリスキャンセルおよびテスト回路の検証方法
JPH1123667A (ja) * 1997-07-03 1999-01-29 Mitsubishi Electric Corp 回路装置の試験方法
JPH1144741A (ja) * 1997-07-25 1999-02-16 Fujitsu Ltd プログラマブルロジックデバイス及びその試験方法並びに試験用データ作成方法
JP2005283205A (ja) * 2004-03-29 2005-10-13 Nec Electronics Corp システム・イン・パッケージ及びその検証方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6347387B1 (en) * 1998-10-09 2002-02-12 Agere Systems Guardian Corp. Test circuits for testing inter-device FPGA links including a shift register configured from FPGA elements to form a shift block through said inter-device FPGA links
US6678645B1 (en) * 1999-10-28 2004-01-13 Advantest Corp. Method and apparatus for SoC design validation
JP4219655B2 (ja) * 2002-11-01 2009-02-04 富士通株式会社 デバイス間結線チェック方法
US7225416B1 (en) * 2004-06-15 2007-05-29 Altera Corporation Methods and apparatus for automatic test component generation and inclusion into simulation testbench

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07174821A (ja) * 1993-12-20 1995-07-14 Toshiba Corp バウンダリスキャンセルおよびテスト回路の検証方法
JPH1123667A (ja) * 1997-07-03 1999-01-29 Mitsubishi Electric Corp 回路装置の試験方法
JPH1144741A (ja) * 1997-07-25 1999-02-16 Fujitsu Ltd プログラマブルロジックデバイス及びその試験方法並びに試験用データ作成方法
JP2005283205A (ja) * 2004-03-29 2005-10-13 Nec Electronics Corp システム・イン・パッケージ及びその検証方法

Also Published As

Publication number Publication date
US7984343B2 (en) 2011-07-19
JP5099119B2 (ja) 2012-12-12
US20090295403A1 (en) 2009-12-03
JPWO2008111135A1 (ja) 2010-06-24

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