WO2008081426A1 - Eviter des erreurs dans une mémoire flash en utilisant des transformations de substitution - Google Patents

Eviter des erreurs dans une mémoire flash en utilisant des transformations de substitution Download PDF

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Publication number
WO2008081426A1
WO2008081426A1 PCT/IL2007/001567 IL2007001567W WO2008081426A1 WO 2008081426 A1 WO2008081426 A1 WO 2008081426A1 IL 2007001567 W IL2007001567 W IL 2007001567W WO 2008081426 A1 WO2008081426 A1 WO 2008081426A1
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Prior art keywords
cells
memory
string
states
input string
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PCT/IL2007/001567
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WO2008081426B1 (fr
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Idan Alrod
Eran Sharon
Simon Litsyn
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Ramot At Tel Aviv University Ltd.
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Publication of WO2008081426A1 publication Critical patent/WO2008081426A1/fr
Publication of WO2008081426B1 publication Critical patent/WO2008081426B1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/16—Protection against loss of memory contents
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Definitions

  • the present invention relates to flash memories and, more particularly, to methods of transforming data for more reliable storage in a flash memory.
  • Flash memory devices have been known for many years. Typically, each cell within a flash memory stores one bit of information. Traditionally, the way to store a bit has been by supporting two states of the cell - one state represents a logical "0" and the other state represents a logical "1". In a flash memory cell the two states are implemented by having a floating gate above the cell's channel (the area connecting the source and drain elements of the cell's transistor), and having two valid states for the amount of charge stored within this floating gate. Typically, one state is with zero charge in the floating gate and is the initial unwritten state of the cell after being erased (commonly defined to represent the "1" state) and another state is with some amount of negative charge in the floating gate (commonly defined to represent the "0" state).
  • the threshold voltage of the cell's transistor i.e. the voltage that has to be applied to the transistor's control gate in order to cause the transistor to conduct
  • the threshold voltage of the cell's transistor i.e. the voltage that has to be applied to the transistor's control gate in order to cause the transistor to conduct
  • Figure IA shows graphically how this works. Specifically, Figure IA shows the distribution of the threshold voltages of a large population of cells. Because the cells in a flash device are not exactly identical in their characteristics and behavior (due, for example, to small variations in impurity concentrations or to defects in the silicon structure), applying the same programming operation to all the cells does not cause all of the cells to have exactly the same threshold voltage. (Note that, for historical reasons, writing data to a flash memory is commonly referred to as “programming" the flash memory. The terms “writing” and “programming” are used interchangeably herein.) Instead, the threshold voltage is distributed similar to the way shown in Figure IA.
  • Cells storing a value of "1" typically have a negative threshold voltage, such that most of the cells have a threshold voltage close to the value shown by the left peak of Figure IA, with some smaller numbers of cells having lower or higher threshold voltages.
  • cells storing a value of "0" typically have a positive threshold voltage, such that most of the cells have a threshold voltage close to the value shown by the right peak of Figure IA, with some smaller numbers of cells having lower or higher threshold voltages.
  • MLC Multi Level Cells
  • one way to read the lower bit is first to compare the cell's threshold voltage to a reference comparison voltage F 1 and then, depending on the outcome of the comparison, to compare the cell's threshold voltage to either a zero reference comparison voltage or a reference comparison voltage F 2 .
  • Another way to read the lower bit is to compare the cell's threshold voltage unconditionally to both the zero reference voltage and V ⁇ . In either case, two comparisons are needed.
  • MBC devices provide a great advantage of cost - using a similarly sized cell one stores two bits rather than one.
  • MBC flash the average read and write times of MBC memories are longer than of SBC memories, resulting in lower performance.
  • the reliability of MBC is lower than SBC.
  • SBC the differences between the threshold voltage ranges in MBC are much smaller than in SBC.
  • a disturbance in the threshold voltage e.g. leaking of the stored charge causing a threshold voltage drift, interference from operations on neighboring cells, etc.
  • SBC a disturbance in the threshold voltage (e.g. leaking of the stored charge causing a threshold voltage drift, interference from operations on neighboring cells, etc.) that may have gone unnoticed in SBC because of the large gap between the two states, might cause an MBC cell to move from one state to another, resulting in an erroneous bit.
  • the end result is a lower quality specification of MBC cells in terms of data retention time or the endurance of the device to many write/erase cycles.
  • the present invention is mainly concerned with a specific source of error commonly called “Program Disturb” or “PD” for short.
  • the PD effect causes cells, that are not intended to be written, to unintentionally move from their initial left-most state to some other state.
  • the explanations herein assume the common practice, also used in Figures IA and IB, of drawing the threshold voltage axis such that its left direction represents lower values. This is an arbitrary practice and should not be construed to limit the scope of the present invention in any way).
  • Figure 2 which is identical to Figure 1 of the Chen patent, is a block diagram of a typical prior art flash memory device.
  • a memory cell array 1 including a plurality of memory cells M arranged in a matrix is controlled by a column control circuit 2, a row control circuit 3, a c-source control circuit 4 and a c-p-well control circuit 5.
  • Column control circuit 2 is connected to bit lines (BL) of memory cell array 1 for reading data stored in the memory cells (M), for determining a state of the memory cells (M) during a program operation, and for controlling voltage levels of the bit lines (BL) to promote the programming or to inhibit the programming.
  • BL bit lines
  • Row control circuit 3 is connected to word lines (WL) to select one of the word lines (WL), to apply read voltages, to apply programming voltages combined with the bit line voltage levels controlled by column control circuit 2, and to apply an erase voltage coupled with a voltage of a p- type region on which the memory cells (M) are formed.
  • C-source control circuit 4 controls a common source line connected to the memory cells (M).
  • C-p-well control circuit 5 controls the c-p-well voltage.
  • a page is the smallest unit of a NAND flash device whose cells can be programmed together.
  • a block is the smallest unit of a NAND flash device whose cells can be erased together.
  • the data stored in the memory cells (M) are read out by column control circuit 2 and are output to external I/O lines via an I/O line and a buffer in data input/output circuit 6.
  • Program data to be stored in the memory cells are input to the buffer in data input/output circuit 6 via the external I/O lines, and are transferred to the column control circuit 2.
  • the external I/O lines are connected to a controller 20.
  • Command data for controlling the flash memory device are input to a command interface connected to external control lines that are connected with controller 20.
  • the command data inform the flash memory of what operation is requested.
  • the input command is transferred to a state machine 8 that controls column control circuit 2, row control circuit 3, c-source control circuit 4, c-p-well control circuit 5 and data input/output circuit 6.
  • State machine 8 can output a status data of the flash memory such as READY/BUSY or PASS/FAIL.
  • Controller 20 is connected or connectable with a host system such as a personal computer, a digital camera, a personal digital assistant. It is the host that initiates commands, such as to store or read data to or from memory array 1, and provides or receives such data, respectively. Controller 20 converts such commands into command signals that can be interpreted and executed by command circuits 7. Controller 20 also typically contains buffer memory for the user data being written to or read from memory array 1.
  • a typical memory system includes one integrated circuit chip 21 that includes controller 20, and one or more integrated circuit chips 22 that each contain a memory array and associated control, input/output and state machine circuits. The trend, of course, is to integrate the memory array and controller circuits of a system together on one or more integrated circuit chips.
  • the memory system may be embedded as part of the host system, or may be included in a memory card that is removably insertable into a mating socket of host systems. Such a card may include the entire memory system, or the controller and memory array, with associated peripheral circuits, may be provided in separate cards.
  • the reason for the PD effect is easy to understand when reviewing the voltages applied to the cells of a NAND flash device when programming a page. When programming a page of cells, a relatively high voltage is applied to the word line connected to the control gates of the cells of the page. What decides whether a certain cell threshold voltage is increased as a result of this control gate voltage is the voltage applied to the bit line connected to that cell.
  • a cell that is not to be written with data (that is — that is to remain erased, representing an all-one state), has its bit line connected to a relatively high voltage level that minimizes the voltage difference across the cell.
  • a cell that is to be written has its bit line connected to low voltage, causing a large voltage difference across the cell, and resulting in the cell's threshold voltage getting increased, thus moving the cell to the right on the voltage axis of Figure IB and causing the cell's state to change.
  • PD is an effect in which when programming a page of cells, some cells that are intended to remain in the leftmost erased state end up in another state, resulting in bit errors when reading those cells.
  • PD effects can be empirically and statistically measured, and counter- measures in the form of error correction schemes may be applied to handle them. Flash device manufacturers are aware of this source of potential errors, and they take it into account when recommending to their customers the level of error correction the customers should use. So when a manufacturer of a two-bit-per-cell MBC flash device recommends a 4-bit ECC scheme (meaning that every 512 bytes of user data should be protected against the occurrence of up to four bit errors), he may base this recommendation on a statistical analysis that assumes a random data pattern stored into the device and on the probability that a PD-type error will occur under such circumstances. Obviously, other error sources and types are also taken into account in such calculations. Unfortunately, typical real-life user data are not random.
  • Measurements on real-life user files show that the various possible states of the cells do not have equal probability to occur. As the leftmost state of the cells is the default value of cells not being written to, this state is the most frequent. This is easy to understand - a section of memory not initialized, or not used within a file, very often corresponds to cells in the erased state.
  • the present invention deals with reducing the number of errors due to PD by manipulating the user data and controlling the actual sequences of voltage levels or states programmed into the flash memory. By making sure that only a limited fraction of the cells in the flash memory (or in a page of the flash memory) are programmed to the erase state, which is the state most vulnerable to the PD effect, we can minimize the amount of error due to PD.
  • the present invention is mainly concerned with reducing PD errors, it is also applicable for reducing the effect of other undesirable phenomena in the flash memory.
  • another error source in the flash memory is leakage of the stored charge from a cell's floating gate, causing a threshold voltage drift.
  • this error source is also influenced by the user data programmed into the flash memory over time. The reason for this is that the amount of charge leakage depends on the quality of the insulation layer between the floating gate and the conductive channel of the cell's transistor. However the quality of the insulation layer changes with time. The more charge transferred through the insulation layer by applying high stress in the form of high voltage levels differences across the insulation layer, the weaker the insulation layer becomes.
  • a cell that has sustained many programming and erase (P/E) cycles exhibits a higher error rate than a cell that has sustained few P/E cycles.
  • P/E programming and erase
  • the cell that has been programmed to higher voltage levels is expected to exhibit a higher error rate than the other cell due to the higher stress applied to the insulation layer of the cell that has been programmed to higher voltage levels.
  • the error rates of a flash device due to P/E cycles also depend on the user data that have been programmed to the flash device. If the user data are statistically distributed in such a way that higher voltage levels are frequently programmed, then the flash memory device will suffer from higher error rates and become less reliable.
  • flash memory device that is more reliable than prior art flash memory devices in the sense of being less vulnerable to phenomena such as PD, especially when used in real-life scenarios where user data are not random and the actual voltage levels programmed into the flash memory are not uniformly distributed over all possible voltage levels.
  • a cell error As a cell being read as being in a state other than the state to which the cell was programmed.
  • cell errors result in errors in the bits read from the flash.
  • each cell in the flash can be programmed to L different voltage levels or states. Normally, this means that each cell can store up to N - ⁇ og 2 L bits; but see also US Patent No. 6,469,931 to Ban and US Patent Application No. 11/540,560 to Litsyn et al. in which this relationship does not strictly hold.
  • N of bits programmed into the cell is not necessarily the same as the number of information bits per cell: if, as normally is the case, error correction encoding is applied to the input data, the number of information bits per cell is NR, where R is the ECC rate.
  • a distribution of states over a set of cells in a flash memory device is a sequence of L numbers. Each number corresponds to one possible cell state. This number is equal to the number of cells in the set that are programmed to this state. We say that such states distribution is "good” if it meets certain criteria. The criteria for a good distribution depend on our knowledge of the various physical phenomena in the flash memory that are responsible for data dependent errors and of the statistics of the data generated by the user application.
  • a good states distribution with respect to the PD effect is a distribution in which the fraction of cells programmed to the erase state is minimized, or is smaller than some threshold.
  • a more "sophisticated" definition of a good states distribution would require that both low and high voltage level states be programmed less frequently. This would reduce the overall effect of various undesirable phenomena such as PD and such as increased charge leakage due to faster cell insulation layer weakening.
  • the flash memory device will suffer from higher error rates and become less reliable.
  • a method of storing an input string of MiV-tuples of bits including the steps of: (a) selecting, in accordance with the input string, a substitution transformation to apply to the input string; (b) applying the selected substitution transformation to the input string, thereby providing a transformed string of M N- tuples of bits; and (c) programming at least M cells of a memory to represent the transformed string.
  • a method of storing an input string of M iV-tuples of bits including the steps of: (a) providing a memory that is operative to selectively program each of at least M cells to a respective one of 2 N states of the each cell; (b) selecting, in accordance with the input string, a mapping that maps each binary number from 0 through 2 N - ⁇ into a respective one of the states; and (c) programming M the cells to represent the input string in accordance with the selected mapping.
  • a memory including: (a) at least M nonvolatile memory cells; and (b) circuitry for storing an input string of MiV-tuples of bits in the nonvolatile memory cells, wherein N>1, by steps including: (i) selecting, in accordance with the input string, a substitution transformation to apply to the input string, (ii) applying the selected substitution transformation to the input string, thereby providing a transformed string of M N- tuples of bits, and (iii) programming at least M of the cells to represent the transformed string.
  • a memory device including: (a) a memory including at least M nonvolatile memory cells; and (b) a controller for storing an input string of M TV-tuples of bits in the memory, wherein N>1, by steps including: (i) selecting, in accordance with the input string, a substitution transformation to apply to the input string, (ii) applying the selected substitution transformation to the input string, thereby providing a transformed string of M iV-tuples of bits, and (iii) instructing the memory to program at least M of the cells to represent the transformed string.
  • a system including: (a) a first nonvolatile memory that includes at least M nonvolatile memory cells; and (b) a host, of the first nonvolatile memory, that includes: (i) a host memory for storing an input string of M iV-tuples of bits, wherein N> ⁇ , (ii) a second nonvolatile memory for storing a driver for the first nonvolatile memory, the driver including code for: (A) selecting, in accordance with the input string, a substitution transformation to apply to the input string, and (B) applying the selected substitution transformation to the input string, thereby providing a transformed string of M N- tuples to be stored in the first nonvolatile memory by programming at least M of the cells to represent the transformed string, and (C) storing the transformed string in the first nonvolatile memory, and (iii) a processor for executing the code of the driver.
  • a computer- readable storage medium having computer-readable code embedded thereon, the computer-readable code being driver code for a memory device that includes at least M memory cells, the computer-readable code including: (a) program code for selecting, in accordance with an input string of M ⁇ V-tuples of bits, wherein N> ⁇ , a sustitution transformation to apply to the input string; and (b) program code for applying the selected transformation to the input string, thereby providing a transformed string of MiV-tuples to be stored in the memory device by prograirrrning at least M of the memory cells to represent the transformed string.
  • a memory including: (a) at least M nonvolatile memory cells; and (b) circuitry for storing an input string of M JV-tuples of bits in the nonvolatile cells, wherein JV>1, by steps including: (i) selectively programming each cell to represent each binary number from 0 through 2 ⁇ -1 as a respective one of 2 N states of the each cell, (ii) selecting, in accordance with the input string, a mapping that maps the binary numbers into the respective states thereof, and (iii) programming M of the cells to represent the input string in accordance with the selected mapping.
  • a memory device including: (a) a memory including: (i) at least M nonvolatile memory cells, and (ii) circuitry for selectively programming each cell to represent each binary number from 0 through 2 ⁇ -1 as a respective one of 2 N states of the each cell, and (b) a controller for storing an input string of M iV-tuples of bits in the memory, wherein N> ⁇ , by steps including: (i) selecting, in accordance with the input string, a mapping that maps the binary numbers into the respective states thereof, and (ii) instructing the circuitry to program M of the cells to represent the input string in accordance with the selected mapping.
  • One basic method of the present invention is a method of storing an input string of M N-tuples of bits.
  • N is an integer greater than 1.
  • a substitution transformation is selected to apply to the input string.
  • a "substitution transformation” is a substitution cipher in which the "alphabet” is the set of binary numbers from 0 through 2 ⁇ -1.
  • the substitution transformations are substitution ciphers in which the "alphabet" is the binary numbers 00, 01, 10 and 11.
  • the substitution transformation is selected in accordance with the input string, so that different input strings could get different substitution transformations applied to them.
  • the selected substitution transformation is applied to the input string, thereby providing a transformed string of MiV-tuples of bits. M or more cells of a memory then are programmed to represent the transformed string. That the substitution transformation is selected in accordance with the input string distinguishes the present invention from prior art methods in which an input string is encrypted prior to being stored, because in those prior art methods the same encryption transformation is applied to all input strings. That the input string and the transformed string have the same number of bits distinguishes the substitution transformation of the present invention from prior art adaptive compression algorithms.
  • the memory is operative to selectively program each of its cells to represent each binary number from 0 through 2 -1 as a respective one of 2 N states of the cell that are ordered from a lowest state to a highest state.
  • the selected substitution transformation is such that the binary number that is represented as the lowest state is the JV-tuple that occurs least often in the transformed string.
  • the memory is operative to selectively program each of its cells to represent each binary number from 0 through 2 ⁇ -1 as a respective one of 2 N states of the cell.
  • the selected substitution transformation is such that a first one of those binary numbers occurs at most as often as, or alternatively less often than, an iV-tuple of the transformed string as does a second one of those binary numbers. For example, in some embodiments of the present invention it is required that 11 occur in the transformed string at most as often as, or alternatively less often than, 00.
  • the memory is operative to selectively program each of its cells to represent each binary number from 0 through 2 ⁇ -1 as a respective one of 2 states of the cell.
  • the selected substitution transformation is such that those binary numbers occur as iV-tuples of the transformed string with respective frequencies that are in a predetermined order, as in Figure 6 below.
  • the memory is operative to selectively program each of its cells to represent each binary number from 0 through 2 ⁇ -1 as a respective one of 2 N states of the cell.
  • the selected substitution transformation is such that a designated one of those binary numbers occur as iV-tuples of the transformed string with at most a predetermined frequency.
  • a key such as a single JV-tuple of bits, or alternatively an ordered list of iV-tuples of bits for effecting a substitution transformation, is stored in the memory in association with the M or more cells.
  • the selected substitution transformation is effected by arithmetically combining (e.g., adding, multiplying, inverting and adding, or inverting and multiplying) the key with each iV-tuple of the input string.
  • error correction encoding is applied to the key before storing the key in the memory, as in Figure 3 below.
  • the key is a key string of K iV-tuples.
  • the programming of the memory cells to represent the transformed string and the storing of the key in the memory are combined into the step of concatenating the transformed string and the key string to provide a concatenated string and the step of programming
  • M+K memory cells to represent the concatenated string, as in Figure 5 below.
  • error correction encoding is applied to the concatenated string before the M+K cells are programmed to represent the concatenated string.
  • the key is stored in a reliable partition of the memory.
  • the method also includes reading the M or more cells, thereby providing a read string of M TV-tuples, and applying an inverse of the selected substitution transformation to the read string, thereby providing an output string of M TV-tuples. If the invention has worked correctly, which is almost invariably the case, the output string is identical to the input string.
  • the memory is operative to selectively program each of its cells to represent each binary number from 0 through 2 N - ⁇ as a respective one of 2 states of the cell.
  • the selecting is of a substitution transformation that results in the programming, of the M or more memory cells to represent the transformed string, yielding a distribution of respective states of the M or more cells that satisfies a predetermined logical condition.
  • Examples of such logical conditions include the lowest state occurring least often in the distribution (in the case of the states being ordered from lowest to highest), a first state occurring at most as often in the distribution as a second state, a first state occurring in the distribution less often than a second state, a predetermined ordering of respective frequencies of all the states, and a designated one of the states occurring in the distribution with at most a predetermined frequency.
  • Another basic method of the present invention also is a method of storing an input string of MTV-tuples of bits. As in the first basic method, TV is an integer greater than 1.
  • a memory is provided that is operative to selectively program each of at least M of its cells to a respective one of 2 states of the cell. In accordance with the input string, a mapping is selected that maps each binary number from 0 through 2 -1 into a respective one of the states.
  • the M cells are programmed to represent the input string in accordance with the selected mapping.
  • the mapping is selected in accordance with a statistical property of the input string.
  • Examples of mapping in accordance with a statistical property of the input string include the binary number that occurs least often as an JV-tuple of the input string being mapped into the lowest state (in case the states are ordered from lowest to highest), first and second binary numbers being mapped into respective states with the first binary number occurring as an iV-tuple of the input string at most as often as the second binary number, first and second binary numbers being mapped into respective states with the first binary number occurring as an iV-tuple of the input string less often than the second binary number, each binary number being mapped into its respective state in accordance with a frequency with which that binary number occurs as a iV-tuple of the input string, and a designated one of the binary numbers being mapped into its respective state in accordance with that binary number occurring as an iV-tuple of the input string with at most a predetermined frequency.
  • a key of the selected mapping such as a single JV-tuple of bits or a list of the binary numbers from 0 through 2 ⁇ -1 ordered according to the map, is stored in the memory in association with the M bits.
  • the key is stored in the memory in accordance with a default mapping.
  • the key is stored in a reliable partition of the memory.
  • error correction encoding is applied to the key before the key is stored in the memory.
  • the method also includes the step of reading the M cells in accordance with the selected mapping, thereby providing an output string of M N- tuples.
  • the selected mapping is such that the programming of the M cells to represent the input string yields a distribution of respective states of the M cells that satisfies a predetermined logical condition.
  • Examples of such logical conditions include the lowest state occurring least often in the distribution (in the case of the states being ordered from lowest to highest), a first state occurring at most as often in the distribution as a second state, a first state occurring in the distribution less often than a second state, a predetermined ordering of respective frequencies of all the states, and a designated one of the states occurring in the distribution with at most a predetermined frequency.
  • a memory of the present invention includes at least M nonvolatile memory cells and circuitry for storing an input string of M iV-tuples of bits in the nonvolatile memory cells, with N being an integer greater than 1, using one of the methods of the present invention.
  • the circuitry is operative to selectively program each cell to represent each binary number from 0 through 2 N - ⁇ as a respective one of 2 N (most preferably ordered) states of the cell.
  • the memory also includes circuitry for reading the string as stored, using a corresponding preferred method of the present invention.
  • a memory device of the present invention includes a memory that has at least M nonvolatile memory cells, and a controller for storing an input string of MiV-tuples of bits in the memory, with N being an integer greater than 1, using one of the methods of the present invention.
  • a memory device that uses one of the second methods of the present invention also includes circuitry for selectively programming each memory cell to represent each binary number from 0 through 2 -1 as a respective one of 2 N (preferably ordered) states of the cell.
  • Memory devices that use some of the first methods of the present invention similarly are operative to selectively program their cells to represent the binary numbers from 0 through 2 N - ⁇ as respective ones of 2 N (most preferably ordered) states of the cells.
  • the controller of a memory device that uses one of the first methods of the present invention also is operative to instruct the memory to read the stored string and to apply an inverse of the selected substitution transformation to the string as read in order to provide an output string of M iV-tuples.
  • a memory device that uses one of the second methods of the present invention also includes circutry for reading the memory cells, and the device's controller is operative to instruct the reading circuitry to read the cells, wherein the input string is stored, in accordance with the selected mapping in order to provide an output string of M N- tuples.
  • a system of the present invention includes a first nonvolatile memory with at least M nonvolatile memory cells and a host of the first nonvolatile memory.
  • the host includes a host memory, such as a RAM or a hard disk, for storing an input string of M iV-tuples, where N is an integer greater than 1.
  • the host also includes a second nonvolatile memory, such as a hard disk, for storing a driver for the first nonvolatile memory, and a processor for executing the driver code.
  • the driver code includes code for implementing one of the first methods of the present invention. Hence, in executing the driver code, the host emulates the controller of the memory device of the present invention.
  • the host preferably is operative to selectively program the cells of the first nonvolatile memory to represent the binary numbers from 0 through 2 ⁇ -1 as respective ones of 2 N (most preferably ordered) states of the cells.
  • the scope of the present invention also includes a computer-readable storage medium having embedded thereon such driver code.
  • FIG. IA illustrates the threshold voltage distributions of flash cells programmed in 1-bit mode
  • FIG. IB illustrates the threshold voltage distributions of flash cells programmed in 2-bit mode
  • FIG. 2 is a block diagram of a flash memory device
  • FIG. 3 illustrates an embodiment of the present invention in which a transformation rule is selected and applied subsequent to ECC encoding
  • FIG. 4 illustrates an embodiment of the present invention in which a default mapping from bits to states is replaced with a substitute mapping
  • FIG. 5 illustrates an embodiment of the present invention in which a transformation rule is selected and applied prior to ECC encoding
  • FIG. 6 is an exemplary histogram of a good states distribution
  • FIG. 7 is a high-level block diagram of a system of the present invention.
  • the present invention reduces the effect of error sources such as PD that depend on the user data stored in a multi bit per cell flash memory device by manipulating the user data and controlling the actual sequence of states that is programmed into the flash memory.
  • a desired distribution states that is optimal in the sense of minimizing the expected number of cell errors, is induced over the flash memory cells.
  • the expected number of cell errors is minimized by minimizing the number of cells that are programmed to the erase state and/or to high states. This is done in the following way: The distribution of the states that should be programmed into the flash memory is examined as a function of the bit sequence that is to be stored in the flash memory.
  • bit sequence is altered according to a transformation rule that is invertible and that can be concisely described, such that the new distribution of states based on the altered bit sequence is closer, and preferably as close as possible, to the optimal desired distribution.
  • the altered bit sequence is stored into the flash memory.
  • the transformation rule also is stored in the flash memory in order to allow recovery of the original bit sequence upon reading. Note that it is also possible to embed the transformation rule inside the altered bit sequence. When the flash memory is read, the stored bit sequence and the transformation rule are recovered. The transformation rule is then used in order to obtain the original bit sequence by performing an inverse transformation.
  • transformation rule that is stored in the flash memory be well protected, such that the transformation rule can be recovered without errors with very high probability. This can be done in several ways.
  • a transformation rule is chosen based on the ECC- encoded user data bits, such that applying the transformation to the bit sequence results in an altered bit sequence that when programmed to the flash memory induces a states distribution that is closer, and preferably as close as possible, to the desired states distribution.
  • the encoded user data are altered based on the transformation rule and then are programmed into the flash memory.
  • the transformation rule is separately protected by an ECC and then is programmed into the flash memory . Upon reading the flash memory, the transformation rule is recovered by an ECC decoder.
  • the transformation rule then is used in order to recover the stored encoded user data bits together with bit errors introduced in the course of storing the encoded user data in the flash memory (referred to as "noisy" encoded user data bits).
  • the user data bits are then recovered by ECC decoding of the noisy encoded user data bits. Note that it might be the case that an ECC is not required for protecting the transformation rule and/or the user data bits. For example if a small reliable partition requiring no ECC protection (such as an SBC flash partition) is allocated in the flash memory, then a transformation rule that can be concisely described using a small number of bits can be stored in the small reliable partition without ECC protection. Because ECC encoding and decoding is optional, the ECC encoder and decoder blocks for the transformation rule in Figure 3 have dashed borders rather than solid borders.
  • an optimal mapping from bits to states is computed, such that the states distribution induced by the ECC encoded user data bits is closer, and preferably as close as possible, to the desired states distribution.
  • the mapping information is protected by an ECC and then is programmed to the flash memory according to a default mapping from bits to states.
  • the encoded user data bits are stored into the flash memory according to the new mapping.
  • the mapping information is recovered by an ECC decoder.
  • the mapping information is used in order to read the stored encoded user data bits together with bit errors introduced by the flash (referred to as "noisy" encoded user data bits).
  • the user data bits then are recovered by ECC decoding of the noisy encoded user data bits.
  • an ECC is not required for protecting the transformation rule and/or the user data bits.
  • a small reliable partition requiring no ECC protection such as an SBC flash partition
  • the mapping information that can be concisely described using a small number of bits can be stored in the small reliable partition without ECC protection.
  • ECC encoding and decoding is optional, the ECC encoder and decoder blocks for the mapping information in Figure 3 have dashed borders rather than solid borders.
  • mapping information is stored in the flash memory.
  • a "key" of the mapping is referred to in the appended claims as a "key" of the mapping.
  • a transformation rule is chosen based on the user data bits.
  • the user data bits are altered based on the transformation rule.
  • the transformation rule that can be concisely described using a small number of bits, is concatenated to the altered user data bits sequence.
  • the resulting bit sequence is encoded using an ECC encoder. If the ECC encoder is systematic, it computes a set of parity bits that is concatenated to the bit sequence to produce a codeword. If the ECC encoder is not systematic, it produces a codeword in which the input bit sequence is not separately recognizable. The codeword is programmed to the flash memory.
  • the transformation rule is chosen in such a way that the induced states distribution of the encoded bit sequence is closer, and preferably as close as possible, to the desired states distribution.
  • the read bit sequence is decoded by an ECC decoder, recovering both the transformation rule and the altered user data bits.
  • the transformation rule then is used for recovering the user data bits from the altered user data bits.
  • the flash memory is a two-bit-per-cell MBC flash memory and that each cell can be programmed into L-A states or voltage levels.
  • the first example is based on the embodiment shown in Figure 5.
  • the transformation rule is two bits long and so is stored in one cell.
  • a good states distribution over the cells of the page as a distribution in which the fraction of cells in the page that are programmed to the erase state (state 0 mapped by 11) is smaller than 0.36.
  • the present invention ensures that every programmed bit sequence induces a good states distribution, regardless of the user data that are stored in the flash memory, by implementing the following steps:
  • the transformation rule is defined as summation modulo 2 of the user data bits with the inverse of the chosen state.
  • the decoder Upon reading the flash memory, decode the read bit sequence, hi this example the decoder decodes the read 28 bit sequence and outputs the stored 26 bits sequence [1 0, 1 0, 1 0, 1 O 5 1 0, 0 0, 0 I 3 0 0, 1 1, 0 I 5 0 O 3 0 0, 0 I].
  • a good states distribution as a distribution in which the erase state is as most as frequent as state 3, in which state 3 is at most as frequent as state 1, and in which state 1 is at most as frequent as state 2.
  • the histogram of such a states distribution would look like the histogram shown in Figure 6. It is possible to induce such good state distributions by changing the mapping from bits to states during flash programming, based on the embodiment shown in Figure 4.
  • this example we assume that there is a fixed mapping from bits to states used by the flash device that cannot be changed.
  • this example is based on the embodiment shown in Figure 3.
  • the transformation rule information can be stored in a reliable partition of the flash and requires no ECC protection.
  • the present invention implements the following steps:
  • the transformation rule basically represents an alternative mapping from bits to states.
  • Z*log 2 (Z>) bits in order to store the transformation rule.
  • log 2 (Z!) ⁇ Z*log 2 (i) bits are sufficient for representing any mapping but then the mapping representation is "compressed" and less convenient to handle. In any case, when the number of cells in the page is large, the overhead of storing the transformation rule is negligible.
  • this method also does not depend on the actual user data and therefore has the disadvantage that even though this method provides a high probability of a "good” distribution, there are user data patterns that when stored into the flash memory cause many cells to be programmed to the erase state, resulting in many PD errors.
  • the present invention can ensure a "good" distribution of states over the flash cells for any user data pattern stored in the flash memory. For example, the present invention can ensure that for any user data pattern the fraction of cells that are programmed into the erase state is smaller than some threshold. Hence, under the present invention there are no problematic user data patterns that exhibit higher error rates than other user data patterns when stored in the flash memory.
  • Gonzalez et al. in US Patent No. 6,684,289, also teach mapping between logical bit values and physical bit values when writing and reading a flash memory, for the purpose of avoiding repeated programming of static patterns of data (see column 6 lines 28-47). Not only do Gonzalez et al. '289 have nothing to do with minimizing the probability of data dependent errors such as PD errors of the stored bits, but Gonzalez et al. '289 also apply a time- varying transformation such that the same logical data value is transformed to different physical states at different times, as otherwise the goal of avoiding repeated programming of static data patterns is not achieved.
  • the present invention has no requirement that the transformation be time-dependent.
  • the present invention applies a transformation that is a function of the user data but that need not have changed over time when the same data are stored again.
  • flash memory devices in which this is not the case. In such devices the erased state is different from all data states. Specifically, the erased state has a more negative threshold voltage than any of the data states.
  • the methods of the present invention can be implemented either by software or by hardware. More specifically, the transformation of the bits (during writing, reading or both) can be implemented by executing software code or by electrical circuitry (such as inverter gates). If the transformation is implemented by software, it may be implemented either by software executed on the host computer that writes or reads the data (for example, within the software device driver supporting the storage device), or it may be implemented by firmware executed within the memory controller (e.g., controller 20 of Figure 2) that interacts with the host computer and controls the memory media. If the transformation is implemented by hardware, it may be implemented either in the memory controller or within the memory media (e.g. in data input/output circuit 6 of Figure 2). This applies whether the memory controller and the memory media are two separate dies or reside on a common die. AU the above configurations and variations are within the scope of the present invention.
  • Figure 2 also illustrates two kinds of embodiments of a flash memory device of the present invention in which the methods of the present invention are implemented by the circuitry of circuit chip(s) 22.
  • the circuitry could perform ECC encoding and decoding. In practice, this usually is prohibitively expensive. Therefore, part of memory cell array 1 is reserved for programming in SBC mode, for storing the key of the transformation (method of Figure 3) or of the mapping (method of Figure 4).
  • command circuits 7 upon receiving an input string to store in memory cell array 1, command circuits 7 select the substitution transformation to apply to the input string and then apply the selected transformation to the input string prior to transferring the input string and the transformation key to state machine 8 for programming into memory cell array 1 as described above and as illustrated in Figure 3.
  • command circuits 7 receive an instruction from controller 20 to read the string, command circuits 7 read both the string and the transformation key and apply the inverse transformation to the string before sending the string to controller 20.
  • command circuits 7 upon receiving an input string to store in memory cell array 1, command circuits 7 select, in accordance with the input string, a map of the binary integers in the interval [O 3 2 ⁇ -1] to the 2 M states to which column control circuit 2 and row control circuit 3 program the cells of memory cell array 1 other than the cells of the SBC partition. State machine 8 then directs column control circuit 2 and row control circuit 3 to program the input string into memory cell array 1 in accordance with the selected map and to program a key of the map into the SBC partition of memory cell array 1, as described above and as illustrated in Figure 4.
  • command circuits 7 receive an instruction from controller 20 to read the string
  • command circuits 7 read the map key from the SBC partition of memory cell array 1 and instruct state machine 8 to direct column control circuit 2 and row control circuit 3 to read the string in accordance with the map.
  • Figure 2 illustrates corresponding embodiments of a flash memory device of the present invention in which the methods of the present invention, as illustrated in Figures 3-5, are implemented by controller 20, either in dedicated hardware, or by executing flash controller software, or by a combination of the two.
  • command circuits 7 are provided with a default map of the binary integers in the interval [0, 2 ⁇ -1] to the 2 N states to which column control circuit 2 and row control circuit 3 program the cells of memory cell array 1 (other than cells of a SBC partition in embodiments in which memory cell array 1 has such a partition).
  • the default map maps binary 2 N - ⁇ (a string of N l's) to the lowest programmed state of the cells.
  • Command circuits 7 also are operative to temporarily replace the default map with a replacement map as commanded by controller 20 in support of the method of Figure 4.
  • Figure 7 is a high-level block diagram of a system 30 of the present invention.
  • System 30 includes a processor 32 and four memory devices: a RAM 34, a boot ROM 36, a mass storage device (hard disk) 38 and one or more circuit chips 22 of Figure 2 as a flash memory device 42, all communicating via a common bus 44.
  • Flash memory driver code 40 is stored in mass storage device 38 and is executed by processor 32 to interface between user applications executed by processor 32 and flash memory device 42, and to manage the flash memory of flash memory device 42.
  • driver code 40 emulates the functionality of controller 20 of Figure 2 with respect to implementing the methods of the present invention.
  • Driver code 40 typically is included in operating system code for system 30 but also could be freestanding code.
  • Mass storage device 38 is an example of a computer-readable storage medium bearing computer-readable driver code for implementing the present invention.
  • Other examples of such computer-readable storage media include read-only memories such as CDs bearing such code.

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Abstract

Un circuit de mémoire, ou une unité de commande de dispositif de mémoire, ou un hôte d'un dispositif de mémoire, stocke une chaîne d'entrée de M N-uplets de bits en sélectionnant une transformation de substitution conformément à la chaîne d'entrée et en appliquant la transformation à la chaîne d'entrée pour fournir une chaîne transformée de M N-uplets de bits. M cellules de mémoire ou plus sont programmées pour représenter la chaîne transformée et de préférence pour également représenter une clé de la transformation. Sinon, le circuit programme de façon sélective chacune des M cellules ou plus dans un état respectif des 2N états. Le circuit ou l'unité de commande sélectionne un mappage qui mappe les nombres binaires dans [0,2N-1] en des états respectifs conformément à la chaîne d'entrée et le circuit utilise le mappage pour programmer M cellules afin de représenter la chaîne d'entrée. De préférence, une clé du mappage est stockée dans la mémoire en association aux M cellules.
PCT/IL2007/001567 2006-12-31 2007-12-19 Eviter des erreurs dans une mémoire flash en utilisant des transformations de substitution WO2008081426A1 (fr)

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KR101518033B1 (ko) 2008-11-18 2015-05-06 삼성전자주식회사 멀티-레벨 비휘발성 메모리 장치, 상기 장치를 포함하는 메모리 시스템 및 그 동작 방법

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US7984360B2 (en) 2011-07-19
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