WO2008044746A1 - Récepteur - Google Patents

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Publication number
WO2008044746A1
WO2008044746A1 PCT/JP2007/069894 JP2007069894W WO2008044746A1 WO 2008044746 A1 WO2008044746 A1 WO 2008044746A1 JP 2007069894 W JP2007069894 W JP 2007069894W WO 2008044746 A1 WO2008044746 A1 WO 2008044746A1
Authority
WO
WIPO (PCT)
Prior art keywords
frequency
signal
circuit
digital
converter
Prior art date
Application number
PCT/JP2007/069894
Other languages
English (en)
Japanese (ja)
Inventor
Takeshi Ikeda
Hiroshi Miyagi
Original Assignee
Nsc Co., Ltd.
Ricoh Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nsc Co., Ltd., Ricoh Co., Ltd. filed Critical Nsc Co., Ltd.
Publication of WO2008044746A1 publication Critical patent/WO2008044746A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/26—Circuits for superheterodyne receivers
    • H04B1/28—Circuits for superheterodyne receivers the receiver comprising at least one semiconductor device having three or more electrodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
    • H04B1/0007—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage
    • H04B1/001—Channel filtering, i.e. selecting a frequency channel within the SDR system
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
    • H04B1/0007—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage
    • H04B1/0014—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage using DSP [Digital Signal Processor] quadrature modulation and demodulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
    • H04B1/0007—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage
    • H04B1/0025—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage using a sampling rate lower than twice the highest frequency component of the sampled signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
    • H04B1/0028—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at baseband stage
    • H04B1/0032—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at baseband stage with analogue quadrature frequency conversion to and from the baseband

Definitions

  • the present invention relates to a receiver configured to convert a high-frequency signal received via an antenna into an intermediate-frequency signal and process the signal, for example,
  • a high-frequency signal received by a receiving antenna and a local oscillation signal output from a local oscillator are frequency-mixed by a mixer. Convert high frequency signals to intermediate frequency signals.
  • the receiver of the super hetero dialog down method setting the local oscillation frequency to a frequency shifted by an intermediate frequency ⁇ ⁇ ⁇ ⁇ against Canon Li ⁇ frequency f RF to be received.
  • the frequency conversion is performed.
  • An IF filter is placed on the output side of the mixer, and only the signal of the intermediate frequency f IF is passed through the subsequent circuits. After that, the signal of the intermediate frequency f IF is detected by the detection circuit, and is processed as a baseband signal through predetermined processing. In some cases, the baseband signal is amplified by a low-frequency amplifier circuit. In this way, the superheterodyne method demodulates the intermediate frequency signal into a baseband signal.
  • Some receivers employ a direct conversion method (also called direct conversion method or zero-IF method) that converts the frequency directly from the high-frequency signal of the received radio wave to the base-band signal.
  • a direct conversion method also called direct conversion method or zero-IF method
  • the direct conversion type receiver amplifies a high-frequency signal received by an antenna as it is by a high-frequency amplifier circuit, and directly detects a baseband signal from the signal by a detection circuit.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2 00 4-4 9 6 4 0
  • the direct conversion method eliminates the IF (intermediate frequency) stage of the receiver circuit compared to the superheterodyne method, so the number of receiver parts can be greatly reduced and the mounting area can be reduced. In this way, the direct-comparison receiver has a simpler structure than the superheterodyne receiver.
  • the superheterodyne method has little interference and can detect and output without being affected by the input signal level.
  • the configuration is more complicated, but it is most commonly used because of its superior total performance.
  • DSP Digital Signal Processor
  • the processing for the intermediate frequency signal output from the mixer is performed by the DSP.
  • a conventional IF filter composed of a SAW filter (surface acoustic wave filter) and composed of a DSP is used to make the IF filter different from other circuits. Disclosure of the invention in which both can be integrated on one IC chip
  • the intermediate frequency is 1 OMHz or higher, and the intermediate frequency signal at the mixer output has a relatively high frequency. Therefore, in order to convert this into a digital signal using an A / D converter, high-speed sampling is required based on the Nyquist theorem. As a result, there was a problem that the power consumption of the AZ D converter would increase. In addition, DSP that processes digital signals also requires a high sampling frequency as an operation clock, resulting in increased power consumption. Another problem is that AZ converters and DSPs that operate at high sampling frequencies have a complicated circuit configuration, which increases the circuit scale.
  • the present invention has been made to solve such problems.
  • an intermediate frequency conversion receiver realized by using a digital circuit such as a DSP
  • an AZD converter or DSP is highly sampled.
  • the purpose is to reduce power consumption and circuit scale so that it does not have to operate at a frequency.
  • a high-frequency analog signal received via an antenna is converted into a low-frequency analog signal and AZD converted, and the generated digital signal is digitally converted. After signal processing, the signal is converted back to an analog signal and frequency-converted to the desired intermediate frequency signal.
  • a low-frequency analog signal may be A / D converted by the AZD converter, so that high-speed sampling is unnecessary based on the Nyquist theorem.
  • the power consumption of the A / D converter is reduced Can be reduced.
  • a digital circuit that processes a digital signal output from the A / D converter does not require a high sampling frequency as an operation clock, and the power consumption of the digital circuit can be reduced.
  • the configuration of the AZD converter and digital circuit can be simplified, and the circuit scale can be reduced.
  • FIG. 1 is a diagram illustrating a configuration example of a receiver according to the present embodiment.
  • FIG. 2 is a diagram showing an example of frequency bands of the intermediate frequency signal and the low frequency signal used in the present embodiment.
  • FIG. 1 is a diagram illustrating a configuration example of a receiver according to the present embodiment.
  • the receiver according to this embodiment includes an antenna 1, a bandpass filter 2, an LNA (Low Noise Amplifier) 3, a first frequency conversion circuit 4, and a first local oscillation circuit 5.
  • 1st PLL (Phase Locked Loop) circuit 6 crystal 7, A / D converter 8, DSP 9, 1st DA converter 10, 2nd D ⁇ A converter 1 1, 2nd Frequency conversion circuit 1 2, second local oscillation circuit 13 3, and second PLL circuit 14.
  • the second frequency conversion circuit 1 2 is an IQ mixer. As shown in FIG. 1, the I signal mixer 1 2 a, the Q signal mixer 1 2 b, the adder 1 2 c, and the 90 ° phase shifter 1 2 d.
  • the configuration shown in Fig. 1 excluding antenna 1 is integrated on a single semiconductor chip by, for example, the CMO S (Complementary Metal Oxide Semiconductor) process or Bi-CMO S (Bipolar-CMOS) process.
  • Bandpass filter 2 selectively outputs a broadcast wave signal in a specific frequency band of the broadcast wave signal received by antenna 1.
  • L NA 3 amplifies the high-frequency analog signal that has passed through the pan-pass filter 2 with low noise.
  • the first frequency conversion circuit 4 frequency-mixes the high-frequency analog signal output from the LNA 3 and the local oscillation signal output from the first local oscillation circuit 5 to thereby generate a high-frequency analog signal. a frequency conversion to a low frequency analog signal of the intermediate frequency f IP I also low frequency Ri of interest.
  • the target intermediate frequency fIF is, for example, 45 MHz, and the frequency bandwidth of the intermediate frequency signal is 6 MHz.
  • the first frequency conversion circuit 4 is a high-frequency analog signal that has a frequency lower than 45 MHz, preferably close to the baseband, and a frequency that can secure a frequency bandwidth of 6 MHz. Frequency conversion.
  • the center frequency f LF of the low-frequency analog signal is 4 MHz as shown in Fig. 2 (b).
  • the first local oscillation circuit 5 is based on a clock signal generated by the first PLL circuit 6 based on a reference signal having a predetermined frequency output from the crystal oscillator 7.
  • the local oscillation signal of the frequency necessary to generate the low frequency analog signal of 4 MHz is generated. Then, this local oscillation signal is supplied to the first frequency conversion circuit 4.
  • the A / D converter 8 performs analog-to-digital conversion on the low-frequency analog signal output from the first frequency conversion circuit 4.
  • the low-frequency signal thus converted into a digital signal is input to the DSP 9.
  • the DSP 9 limits the bandwidth by digitally filtering the digital signal supplied from the AZD converter 8.
  • a low frequency signal having a narrow frequency band of 6 MHz with 4 MHz as the center frequency f LP is extracted.
  • a deep out-of-band attenuation 80 to 90 dB
  • the passband can be obtained digitally accurately, and the occurrence of a notch can be prevented. That is, a filter having a preferable frequency characteristic can be realized, and a good low-frequency signal having a desired frequency bandwidth can be extracted.
  • the DSP 9 also has (sin co LF t) sin table information (cos ⁇ LF t) cos table information based on the low frequency f LF of 4 MHz.
  • the low-frequency signal extracted as described above is divided into an in-phase signal (I signal) and a quadrature signal (Q signal) with a phase orthogonal to it.
  • the first DZA converter 10 converts the digital I signal output from the DSP 9 into a digital analog signal.
  • the second DZA converter 11 converts the digital Q signal output from the DSP 9 into a digital-to-analog converter.
  • the second frequency conversion circuit 12 converts the low-frequency f LF analog signal output from the first and second DZA converters 1 0 '1 1 into an intermediate frequency f IF signal. .
  • the second frequency conversion circuit 12 uses the I signal and the Q signal converted into analog signals by the first and second DZA converters 10 and 1 1. Perform quadrature modulation. That is, in the second frequency conversion circuit 12, the I signal mixer 12 2 a converts the frequency of the I signal supplied from the first DZA converter 10 with the in-phase local oscillation signal. The Q signal mixer 1 2 b converts the frequency of the Q signal supplied from the second DZA converter 1 1 with an orthogonal local oscillation signal. The adder 1 2 c synthesizes the I signal and Q signal, which are quadrature modulated by the mixers 1 2 a and 1 2 b, and outputs the result as a target intermediate frequency signal.
  • the frequency f IF of the local oscillation signal used in each mixer 1 2 a and 1 2 b is an intermediate frequency in the television frequency band of 45 MHz.
  • the second local oscillation circuit 13 uses the clock signal generated by the second PLL circuit 14 based on the reference signal of a predetermined frequency output from the crystal oscillator 7 as a clock signal. Based on this, generate a local oscillator signal of 45 MHz.
  • the 90 ° phase shifter 12 2 d rotates the phase of the local oscillation signal generated by the second local oscillation circuit 13 90 °.
  • the in-phase local oscillation signal output from the second local oscillation circuit 1 3 is supplied to the I signal mixer 12 2 a, and the quadrature local oscillation output from the 90 ° phase shifter 1 2 d Supply the signal to the Q signal mixer 1 2 b.
  • the high-frequency analog signal received via the antenna 1 is converted into a low-frequency analog signal by the first frequency conversion circuit 4 and AZD-converted.
  • digital signal processing is performed on the digital signal generated by DSP 9, it is converted back to an analog signal and converted to a signal of the desired intermediate frequency by the second frequency conversion circuit 12 I try to do it.
  • the AZD converter 8 only needs to perform AD conversion on the low frequency analog signal of 4 MHz, so that high-speed sampling is not required. For example, even if an AZD conversion operation with four times oversampling is performed, the sampling frequency of the AZD converter 8 is only 16 MHz. Even if the frequency f LF of the low-frequency analog signal is 7 MHz, the sampling frequency required for the AZD converter 8 is 28 MHz. Therefore, the power consumption of the AD converter 8 can be reduced.
  • the DSP 9 that processes the digital signal generated by the AZD converter 8 does not require a high sampling frequency as an operation clock, and the power consumption of the DSP 9 can be reduced.
  • the configuration of the AZD converter 8 and DSP 9 can be simplified, and the circuit scale can be reduced. this As a result, the semiconductor chip can be reduced in size.
  • the second frequency conversion circuit 12 is configured by IQ and K but this is merely an example, and the present invention is not limited to this.
  • the IQ mixer is preferred because it can effectively remove image components and carrier components.
  • This IQ mixer is used as a digital signal processing in DSP 9. It can also be realized.
  • the frequency f LF of the low-frequency analog signal is set to 4 M H
  • the receiver is a television tuner.
  • a radio tuner As described above, it may be a radio tuner.
  • the present invention is useful for a superheterodyne receiver realized by using a digital circuit such as DS.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Superheterodyne Receivers (AREA)

Abstract

La présente invention concerne un signal analogique haute fréquence reçu via une antenne (1) qui est converti en un signal analogique basse fréquence par un premier circuit de conversion de fréquence (4), puis soumis à la conversion A/N. Le signal numérique généré par ceci est soumis au traitement du signal numérique par un DSP (9). Le signal revient ensuite à un signal analogique et il est soumis à une conversion de fréquence (12) de manière à le convertir en un signal d'une fréquence intermédiaire cible. Un convertisseur A/N (8) doit uniquement réaliser la conversion A/N du signal analogique ayant une fréquence inférieure à la fréquence intermédiaire, évitant ainsi la nécessité de l'échantillonnage haut débit conformément au théorème de Nyquist. Comme pour le DSP (9), il n'est pas nécessaire de réaliser une opération avec une forte fréquence d'échantillonnage.
PCT/JP2007/069894 2006-10-04 2007-10-04 Récepteur WO2008044746A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006273387A JP2008092476A (ja) 2006-10-04 2006-10-04 受信機
JP2006-273387 2006-10-04

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WO2008044746A1 true WO2008044746A1 (fr) 2008-04-17

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JP (1) JP2008092476A (fr)
CN (1) CN101611557A (fr)
TW (1) TW200818730A (fr)
WO (1) WO2008044746A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI415399B (zh) * 2009-04-07 2013-11-11 Mstar Semiconductor Inc A circuit that eliminates interference
US9673842B2 (en) 2012-04-25 2017-06-06 Qualcomm Incorporated Combining multiple desired signals into a single baseband signal
JP6200367B2 (ja) * 2014-03-31 2017-09-20 ミハル通信株式会社 信号処理装置、ｃａｔｖヘッドエンド、およびｃａｔｖシステム

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6454944A (en) * 1987-08-26 1989-03-02 Kenwood Corp Ssb signal receiver
JPH10135861A (ja) * 1996-10-31 1998-05-22 Toyo Commun Equip Co Ltd 無線受信装置
JP2002521904A (ja) * 1998-07-24 2002-07-16 グローバル・コミュニケーション・テクノロジー・インク 単一チップｃｍｏｓ送信器／受信器およびｖｃｏ−ミキサ構造

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6454944A (en) * 1987-08-26 1989-03-02 Kenwood Corp Ssb signal receiver
JPH10135861A (ja) * 1996-10-31 1998-05-22 Toyo Commun Equip Co Ltd 無線受信装置
JP2002521904A (ja) * 1998-07-24 2002-07-16 グローバル・コミュニケーション・テクノロジー・インク 単一チップｃｍｏｓ送信器／受信器およびｖｃｏ−ミキサ構造

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JP2008092476A (ja) 2008-04-17
CN101611557A (zh) 2009-12-23
TW200818730A (en) 2008-04-16

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