WO2008041216A1

WO2008041216A1 - A sigma-delta modulator

Info

Publication number: WO2008041216A1
Application number: PCT/IE2007/000092
Authority: WO
Inventors: Michael Peter Kennedy; Kaveh Hosseini
Original assignee: University College Cork - National University Of Ireland, Cork;
Priority date: 2006-10-04
Filing date: 2007-10-04
Publication date: 2008-04-10
Also published as: IE20070709A1

Abstract

A digital to digital Sigma-Delta modulator (100) of order L comprises a signal input (10, 110, 210) to receive a digital input value encoded over a given number no of bits, where no is an integer; and an output (20, 120, 220) for delivering a digital output value encoded over a given number m of bits, where m is an integer less than no. There is at least one Sigma-Delta cell comprising an adder (A1, A11, A21) for receiving an input signal and feedback, and a quantizer (Q1, Q11, Q21) with interval M. The cell further comprises a gain component (DG1, G22) for monitoring the quantizer and for adding a number w to the state of the cell. The number w is added according to the output of the quantizer in order to offset the cell state so that the cell sequence length (M-w) L becomes a power of a prime number. Preferably, the quantizer (Q1, Qi 1, Q21) interval M satisfies M = 2 No. The effect of the auxiliary feedback is to spread the energy over a large number of tones, independently of the input and initial conditions, as illustrated in Fig. 4 (b).

Description

"A Sigma-Delta Modulator"

INTRODUCTION

Field of the Invention

The present invention relates to digital to digital Sigma-Delta (Σ-Δ) modulators. It is applicable to digital frequency synthesizers or DMS (Digitally Modulated Synthesizer) circuits. Such circuits are especially used in the radio frequency transceivers of mobile terminals or of stationary stations of a radio communications system.

Prior Art Discussion

A digital to digital Σ-Δ modulator is a device for encoding a digital signal using a small number of steps, and a sampling frequency which is high compared to the passband of the signal to be encoded. This device shapes the spectrum of the quantization noise by pushing its power back into a frequency band not occupied by the spectrum of the useful signal. This spectral separation makes it possible, by filtering the encoded signal, to retain a signal-to-noise ratio complying with given specifications.

A typical known digital to digital Sigma-Delta modulator comprises:

• an input in order to receive a digital input value encoded over a given number no of bits, where no is a specified integer;

• an output in order to deliver a digital output value encoded over a given number m of bits, where m is a specified integer less than no; and

• one or more Sigma-Delta cells placed between the input and the output of the modulator.

Each cell may be of the first order or of a higher order. When the modulator comprises several cells, the latter may be arranged according to a structure known to the one skilled in the art by the name of "MASH structure". In this case, the cells are often identical to each other, but this is not mandatory. In particular, some may be of the first order, and others of a higher order.

A conventional Sigma-Delta cell of the output feedback type comprises, at a minimum, the following elements:

• A feedforward filter comprising an input coupled to the output of the subtracter, and an output;

• A feedback filter comprising an input coupled to the output of the quantizer, and an output coupled to the second input of the subtractor;

• A quantizer having an input coupled to the output of the feedforward filter and an output coupled to the feedback filter. Furthermore, the output of the quantizer is coupled to the output of the modulator in order to deliver the digital output value or a contribution thereto. The quantizer has a specified quantization interval.

An alternative realization of a Sigma-Delta cell, known as an "error feedback modulator", comprises the following elements:

• An adder, comprising a first input, a second input, and an output, the first input being coupled to the input of the modulator in order to receive the digital input value or a value derived therefrom;

• A subtractor comprising a first input coupled to the output of the adder, a second input, and an output coupled via a delay or filter block to the second input of the adder; • A quantizer having an input coupled to the output of the adder and an output coupled, via a gain block with gain M, to the second input of the subtractor. Furthermore, the output of the quantizer is coupled to the output of the modulator in order to deliver the digital output value or a contribution thereto. The quantizer has a specified quantization interval. In practice, the input of the modulator receives successive values of a digital input signal, occupying a passband much lower than the sampling frequency. The corresponding output values form an output signal, which is a digital signal.

A particularly awkward problem for implementing such a modulator resides in the unpredictable (except for exhaustive simulations which in practice are sometimes unachievable) appearance of cycles. These cycles depend on the value of the input signal, on the architecture of the Σ-Δ modulator, and on the initial conditions. They are apparent from the concentration of a considerable part of the output signal power in a small number of tones (tones with a power value which is higher than the local mean value). These situations impair the desired encoding performance by increasing the power of the encoding noise in the passband of the useful signal.

Analysis of the behaviour of a digital to digital Σ-Δ modulator comes within the study of systems called "sequential Mealy machines" and of non-linear servo-control systems. The "harmonic" analysis of a digital to digital Σ-Δ modulator makes it possible to predict its transfer function and its encoding performance by assuming that the quantizer introduces an encoding error, the spectrum of which is that of decorrelated white noise for the input signal. With this assumption, the behaviour of the Σ-Δ modulator according to the simulation is predicted, except during the appearance of cycles.

The inventors are not aware of any device having the encoding properties of a digital to digital Σ-Δ modulator without the drawbacks of the existence of cycles.

The quantization noise in a digital delta-sigma modulator (DDSM) is distributed over a number of tones that is determined by the length of the quantization noise sequence. The larger the number of tones, the lower the noise power per tone. One therefore tries to maximize the number of tones by maximizing the sequence (cycle) length.

The conventional solution uses a power-of-2 quantizer. The difficulty with this architecture is that it can produce short sequences, resulting in large quantization noise tones. Various ideas have been proposed to overcome this problem. - A -

One approach to maximizing the sequence length is described in US6822593 (Level et at). This involves the use of a prime modulus quantizer which overflows when it reaches the maximum count, which is a prime number. By using a prime modulus P, this modulator produces sequences of length P when the input is constant.

Another approach to increasing the sequence length, as described in the Pamarti et al reference below, is to add a so-called LSB dither signal to the modulator input prior to applying it to the input of the Sigma-Delta cell. While this approach increases the number of tones and therefore lowers the average power per tone, it raises the noise floor of the output spectrum. This approach is refereed to as "LSB dither", and its effects are illustrated in Figs. 8 and 10.

The invention is directed towards providing an improved Sigma Delta modulator, in which there is a greater guaranteed minimum sequence length and the quantization noise is spread over more tones. Another objective is that the modulator is simpler to implement in hardware.

References

US6822593, November 2004, Level et al.

Harris, F.;"A Modified Delta-Sigma Quantizer to Obtain High Resolution A/D Conversion with Small Excess Sample Rates"; Proceedings of the Asilomar Conference on Signals, Systems and Computers. Pacific Grove, Oct. 31 —Nov. 2, 1988; New York, IEEE; vols. 1 & 2 Conf. 22; pp. 622-625; XP000130325.

Magrath, A. J., et al.; A Sigma-Delta Modulator Topology with High Linearity: Circuits and Systems, 1997: ISCAS '97: Proceedings of 1997 IEE International Symposium on Hong Kong Jun. 9-12, 1997: New York, pp. 53-56; XP010235973. Kozak, M. and Kale, I.; "Oversampled Delta-Sigma Modulators, Analysis, Applications, And Novel Topologies", Kluwer Academic Publishers, Boston, 2003.

Borkowski, MJ. , Riley, T.A.D., Hakkinen, J., Kostamovaara, J.; "A Practical Delta Sigma Modulator Design Method Based on Periodical Behavior Analysis "IEEE Transactions on Circuits and Systems-II, Vol.52, pp. 626-630, October, 2005.

S. Pamarti, J. Welz, and I. Galton, "Statistics of the quantization noise in one-bit dithered single-quantizer digital delta-sigma modulators," IEEE Trans. Circuits Syst. I, vol. 54, no. 3, pp. 492-503, Mar. 2006.

SUMMARY OF THE INVENTION

According to the invention, there is provided a digital to digital Sigma-Delta modulator of order L comprising: a signal input to receive a digital input value encoded over a given number no of bits, where no is an integer; an output for delivering a digital output value encoded over a given number m of bits, where m is an integer less than no; and at least one Sigma-Delta cell comprising: an adder for receiving an input signal and feedback, and a quantizer with interval M; wherein the cell further comprises means for monitoring the quantizer and for adding a number w to the state of the cell, said number being added according to the output of the quantizer in order to offset the cell state so that the cell sequence length (M-w)^L becomes a power of a prime number.

In one embodiment, the monitoring means monitors the output of the quantizer.

In one embodiment, the quantizer interval M = 2"° . In one embodiment, the number w has a value according to the following table:

In one embodiment, the monitoring means is in an auxiliary feedback loop between the quantizer and the adder.

In another embodiment, the monitoring means comprises a gain component which adds the number w into the state of the cell.

In one embodiment: the adder comprises a first input, a second input, a third input, and an output, the first input being coupled to said signal input, the second input being coupled to the output of a filter block of a feedback path, the third input being coupled to the auxiliary feedback loop; the cell comprises a subtractor comprising a first input coupled to said adder output and an output coupled to the input of a filter; the quantizer has an input coupled to said adder output, and an output coupled to the output of the modulator and furthermore coupled to the auxiliary feedback loop and, via a gain block, to the second input of the subtractor; the auxiliary feedback loop comprises a gain component providing a gain of w, and its output is coupled to the third input of the adder.

In another embodiment, the cell comprises a feedforward filter having a first input coupled to said adder output, and an output coupled to the input of the quantizer. In a further embodiment, the modulator further comprises a number L-I of other Sigma-Delta cells, where L is an integer greater than or equal to 2, the L cells being arranged according to a MASH structure, and wherein a quantization interval, gain M, and added number w of each of said L cells are equal.

In another aspect, the invention provides a digital frequency synthesizer comprising any modulator as defined above.

DETAILED DESCRIPTION OF THE INVENTION

Brief Description of the Invention

The invention will be more clearly understood from the following description of some embodiments thereof, given by way of example only with reference to the accompanying drawings in which: -

Fig. 1 is a diagram of a digital to digital Σ-Δ modulator of the invention having a first-order cell;

Fig. 2 is a graph showing the properties of a quantizer having two output levels;

Fig. 3 is a diagram illustrating a digital to digital Σ-Δ modulator having three first-order cells of the type shown in Fig. 1 arranged according to a MASH structure;

Figs. 4(a) and 4(b) are graphs showing the spectrum of the output signal y of a modulator according to Fig. 3, with w=0 and w=l, respectively; M—2^Λ9 in both cases;

Fig. 5 is a diagram illustrating a digital frequency synthesizer incorporating a digital to digital Σ-Δ modulator according to the invention; Fig. 6 is a generalized diagram of a modulator of the invention having a K- level quantizer, and Fig. 7 is a plot showing levels of the quantizer;

Fig. 7 is a graph showing the properties of the quantizer of Fig. 6, in which K is 5;

Fig. 8 is a graph showing the spectrum of the output signal y of a modulator according to Fig. 6 with w=0 and w=3, respectively; M=2^Λ9 in both cases;

Fig. 9 is a diagram of a digital-to-digital Σ-Δ single quantizer feedback modulator having an Lth-order cell; and

Fig. 10 is a graph showing the spectrum of the output signal y of a modulator according to Fig. 9 with w=0 and w=3, respectively; M=2^Λ9 in both cases.

Description of the Embodiments

A digital to digital Sigma-Delta modulator comprises an input which receives a digital input value encoded over no bits, an output which delivers a digital output value encoded over m bits, where m is less than no, and at least a first order Sigma-Delta cell which includes a delayed feedback path with weight w from the output of the quantizer to the summing input. The particular choice of the weight w yields maximum length sequences for all initial values of accumulators and all inputs and thereby minimizes the power of the cycles which may appear depending on the input code of the modulator and on the initial conditions, hi one embodiment, a digital frequency synthesizer incorporating a modulator of the invention is also described, although there are many other advantageous applications.

Fig. 1 shows a digital to digital Σ-Δ modulator 100 of one embodiment. This is a modified error feedback modulator having only a single Σ-Δ cell, of the first order.

The modulator 100 comprises an input 10 to receive successive digital values, each one encoded over no bits, where no is a specified integer, of a digital input signal x. Hereinafter, the letter x denotes both the input signal of the modulator and a particular value of this signal.

The modulator 100 also comprises an output 20 to deliver successive output digital values, each one encoded over a given number m of bits, where m is a specified integer less than no, of a digital output signal >\ In this embodiment, m=l. Hereinafter, the letter y denotes both the output signal of the modulator and a particular value of this signal.

The signal y is equivalent to the signal JC encoded using the modulator. Since the signal y is encoded over a number of bits which is smaller than the number of bits used to encode the signal x, an encoding error is introduced. The structure of the digital to digital Σ-Δ modulator makes it possible to shape this encoding noise (or quantization noise). The modulator 100 is a single Σ-Δ cell. In this embodiment, the modulator 100 is of the first order. It comprises the following elements.

An adder Al comprising a first input 11, a second input 12, a third input 13, and an output 14. The input 11 is coupled to the input 10 of the modulator in order to receive the digital input value x.

A subtracter Sl comprising a first input 21, a second input 22, and an output 23. The input 21 is coupled to the output 14 of the adder.

A quantizer Ql having an input 31 and an output 32. The input 31 is coupled to the output 14 of the adder in order to receive the signal v delivered thereby.

The output 32 is coupled to the output 20 of the modulator in order to deliver the digital values of the output signal y at the sampling frequency Fs. The quantizer Ql has a specified quantization interval, denoted M.

A gain block Gl having an input 41 and an output 42. The input 41 is coupled to the output 32 of the quantizer in order to receive the signal y delivered thereby. The output 42 is coupled to the second input 22 of the subtractor; A delay block Dl with input 51 and output 52. The input 51 is coupled to the output 23 of the subtracter in order to receive the signal e delivered thereby. The output 52 is coupled to the second input 12 of the adder.

A delay block with gain DGl with input 61 and output 62. The input 61 is coupled to the output 32 of the quantizer Ql in order to receive the signal y delivered thereby. The output 62 is coupled to the third input 13 of the adder Al.

The delay with gain block DGl performs the very important function of adding a number to the state of the modulator, hi general terms the number added is determined by the quantizer output level. In this embodiment, the level is one and so the number is always w. hi effect, the block DGl offsets the state by w, and hence the sequence length becomes a prime number. This spreads the energy over a large number of tones, independently of the input and initial conditions, as illustrated in Fig. 4(b).

hi more detail, the output e(t) of the subtracter Sl is expressed, at the time t=nT_s, where T_s denotes the sampling period (T_s =1/F_S), by the following equation: efnj = xfnj + e[n-l] +wy[n-l] —My[n]

The output value y[n] of the modulator is, for a quantizer having two output levels, for example, equal to 1 if v[n] ≥M; otherwise it is equal to 0. The response of such a quantizer with two output levels is illustrated by the graph of Fig. 2. The signal y output from the modulator is then encoded over a single bit (m=l).

The value e(t) changes with each period T_s. Thus, the value of y also changes with time, thereby being periodic. The period of the signal y(t) will be denoted T. This period corresponds to the maximum duration of one cycle of the accumulator, hi some ways, it is the mean value of the signal y(t) over a period T which determines the encoded input value x, and the value of the period that determines the number of tones in the spectrum. For the same value of x, the period T may vary, depending on the values of M and w. Similarly, for the same values of M and w, the time T may vary depending on the value of x.

lfM=2^Λ(no) and w is chosen according to Table 1 to make (M-w) prime, then it can be demonstrated that the period T is defined by the following equation:

T = (M-w) T_s.

Table 1: Values of w to guarantee sequences of length (2^Λ(ΠQ)-W) (for cases 2 ≤z_Q ≤?5).

Table 1

Thus, the time T of a cycle is a maximum when the value of w is chosen such that (M- w) is a prime number.

The case M=8 and w=0 corresponds to a conventional 3-bit Σ-Δ modulator. The cycle period, and hence the number of lines in the spectrum, depends on the value of the input. In the best case, T=87^; in the worst case, T=2T_S.

With the value w chosen from Table 1 , the cycle period always achieves its maximum value, T=1T_S, independently of the input value and the initial condition. This maximizes the number of lines in the spectrum.

Of course, the invention is not limited to the case of a quantizer having only two output levels. Nor is the invention limited to the case of a first-order digital to digital Σ-Δ modulator. The cell of the modulator may be of second order or more. In another embodiment, a modulator comprises a given number L-I of other (additional) Sigma- Delta cells, where L is an integer greater than or equal to 2. hi this case, the L Sigma- Delta cells are preferably arranged according to a MASH structure. Thus, a modulator of order L is obtained when each cell is of the first order. More generally, the order of the modulator is then the sum of the respective orders of the Sigma-Delta cells of the modulator.

An example of a modulator of this type, comprising three cells 100, 200 and 300, that is for the case where L is equal to three (L=3), is shown schematically in Fig. 3. In this figure, the same elements as in Fig. 1 bear the same references, hi addition to the cell 100, the modulator comprises two additional cells 200 and 300.

The three cells have identical structures. This simplifies the production on silicon, hi this example, they are first order cells, that is, they have the same structure as the cell 100. The term "structure of a cell" in this case refers to the overall structure of the cell, that is the type, the number, and the arrangement of the elements of which it is formed. These elements have been described above with regard to the cell 100 shown in Fig. 1.

The respective adders of the cells 100, 200 and 300 are denoted Al, A2 and A3, respectively, the respective subtracters are denoted Sl, S2 and S3, and the respective quantizers are denoted Ql, Q2 and Q3,.

The first input of the adder Al of the cell 100 is coupled to the input 10 of the modulator. The output of the quantizer Ql is coupled to a first input 41 of an adder S 12. The output of the adder S12 is coupled to the output 45 of the modulator through an optional filter Dl 1 in order to deliver the signal y. The first input of the adder A2 of the cell 200 is coupled to the output of the subtracter Sl of the cell 100. The output of the quantizer Q2 is coupled to a first input 43 of another adder S23. The output of the adder S23 is coupled to a second input 42 of the adder S12 through another filter D 12. The first input of the adder A3 of the cell 300 is coupled to the output of the subtractor S2 of the cell 200. The output of the quantizer Q3 is coupled to a second input 44 of the adder S23 through another filter D23.

The first input of the adder A2 of the second cell 200 receives a signal derived from the input signal x. It is coupled to the input 10 in order to receive the signal x through the adder Al and the subtractor Sl of the first cell 100. Similarly, the first input of the adder A3 of the third cell 300 receives a signal derived from the input signal x. It is coupled to the input 10 in order to receive the signal x through the adder Al and the subtractor Sl of the first cell 100, and in addition through the adder A2 and the subtractor S2 of the second cell 200.

The filters DI l, D12, and D23 each introduce a delay (denoted z^"1) corresponding to one period Ts.

The output signal y results from the additive contribution of the signals delivered by the quantizers Ql, Q2 and Q3 of the cells 100, 200 and 300, respectively.

An optional filter DI l corrects for the high frequency pole introduced by the feedback parameter w; this is accomplished by setting a = w/M. The maximum sequence length is also obtained when DI l is a unity gain block (i.e., a = 0).

The respective quantization intervals of the quantizers Ql, Q2 and Q3 of each of the cells 100, 200 and 300, respectively, are all equal to the same number denoted M.

The cycle length N_L of such an L^ order MASH modulator comprising the modulator of the first embodiment of the invention is always a maximum value independently of initial conditions and the input and is determined by:

N_L = N^L = (M - w)^L,

where L is the number of similar first order stages used in the MASH i.e. the cycle length is multiplied by N for every increase in the order of the modulator by l. Fig. 4 shows the spectra of the quantization noise for two third-order MASH Σ-Δ modulators of the type illustrated in Fig. 3. Fig. 4(a) corresponds to a cascade of three first-order error-feedback modulators of the type shown in Fig. 1 with M=2^Λ9 and w=0; this is representative of a conventional 9-bit structure. Fig. 4(b) corresponds to a cascade of three first-order error-feedback modulators of the type shown in Fig. 1 with M=2^Λ9 and w=3.

As can be seen, the energy of the quantization noise (high-frequency noise) is distributed over many more lines in Fig. 4(b) than in Fig. 4(a). Moreover, the level of these lines is clearly much lower for Fig. 4(b) than in the case of Fig. 4(a).

Fig. 5 illustrates a digital frequency synthesizer incorporating the modulator 100. The synthesizer comprises a phase-locked loop (PLL) with a charge pump. The PLL comprises the following elements in a loop: a phase frequency detector (PFD) 81 ; a charge pump (CP) 82; a loop filter 83, which is a low-pass filter (integrator); a voltage controlled oscillator (VCO) 84; a variable frequency divider 85, the variable ratio of which is denoted M_div in the figure and hereinafter.

The phase detector 81 detects the phase difference between a reference frequency F_re/ and the frequency F_vco of the output signal of the VCO divided by the ratio M_d,_v of the frequency divider 85. It applies charge-up and charge-down pulses U and D, respectively, to the charge pump 82. These pulses are used to switch voltage or current sources, which charge or discharge a capacitor of the loop filter 83. The loop filters these pulses and delivers a resulting control voltage to the VCO. The oscillation frequency F_vco of the VCO is altered as a function of this control voltage. Thus, the PLL forms a looped system in which the frequency F_vco of the signal at the output of the VCO is locked onto the frequency Ε_ref><M_di_V. The output from the system is the output from the VCO. The frequency divider is included in the feedback path. It comprises a control signal for the division ratio M_</,_v, which receives a control signal (also denoted M^v for convenience) making it possible to change the value of the frequency F_vco of the output signal of the PLL.

The control signal for the division ratio M^v of the frequency divider 85 is generated by the digital to digital Σ-Δ modulator 100.

hi the example shown, the ratio M_ΛV comprises an integer part Int(Mrf,_v) and a fractional part Frac(M_</,_v) which are added in an adder 86. The output of the adder 86 delivers the control signal M_d,_v. The synthesizer comprises the digital to digital Σ-Δ modulator 100 (it could alternatively be that of Fig. 3) in order to encode the fractional part Frac(Mr_f!V) of the signal M^v before it is added to the integer path Int(M_<#v) of this signal.

The modulator 100 receives as an input the signal Frac(Mr_fiV) encoded over no bits, and delivers at the output a corresponding signal encoded over m bits, where m is less than no, which is added to the signal Int(lvU_v) in the adder 86 in order to form the control signal for the division ratio M_</,_v of the frequency divider 85 of the PLL. The interference lines of the signal over m bits at the output of the Σ.-Δ modulator 100 are eliminated by the low-pass filtering of the PLL.

In certain applications, the signal

may determine the frequency of a channel and the signal Frac(M_</iV) may be a phase or frequency modulation signal. This is only one example of an application. It is understood that the invention can be used in this type of application, since it makes it possible to preserve the spectral purity of the output signal of the VCO. This is advantageous, in particular, in the applications of the synthesizer to a radio frequency transmitter.

The particular choice of the weight w, as specified in Table 1, yields maximum length sequences for all initial values of accumulators and all inputs and thereby minimizes the power of the cycles which may appear depending on the input code of the modulator and on the initial conditions. Referring to Fig. 6, a single-cell modulator 1100 has a multi-level quantizer QI l. The modulator 1100 comprises an input 110 in order to receive the successive digital values, each one encoded over no bits, where no is a specified integer, of a digital input signal x. An output 120 delivers the successive digital values, each one encoded over a given number m of bits, where m is a specified integer less than no, of a digital output signal y. In this embodiment, m=3. The signal y is equivalent to the signal x encoded using the modulator. Since the signal y is encoded over a number of bits which is smaller than the number of bits used to encode the signal x, an encoding error is introduced. The structure of the digital to digital Σ-Δ modulator makes it possible to shape this encoding noise (or quantization noise).

The modulator 1100 comprises the following elements.

An adder Al l comprising a first input 111, a second input 112, a third input 113, and an output 114. The input 111 is coupled to the input 110 of the modulator in order to receive the digital input value x;

A subtracter SI l comprising a first input 121, a second input 122 and an output 123. The input 121 is coupled to the output 114 of the adder.

The quantizer QI l having an input 131 and an output 132. The input 131 is coupled to the output 114 of the adder in order to receive the signal v delivered thereby. The output 132 is coupled to the output 120 of the modulator in order to deliver the digital values of the output signal y at the sampling frequency Fs. The quantizer QI l has a specified uniform quantization interval, denoted M.

A gain block GI l having an input 141 and an output 142. The input 141 is coupled to the output 132 of the quantizer in order to receive the signal y delivered thereby. The output 142 is coupled to the second input 122 of the subtracter.

A filter delay block FDI l with input 151 and output 152. The input 151 is coupled to the output 123 of the subtracter in order to receive the signal e delivered thereby. The output 152 is coupled to the second input 112 of the adder; and

A delay block with gain DGl 1 with input 161 and output 162. The input 161 is coupled to the output 132 of the quantizer Ql 1 in order to receive the signal y delivered thereby. The output 162 is coupled to the third input 113 of the adder

Al l.

The output value y[n] of the modulator is, for a quantizer having five output levels, for example, equal to -2 if v[n] < -3M/2, -1 if -3M/2< v[n] < -M/2, 0 if -M/2< v[n] < M/2, etc., as illustrated by the graph in Fig. 7. The signal y output from the modulator is encoded over three bits (m=3) in this case.

Define the quantization noise as the error introduced by the quantizer. Thus, e_g[nj = y[n]-v[n].

In the Z-domain, the output Y(z) is defined by the following equation:

Y(z) = STF(z) X(z) + NTF(z) E(z)

where E(z) is the Z-transform of the quantization noise e_q, and STF and NTF are the signal transfer function and noise transfer function, respectively.

If H(z) = 1 - (J-z^'1)¹ in the modulator shown in Fig. 6, then the signal and transfer functions are defined by: STF(z) = 1/(1-WZ ¹ZM)

NTF(z) = (1-z ¹)¹ /(1-WZ ¹M)

The digital delta-sigma modulator is a finite state machine and therefore produces a periodic output when the input is fixed. The length of the periodic sequence can be maximized by choosing the value of w. If M=2^Λ(no) and w is chosen according to Table 1 to make (M-w) prime, then it can be demonstrated that the sequence period T is defined by the following equation: T = (M-W)^L T_s. where Ts is the period of the clock.

The case M=512 and w=0 corresponds to a conventional 9-bit Σ-Δ modulator. The cycle period, and hence the number of lines in the spectrum, depends on the value of the input. In the worst case, shown in Fig. 8, T=2T_S. With the value w=3 chosen from Table 1, the cycle period always achieves its maximum value, T=509^zT_i, independently of the input value and the initial condition. This maximizes the number of lines in the spectrum.

Fig. 9 shows a single quantizer delta-si gma modulator 2100 comprising an input 210 in order to receive the successive digital values, each one encoded over no bits, where no is a specified integer, of a digital input signal x. The modulator 2100 also comprises an output 220 in order to deliver the successive digital values, each one encoded over a given number m of bits, where m is a specified integer less than no, of a digital output signal y. In this embodiment, m=3. The signal y is equivalent to the signal x encoded using the modulator. Since the signal y is encoded over a number of bits which is smaller than the number of bits used to encode the signal x, an encoding error is introduced. The structure of the digital to digital Σ-Δ modulator makes it possible to shape this encoding noise (or quantization noise).

The single Σ-Δ cell modulator 2100 comprises the following elements:

An adder A21 comprising a first input 21.1, a second input 212, a third input 213, and an output 214. The input 211 is coupled to the input 210 of the modulator in order to receive the digital input value x.

A feedforward filter FF21 with input 221 and output 222. The input 221 is coupled to the output 214 of the summer A21. The output 222 is coupled to the input 231 of the quantizer Q21. A quantizer Q21 having an input 231 and an output 232. The input 231 is coupled to the output 222 of the feedforward filter in order to receive the signal v delivered thereby. The output 232 is coupled to the output 220 of the modulator in order to deliver the digital values of the output signal y at the sampling frequency Fs. The quantizer Q21 has a specified uniform quantization interval, denoted M.

A gain block G21 with gain M having an input 241 and an output 242. The input 241 is coupled to the output 232 of the quantizer in order to receive the signal y delivered thereby. The output 242 is coupled to the input 251 of the feedback filter.

A feedback filter FB21 with input 251 and output 252. The input 251 is coupled to the output 242 of the gain block. The output 252 is coupled to the second input 212 of the adder.

A block with gain G22 with input 261 and output 262. The input 261 is coupled to the output 232 of the quantizer Q21 in order to receive the signal y delivered thereby. The output 262 is coupled to the third input 213 of the adder

A21.

The output value y[n] of the modulator is, for a quantizer having five output levels, for example, equal to -2 if v[n] < -3M/2, -1 if -3M/2< v[n] < -M/2, 0 if -M/2< v[n\ < M/2, etc., as illustrated by the graph in Fig. 7. The signal y output from the modulator is encoded over three bits (m=3) in this case.

The modulator shown in Fig. 9 has signal and transfer functions defined by:

STF(z) = F(z)/fl+F(z)G(z)-wF(z)/MJ NTF(z) = l/fl+F(z)G(z)-wF(z)/MJ

A choice for F(z) and G(z) that is well-known to practitioners in the field is:

F(Z) = Z ¹O-Z ¹)-¹ G(z) =z^L - (Z-I)¹

With this choice for F(z) and G(z), the modulator shown in Fig. 9, has signal and transfer functions defined by: STF(z) = z^L/(l-wz ^! /M)

NTF(z) = (1-z ^Λ)^L /(1-WZ ¹IM)

The digital delta-sigma modulator is a finite state machine and therefore produces a periodic output when the input is fixed. The length of the periodic sequence can be maximized by choosing the value of w. If M=2^A(no) and w is chosen according to

Table 1 to make (M-w) prime, then it can be demonstrated that the sequence period T is defined by the following equation:

T = (M-w)^L T_s. where Ts is the period of the clock.

The case M=512 and w=0 corresponds to a conventional 9-bit Σ-Δ modulator. The cycle period, and hence the number of lines in the spectrum, depends on the value of the input, hi the worst case, shown in Fig. 10, T=2T_S.

With the value w chosen from Table 1 , the cycle period always achieves its maximum value, T=509^zT_J, independently of the input value and the initial condition. This maximizes the number of lines in the spectrum.

Of course, the invention is not limited to the case of single-quantizer digital to digital Σ-Δ modulators. The cell 1100 or 2100 of the modulator may be of second order or more. As described with reference to Fig. 3 the modulators may also be arranged in a MASH structure. The cycle length N_L of such an L^ώ order MASH modulator comprising the modulator of the first embodiment of the invention is always a maximum value independently of initial conditions and the input and is determined by:

N_L=N¹ = (M-w)^L,

where L is the number of similar first order stages used in the MASH. In other words, the cycle length is multiplied by N for every increase in the order of the modulator by 1.

It will be appreciated that the modulators of the invention produce a sequence length of T^L, where P is a prime number and L is the order of the modulator. The quantizer overflows when it reaches a power of 2 (M) and offsets the state in such a way that it appears like a prime number (by adding a number w). A major advantage of the invention compared to the arrangement of Level et al is that it is easier to implement a power-of-2 quantizer in hardware than a prime number quantizer.

Another advantage is that an Zth order MASH structure constructed using our modulator also has a sequence length of P^ ^=[M-w]^L). For comparison purposes, consider a third order MASH DDSM with a 9-bit word and a constant input. Using a power-of-2 quantizer, the sequence length could range from 4 to 1024, depending on the input. Using Level et al's approach and a prime modulus quantizer with P=509, the sequence length is always 509 and the quantization noise is spread over 509 tones. Using our approach (a power-of-two quantizer with M=512 and w=3), the sequence length is 509³ and the quantization noise is spread over 131872229 tones.

The invention is not limited to the embodiments described but may be varied in construction and detail.

Claims

1. A digital to digital Sigma-Delta modulator ( 100) of order L comprising: a signal input (10, 111, 210) to receive a digital input value encoded over a given number no of bits, where no is an integer; an output (20, 120, 220) for delivering a digital output value encoded over a given number m of bits, where m is an integer less than no; and at least one Sigma-Delta cell comprising: an adder (Al, Al l, A21) for receiving an input signal and feedback, and a quantizer (Ql, Ql 1, Q21) with interval M; wherein the cell further comprises means (DGl, G22) for monitoring the quantizer and for adding a number w to the state of the cell, said number being added according to the output of the quantizer in order to offset the cell state so that the cell sequence length (M- w)^L becomes a power of a prime number.

2. A modulator as claimed in claim 1, wherein the monitoring means (DGl, G22) monitors the output of the quantizer (Ql, Ql 1, Q21).

3. A modulator as claimed in claims 1 or 2, wherein the quantizer (Ql, QI l, Q21) interval M = 2"° .

4. A modulator as claimed in claim 3, wherein the number w has a value according to the following table:

5. A modulator as claimed in any preceding claim, wherein the monitoring means (DGl, G22) is in an auxiliary feedback loop (61-62, 161-162, 261-262) between the quantizer (Ql, QI l, Q21) and the adder (Al, Al 1, A21).

6. A modulator as claimed in claim 5, wherein the monitoring means comprises a gain component (DGl, G22) which adds the number w into the state of the cell.

7. A modulator as claimed in any of claims 3 to 6 wherein:

the adder (Al, Al l, A21) comprises a first input, a second input, a third input, and an output, the first input being coupled to said signal input, the second input being coupled to the output of a filter block of a feedback path, the third input being coupled to the auxiliary feedback loop; the cell comprises a subtractor ((Sl, SI l) comprising a first input coupled to said adder output and an output coupled to the input of a filter; the quantizer (Ql, Ql 1, Q21) has an input coupled to said adder output, and an output coupled to the output of the modulator and furthermore coupled to the auxiliary feedback loop and, via a gain block, to the second input of the subtractor; the auxiliary feedback loop comprises a gain component providing a gain of w, and its output is coupled to the third input of the adder.

8. A modulator as claimed in any of claims 1 to 6, wherein the cell comprises a feedforward filter (FF21) having a first input (221) coupled to said adder (A21), and an output (222) coupled to the input (231) of the quantizer (Q21).

9. A modulator as claimed in any preceding claim, further comprising a number L-I of other Sigma-Delta cells, where L is an integer greater than or equal to 2, the L cells being arranged according to a MASH structure, and wherein a quantization interval, gain M, and added number w of each of said L cells are equal.

10. A digital frequency synthesizer (81-86, 100) comprising a modulator (100) of any preceding claim.

11. A digital to digital Sigma-Delta modulator substantially as described herein with reference to Fig. 1.

12. .A digital to digital Sigma-Delta modulator substantially as described herein with reference to Fig. 3.

13. A digital to digital Sigma-Delta modulator substantially as described herein with reference to Fig. 6.

14. A digital to digital Sigma-Delta modulator substantially as described herein with reference to Fig. 9.