CN108566200A - A kind of divider controller circuit, phaselocked loop and chip - Google Patents
A kind of divider controller circuit, phaselocked loop and chip Download PDFInfo
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- CN108566200A CN108566200A CN201810393352.6A CN201810393352A CN108566200A CN 108566200 A CN108566200 A CN 108566200A CN 201810393352 A CN201810393352 A CN 201810393352A CN 108566200 A CN108566200 A CN 108566200A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
Abstract
The embodiment of the present application discloses a kind of divider controller circuit, phaselocked loop and chip, including：The first signal input part input in conjunction with adder is periodic first digital signal within a preset period of time；The signal input part of digital filter inputs the second digital signal of uniform aperiodicity shake, and the signal output end connection of digital filter combines the second signal input terminal of adder；First digital signal is added the third digital signal for generating aperiodicity shake with the second digital signal in combining adder；The signal input part of DDSM is connected in conjunction with the signal output end of adder, DDSM will export a fractional frequency signal according to third digital signal.Third digital signal enters the zig-zag random distribution in the fractional frequency signal phase noise generated after DDSM, fractional frequency signal processing after input phaselocked loop phase discriminator feedback signal phase noise in zig-zag break up at random, and then can reduce because non-thread sexual maladjustment generate it is spuious.
Description
Technical field
This application involves a kind of semiconductor circuit technology field more particularly to divider controller circuit, phaselocked loop and cores
Piece.
Background technology
Need one or more carrier signals the modulates information to be transmitted to particular channel frequency in a wireless communication system
Rate, or it is that subsequent signal processing is prepared that the radiofrequency signal solution received, which is transferred to base band,.In traditional technology, carrier signal
It is to be generated by the frequency synthesizer of a fractional frequency division.
As shown in Figure 1, being a kind of structural schematic diagram of fractional frequency-division phase-locked loop.Phase discriminator detects input signal and feedback letter
Number frequency difference and difference, generate pulse control signal be sent into charge pump.Pulse control signal is converted into electric current to ring by charge pump
The capacitance Cp of path filter carries out charge and discharge.Loop filter generates control voltage and is sent into voltage controlled oscillator, voltage controlled oscillator
Output signal generates feedback signal by frequency divider, and feedback signal is as divider controller clock signal, divider controller
One fractional frequency signal of output is added to obtain a new divider ratio control divider controller calculating with a fixed divider ratio
New feedback signal.New feedback signal will be fed back to phase discriminator, form a reponse system.Reponse system is until new anti-
When feedback signal is consistent with input signal phase, or one fixed value of difference, by phase lock loop locks.
Due to divider controller input digital signal be one section of INVENTIONPeriodic digital signals and variation it is slower,
Correlation is strong, makes that the fractional frequency signal phase noise that the divider controller in circuit exports is equal due to characteristics of signals
Even zig-zag, when phase discriminator and the non-thread sexual maladjustment of charge pump, the new feedback signal phase that is generated according to fractional frequency signal
The zig-zag of noise just will produce many spuious.Spuious the having in phaselocked loop band and out-of-band of non-thread sexual maladjustment generation, locks
Phase ring loop low pass wave can play inhibiting effect to spuious outside band, and to spuious in band, it can not inhibit so that be
The signal-to-noise ratio degradation of system.
Invention content
This application provides a kind of divider controller circuit, phaselocked loop and chips, to solve in traditional phaselocked loop
When phase discriminator and the non-thread sexual maladjustment of charge pump, led to the problem of in phase-locked loop spuious.
In order to solve the above-mentioned technical problem, the embodiment of the present application discloses following technical solution：
In a first aspect, the embodiment of the present application provides a kind of divider controller circuit, including：In conjunction with adder, in conjunction with
First signal input part of adder inputs the first digital signal, and the first digital signal is INVENTIONPeriodic digital within a preset period of time
Signal；The signal input part of digital filter, digital filter inputs the second digital signal, and the second digital signal is to be uniformly distributed
Aperiodic jittered digital signal, the signal output end connection of digital filter combine the second signal input terminal of adder；First
Digital signal is added in combining adder with the second digital signal and generates third digital signal, and third digital signal is aperiodic
Property jittered digital signal；Digital Delta-Sigma modulators (Digital Delta-Sigma Modulator, DDSM), in conjunction with
The signal input part of the signal output end connection DDSM of adder, the signal output end that third digital signal passes through combination adder
It is input to DDSM, DDSM will export a fractional frequency signal according to third digital signal, and fractional frequency signal is used to control the frequency dividing of phaselocked loop
Device.The third digital signal that the second digital signal introduced through digital filter generates after being added with the first digital signal is non-week
The jittered digital signal of phase property, according to the weak principle of the correlation of acyclic jittered digital signal so that third number is believed
Number zig-zag random distribution in the fractional frequency signal phase noise generated after DDSM is entered, so that at according to fractional frequency signal
The zig-zag being input to after reason in the feedback signal phase noise of phaselocked loop phase discriminator is broken up at random, and then is reduced because non-thread
Sexual maladjustment generates spuious.
Second aspect, the embodiment of the present application provide a kind of divider controller circuit, including：Digital filter, number
The signal input part of filter inputs the 4th digital signal, and the 4th digital signal is to be uniformly distributed aperiodicity jittered digital letter
Number；DDSM, DDSM are N ranks MASH (Multi Stage Noise Shaping, multi-stage noise shaping modulator), N >=2, N ranks
The EFM (Error Feedback Modulator, noise difference feedback modulator) of the first ranks of MASH includes left-hand adder and low
Position adder, the carry input of the carry output connection left-hand adder of right-hand adder, the first letter of left-hand adder
Number input terminal inputs the 5th digital signal, and the first signal input part of right-hand adder inputs the 6th digital signal, the 5th number
Signal is preset time period periodically high-order digit signal, and the 6th digital signal is preset time period periodically low order digit
Signal；In conjunction with adder, the carry output and addition output end of left-hand adder are all connected with the first signal in conjunction with adder
Input terminal connects the signal output end of digital filter, the addition of right-hand adder in conjunction with the second signal input terminal of adder
Output end is connected with the second-order EFM of N ranks MASH with the addition output end of adder is combined.It is introduced through digital filter
The digital signal that 4th digital signal generates after being added with the digital signal exported through left-hand adder is acyclic shake
Digital signal, therefore the digital signal of adder addition output end output and right-hand adder addition output end composition is combined to generate
It is acyclic jittered digital signal, according to the weak principle of the correlation of acyclic jittered digital signal so that
Zig-zag random distribution in the fractional frequency signal phase noise that DDSM is ultimately generated, so that after being handled according to fractional frequency signal
The zig-zag for being input to the feedback signal phase noise of phaselocked loop phase discriminator is broken up at random, and then is reduced because of non-thread sexual maladjustment
What is generated is spuious.
The third aspect, the embodiment of the present application provide a kind of phaselocked loop, including frequency divider, phase discriminator, charge pump and frequency dividing
Device controller, divider controller include divider controller circuit, respectively into divider controller input preset time period
For periodic digital signal and it is uniformly distributed aperiodic jittered digital signal, obtains aperiodicity jittered digital signal, according to
Aperiodicity jittered digital signal generates a fractional frequency signal and exports to frequency divider, and frequency divider calculates defeated according to the fractional frequency signal of reception
Enter the feedback signal of phase discriminator, phase discriminator generates pulse control signal according to feedback signal and is sent to charge pump.Due to frequency divider
Divider controller circuit in controller can to export to the feedback signal phase noise saw in the time domain of phase discriminator
Tooth waveform random distribution, so that being input to the sawtooth of the feedback signal phase noise of phase discriminator after being handled according to fractional frequency signal
Waveform is broken up at random, so reduce because non-thread sexual maladjustment generate it is spuious.
Fourth aspect, the embodiment of the present application provide a kind of chip, including：Microprocessor；At storage microprocessor
Manage the memory of executable instruction；Phaselocked loop is provided with divider controller circuit in phaselocked loop.Since phaselocked loop can be reduced
Because non-thread sexual maladjustment generate it is spuious, optimize the signal-to-noise ratio of chip system.
Description of the drawings
In order to illustrate more clearly of the technical solution of the application, letter will be made to attached drawing needed in the embodiment below
Singly introduce, it should be apparent that, for those of ordinary skills, without having to pay creative labor,
Other drawings may also be obtained based on these drawings.
Fig. 1 is the structural schematic diagram of traditional fractional frequency-division phase-locked loop；
Fig. 2 is a kind of structural schematic diagram of divider controller circuit provided by the present application；
Fig. 3 is a kind of phase noise spectrum figure provided by the present application；
Fig. 4 is another phase noise spectrum figure provided by the present application；
Fig. 5 is the structural schematic diagram of another divider controller circuit provided by the present application；
Fig. 6 is the structural schematic diagram of another divider controller circuit provided by the present application；
Fig. 7 is the structural schematic diagram of 3 rank MASH provided by the present application；
Fig. 8 is a kind of structural schematic diagram of phaselocked loop provided by the present application；
Fig. 9 is a kind of structural schematic diagram of chip provided by the present application.
Specific implementation mode
The application is described in detail below in conjunction with the accompanying drawings.
It is illustrated in figure 2 a kind of divider controller circuit provided by the present application, including combines adder, digital filter
And DDSM, the first digital signal is inputted in conjunction with the first signal end of adder, in the first digital signal and traditional phaselocked loop
It is periodic digital signal that the digital signal that divider controller receives, which is all mutually in one section of preset time,.In the present embodiment,
Preset time period is longer, may be more than ten of clock cycle, primary it is also assumed that the first digital signal is that one end variation is slow
Digital signal.The signal input part that DDSM is connected in conjunction with the output end of adder, since the first digital signal is in preset time
It is interior to be considered as a constant or a slowly varying number, by the correlation principle of signal, the correlation of the first digital signal
It is relatively strong.So that the combined adder of the first digital signal enters meeting output frequency division signal after DDSM, fractional frequency signal phase
There are sawtooth waveforms in noise waveform, and the feedback signal due to entering eventually into phase discriminator is the frequency dividing according to the output of DDSM
What signal processing generated, once non-thread sexual maladjustment occurs for phase discriminator, corresponding sawtooth wave position is then in feedback signal phase noise
Meeting Nonlinear Superposition generates a large amount of spuious.
The signal input part of digital filter in the embodiment of the present application inputs the second digital signal, the second digital signal
Purpose is exactly the sawtooth wave reduced from source in the frequency signal phase noise waveform that DDSM is exported.The effect of digital filter herein
Be the noise filtering in the second digital signal is fallen, in order to avoid influence the second digital signal in influence of noise be input in DDSM
Signal energy.It is one section of digital signal that can be considered as constant that the generation of zig-zag, which is due to entering the signal in DDSM,
As long as therefore the signal entered in DDSM, which is become the irregular dither signal that one section changes greatly, can reduce signal
Correlation, to reduce the sawtooth wave in fractional frequency signal phase noise waveform.Therefore the second digital signal in the application is equal
The even aperiodic jittered digital signal of distribution, it is pointed out that the second digital signal must be that energy is uniform, it is therefore an objective to so that
Second digital signal ensures that the energy of the first digital signal is equal in combining adder with the first digital signal after overlap-add procedure
Even.
It can be seen from the above, it is INVENTIONPeriodic digital signals within a preset period of time that the first digital signal, which is one section, signal is related
Property is stronger.Second digital signal be uniformly distributed aperiodic jittered digital signal, and the second digital signal be one section significantly
Dither signal, the third digital signal generated after can just making the first digital signal and the second digital signal be superimposed in this way are one
Significantly dither signal, signal correlation are smaller for section aperiodicity.Due to the characteristic of third digital signal, produced after being input to DDSM
Sawtooth wave in raw fractional frequency signal phase noise waveform also greatly reduces, and is discrete presence.In this way by the frequency dividing of output
It is sent to frequency divider after one fixed divider ratio of Signal averaging, the feedback signal phase being input in phase discriminator finally obtained
There is also a small amount of zig-zags in noise waveform, though non-thread sexual maladjustment occurs for phase discriminator, and discrete existing a small amount of
It is non-linear at sawtooth wave that generation must be added spuious.
If being pointed out that the spectral power density of the second digital signal is less than the quantization noise spectrum power of DDSM
When density, the bit wide of corresponding second digital signal is less than the bit wide of the first digital signal, then to the correlation of weakening input and output
Property is weaker.On the contrary, if the spectral power density of the second digital signal be more than DDSM quantization noise spectrum power density when,
The bit wide of corresponding second digital signal is more than the bit wide of the first digital signal, then the output of DDSM at this time can be believed with the second number
Number become whitening to be leading, and the fractional frequency signal bit wide of DDSM outputs can also become wide.Therefore in the present embodiment
The bit wide of first digital signal and the second number is consistent.
In an illustrative embodiment, it is assumed that the first digital signal is
00000000000000001111111111111111, think the first digital signal to be for the time being in one section of preset time be periodically
Digital signal.It can be seen from the above, the correlation of the input and output of the first digital signal is stronger, therefore introduce the second digital signal
01101011001011010001100101011010,0 and 1 irregular distribution in the second digital signal, but 0 and 1 number
Amount is identical, and then ensure that the second digital signal is one section of uniform aperiodicity jittered digital signal.If according to
The feedback signal that one digital signal generates enters phase discriminator and phase noise spectrum figure such as Fig. 3 after non-thread sexual maladjustment occurs, then
It is input to DDSM after first digital signal is added with the second digital signal, the feedback signal ultimately generated enters phase discriminator hair
Phase noise spectrum figure such as Fig. 4 after raw non-thread sexual maladjustment, compares Fig. 3 and Fig. 4, and spuious in Fig. 4 significantly reduces.Certainly, on
It states the citing to the first digital signal and the second digital signal and the corresponding phase noise spectrum figure generated is only schematical.
It is added with the first digital signal seeing as the second digital signal introduced through digital filter by above-described embodiment
The third digital signal generated afterwards is acyclic jittered digital signal, according to the correlation of acyclic jittered digital signal
The weak principle of property so that third digital signal enters zig-zag in the fractional frequency signal phase noise generated after DDSM and divides at random
Cloth, so that being input to the zig-zag in the feedback signal phase noise of phaselocked loop phase discriminator after being handled according to fractional frequency signal
Broken up at random, so reduce because non-thread sexual maladjustment generate it is spuious.
Indicate in the above-described embodiments the first digital signal and the second digital signal must bit wide be identical, therefore it is false
If the first digital signal is N-bit, then the second digital signal also must be N-bit, and corresponding digital filter also must be N ratios
Superfine, virtually increase the area of circuit.
In order to which under the premise of not influencing spuious, circuit area can be reduced, the embodiment of the present application also provides another
Divider controller circuit.As shown in figure 5, including combining adder, digital filter, bit wide amplifier and DDSM.With it is above-mentioned
Unlike the divider controller circuit that embodiment provides, in the present embodiment between digital filter and combination adder
One bit wide amplifier is set, and the effect of bit wide amplifier can carry out the digital signal of small bit wide according to corresponding magnification ratio
Amplification.
Referring still to the above-mentioned schematic example provided, if Fig. 2 shows divider controller circuit in input
First digital signal and the second digital signal are N-bit, then digital filter also must be N-bit grade.And in the present embodiment,
The amplification factor that bit wide amplifier can be set makes the bit wide of the second digital signal for N/2 bits, therefore corresponding digital filtering
Device is N/2 bit-levels, therefore the divider controller circuit relatively in above-described embodiment, and the digital filter in circuit just lacks N/
The area of 2 bits.
Although the hardware area of the digital filter of the corresponding reduction of above-described embodiment, it is still original to combine adder
Circuit area if being N-bit according to being input in conjunction with the digital signal in adder be also N ratios in conjunction with adder
Superfine.Therefore it is also prodigious in conjunction with the hardware area of adder.
To solve the above-mentioned problems, the embodiment of the present application provides the third divider controller circuit again, such as Fig. 6 institutes
Show, divider controller circuit provided in this embodiment includes digital filter, in conjunction with adder and DDSM.Wherein DDSM is N
Rank MASH, N >=2.Since the spectrogram of 3 rank MASH outputs is optimal, the DDSM in corresponding above-mentioned other embodiment is 3
Rank MASH, what is provided such as Fig. 7 is a kind of structural schematic diagram of 3 rank MASH, and the Cout of adder is carry output in Fig. 7,
Sout is addition output end, and Cin is carry input, and 1/Z is flip-flop element.
Therefore the adder in the EFM in 3 the first ranks of rank MASH is divided into a high position by taking 3 rank MASH as an example in the present embodiment
Adder and right-hand adder, corresponding the first digital signal by above-described embodiment are divided into high-order piece of digital signal and low level
High-order piece of digital signal definition is for the time being the 5th digital signal, low level in the present embodiment to describe aspect by piece of digital signal
Piece of digital signal definition is the 6th digital signal.5th digital signal and the 6th digital signal are preset time period periodically
Digital signal.6th digital signal compares one clock cycle of the 5th delayed digital signal, the right-hand adder in the present embodiment
Carry output connection left-hand adder carry input, the carry of the overflow position of right-hand adder as left-hand adder
Input.First signal input part of left-hand adder inputs the 5th digital signal, and the first signal input part of right-hand adder is defeated
Enter the 6th digital signal.The overflow position of the carry output of left-hand adder and the addition output end signal of left-hand adder merge
At a bus the first signal input part in conjunction with adder is input in up to one 0 composition section digital signal of benefit.
The signal output end of digital filter, the addition of right-hand adder are connected in conjunction with the second signal input terminal of adder
Output end is connected with the second-order EFM of 3 rank MASH with the addition output end of adder is combined.Since left-hand adder inputs
The 5th digital signal be high-order piece of digital signal, therefore the digital signal of input filter also should mutually should be uniformly aperiodic
Property high-order piece of digital signal, the uniform acyclic high-order piece of digital signal for inputting digital filter is determined in the present embodiment
Justice is the 4th digital signal.
Further, the EFM of 3 the first ranks of rank MASH further includes the first flip-flop element and the second flip-flop element, and first
Flip-flop element is separately connected the addition output end of right-hand adder and the second signal input terminal with right-hand adder, and second touches
Hair device unit be separately connected in conjunction with adder addition output end and with the second signal input terminal of the left-hand adder.In conjunction with
The carry output of adder connects the error concealment filter of 3 rank MASH.
Assuming that with the above-mentioned example provided, the first digital signal is N-bit, does not have a holiday or vacation set the 5th number in the present embodiment
Signal and the 6th digital signal are N/2 bits, then the 4th digital signal is also N/2 bits, and adder is combined due to being input to
In digital signal be left-hand adder carry output overflow position and left-hand adder addition output end signal merge
It forms, and one 0 has been mended in a high position again intermediate, therefore enter the digital signal in conjunction with the first signal input part of adder
For N/2+2 bits knot is entered in conjunction with the digital signal that the first signal input part of adder inputs to ensure the equilibrium of signal
After closing in adder, the carry output directly by high two by combining adder overflows the error for being input to 3 rank MASH
It eliminates and is filtered out in filter.Accordingly, in conjunction with the of the corresponding low level output end of addition of adder and 3 rank MASH in the present embodiment
Second order EFM is connected.
By above-mentioned analysis, since the 5th digital signal of left-hand adder input is N/2 bits, number in the present embodiment
The fourth signal of filter input is N/2 bits, then combines adder to become N/2 bit-levels, digital filter is also N/2 bits
Grade, and left-hand adder is added with right-hand adder or N-bit, therefore be equivalent under the premise of no change DDSM areas,
The area of digital filter and combination adder is reduced half simultaneously, digital filter is greatly saved and combines addition
Hardware configuration in device.Certainly above-mentioned is exemplary, if the 5th digital signal being input in left-hand adder is N/5
Bit then combines adder and digital filter to reduce 4N/5 adder accordingly, other citings are not repeating one by one.
The 4th digital signal introduced through digital filter generates after being added with the digital signal exported through left-hand adder
Digital signal be acyclic jittered digital signal, therefore combine the digital signal and low of adder addition output end output
It is acyclic jittered digital signal that position adder addition output end composition, which generates, is believed according to acyclic jittered digital
Number the weak principle of correlation so that the zig-zag in the fractional frequency signal phase noise that DDSM is ultimately generated is broken up at random,
So that being input to the zig-zag of the feedback signal phase noise of phaselocked loop phase discriminator after being handled according to fractional frequency signal is also
Random distribution, and then reduce because non-thread sexual maladjustment generates spuious, and the digital filter in the present embodiment and combination
Adder can reduce internal hardware configuration, further reduced the circuit area and power consumption of divider controller circuit.
Corresponding with the embodiment of divider controller circuit of above-mentioned offer, present invention also provides a kind of phaselocked loops
Embodiment, as shown in figure 8, including frequency divider, phase discriminator, charge pump and divider controller.
Divider controller wherein in the present embodiment includes divider controller circuit, and frequency divider control circuit includes
Digital filter, in conjunction with adder and DDSM.It is periodic digital signal into divider controller input preset time period
Be uniformly distributed aperiodic jittered digital signal, combination adder in divided device control circuit obtains aperiodicity after being added
Jittered digital signal generates a fractional frequency signal according to aperiodicity jittered digital signal and exports to frequency divider, and frequency divider is according to connecing
The fractional frequency signal of receipts calculates the feedback signal of input phase discriminator, and phase discriminator generates pulse control signal according to feedback signal and is sent to
Charge pump.
Since the divider controller circuit in divider controller can to export to the feedback signal phase of phase discriminator
Zig-zag random distribution in the noise of position, so that being input to the feedback signal phase of phase discriminator after being handled according to fractional frequency signal
The zig-zag of position noise is also random distribution, and then is reduced because non-thread sexual maladjustment generates spuious, and phaselocked loop is improved
The signal-to-noise ratio of system.
By above-described embodiment it is found that the embodiment of the present application provides 3 kinds of divider controller circuits, so if according to need
It wants, the divider controller in phaselocked loop can select optimal divider controller circuit, to reduce frequency divider in digital phase-locking
The circuit area of controller circuitry.
Corresponding, the embodiment of the present application also provides a kind of chips, as shown in figure 9, chip provided by the present application includes micro-
Processor, memory and phaselocked loop.
Memory is used for the executable instruction of storage microprocessor processing, and the executable instruction of memory storage includes program
Code, program code include computer-managed instruction.Memory may include random access memory (random access
Memory, abbreviation RAM), it is also possible to further include nonvolatile memory (non-volatile memory), for example, at least one
Magnetic disk storage.
A microprocessor is illustrated only in figure, certainly, microprocessor can also be as needed, is multi-microprocessor.
Microprocessor, for reading the program code stored in memory.Microprocessor is typically the allomeric function for controlling chip, this
Outside, microprocessor may include one or more modules, the interaction between microprocessor and other assemblies.
Microprocessor is communicated to connect with phaselocked loop, and divider controller circuit is provided in phaselocked loop.Since phaselocked loop can
It is spuious because non-thread sexual maladjustment generates with reduction, optimize the signal-to-noise ratio of chip system.Further, the frequency divider in phaselocked loop
Controller can select optimal divider controller circuit according to demand, and then reduce the power consumption of chip.For example, radio frequency core
Piece, including：Lan Yan, GSM etc., it is high to the power consumption requirements of chip when due to chip wirelessly transmit, it can
To select divider controller circuit least in power-consuming in the application, so that chip power-consumption is preferably minimized, extend corresponding letter
The operating time of number equipment.
In the present embodiment, microprocessor, memory and phaselocked loop are encapsulated in chip carrier.Chip further includes power supply group
Part, power supply module include that microprocessor, memory and phaselocked loop provide electric power for the various assemblies of chip.Power supply module can wrap
Include power-supply management system, one or more power supplys and other generate, manage and distribute electric power associated component with for chip.
In the exemplary embodiment, chip can also configure I/O interfaces, and I/O interfaces carry between microprocessor and peripheral interface module
Can also be the interface provided with memory for interface.
The relational terms of Wen Zhong, such as " first " and " second " or the like be used merely to by an entity or operation with it is another
One entity or operation distinguish, and without necessarily requiring or implying between these entities or operation, there are any this reality
Relationship or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to the packet of nonexcludability
Contain, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes
Other elements that are not explicitly listed, or further include for elements inherent to such a process, method, article, or device.
In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that including the element
Process, method, article or equipment in there is also other identical elements.
The same or similar parts between the embodiments can be referred to each other in present specification.Especially for locking phase
For ring and chip embodiment, since divider controller circuit therein is substantially similar to the implementation of divider controller circuit
Example, so description is fairly simple, related place is referring to the explanation in divider controller circuit embodiments.
Above-described the application embodiment does not constitute the restriction to the application protection domain.
Claims (8)
1. a kind of divider controller circuit, which is characterized in that including：
In conjunction with adder, the first signal input part of the combination adder inputs the first digital signal, the first number letter
It is INVENTIONPeriodic digital signals number within a preset period of time；
The signal input part of digital filter, the digital filter inputs the second digital signal, and second digital signal is
It is uniformly distributed aperiodic jittered digital signal, the signal output end of the digital filter connects the second of the combination adder
Signal input part；First digital signal is added in the combination adder with second digital signal and generates third number
Word signal, the third digital signal are aperiodicity jittered digital signal；
The signal output end of digital Delta-Sigma modulators (DDSM), the combination adder connects the signal of the DDSM
Input terminal, the third digital signal are input to the DDSM, the DDSM by the signal output end of the combination adder
A fractional frequency signal will be exported according to third digital signal, the fractional frequency signal is used to control the frequency divider of phaselocked loop.
2. divider controller circuit according to claim 1, which is characterized in that first digital signal and described the
The numerical digit of two digital signal is of same size.
3. divider controller circuit according to claim 1, which is characterized in that the digital filter and the combination
A numerical digit width amplifier is provided between adder, the numerical digit width amplifier is separately connected the letter of the digital filter
The second signal input terminal of number output end and the combination adder；
The numerical digit width of second digital signal is less than the numerical digit width of first digital signal, the numerical digit width amplification
Filtered second digital signal is carried out numerical digit width amplification by device, so that the numerical digit width etc. of second digital signal
In the numerical digit width of first digital signal.
4. a kind of divider controller circuit, which is characterized in that including：
The signal input part of digital filter, the digital filter inputs the 4th digital signal, and the 4th digital signal is
It is uniformly distributed aperiodic jittered digital signal；
DDSM, the DDSM are N rank MASH, and the EFM of N >=2, the first ranks of the N ranks MASH includes that left-hand adder and low level add
Musical instruments used in a Buddhist or Taoist mass, the carry output of the right-hand adder connect the carry input of the left-hand adder, the left-hand adder
The first signal input part input the 5th digital signal, the right-hand adder the first signal input part input the 6th number letter
Number, the 5th digital signal is preset time period periodically high-order digit signal, when the 6th digital signal is default
Between section periodically low order digit signal；
In conjunction with adder, the carry output and addition output end of the left-hand adder are all connected with the of the combination adder
The second signal input terminal of one signal input part, the combination adder connects the signal output end of the digital filter, institute
Second-order of the addition output end of the addition output end and the combination adder of stating right-hand adder with the N ranks MASH
EFM is connected.
5. divider controller circuit according to claim 4, which is characterized in that the EFM of the first ranks of the N ranks MASH is also
Including the first flip-flop element and the second flip-flop element, first flip-flop element is separately connected the right-hand adder
Addition output end and second signal input terminal with the right-hand adder, second flip-flop element are separately connected the knot
Close the addition output end of adder and the second signal input terminal with the left-hand adder.
6. divider controller circuit according to claim 4 or 5, which is characterized in that the carry of the combination adder
Output end connects the error concealment filter of the N ranks MASH.
7. a kind of phaselocked loop, which is characterized in that including frequency divider, phase discriminator, charge pump and divider controller, the frequency divider
Controller includes divider controller circuit as claimed in any one of claims 1 to 6, respectively to divider controller electricity
For periodic digital signal and it is uniformly distributed aperiodic jittered digital signal in road input preset time period, obtains aperiodicity
Jittered digital signal, is then output to frequency divider, and the frequency divider calculates defeated according to the aperiodicity jittered digital signal of reception
Enter the feedback signal of phase discriminator, the phase discriminator generates pulse control signal according to the feedback signal and is sent to charge pump.
8. a kind of chip, which is characterized in that including：
Microprocessor；
Memory for storing the microprocessor processes executable instruction；
Phaselocked loop as claimed in claim 7 is provided with frequency divider as claimed in any one of claims 1 to 6 in the phaselocked loop
Controller circuitry.
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