JP4445415B2 - Frequency modulator - Google Patents

Description

  The present invention relates to a frequency modulation device that modulates a frequency based on phase modulation data.

  A conventional synthesizer is shown in FIG. The synthesizer 10 includes a voltage controlled oscillator (hereinafter referred to as “VCO”) 11, a frequency divider 12, a phase comparator 13, a reference oscillator 14, and a loop filter 15.

  The VCO 11 provides a desired output frequency fo and also supplies an input to the frequency divider 12. The output of the frequency divider 12 supplies one input of the phase comparator 13 and the other input of the phase comparator 13 is supplied from the reference oscillator 14. The output of the phase comparator 13 is filtered by the loop filter 15 to remove unnecessary noise components.

  Next, the output of the loop filter 15 is fed back to the control input of the VCO 11, whereby the output frequency fo of the VCO 11 is adjusted to be a value of the frequency division ratio times the frequency of the reference oscillator 14. The reference frequency (fr) and the comparison frequency obtained by dividing the VCO output (fo) by 1 / M by the variable frequency divider are input to the phase comparator 13. The loop becomes stable in the state of fr = fo / M.

  Therefore, the output frequency (fo) becomes fo = fr · M, and the output frequency of the VCO can be varied by the frequency step Δf = fr by changing the frequency division ratio M.

  A conventional synthesizer is shown in FIG. The synthesizer 20 includes a voltage controlled oscillator (hereinafter referred to as “VCO”) 11, a frequency divider 12, a phase comparator 13, a reference oscillator 14, a loop filter 15, and an accumulator 21.

  The accumulator 21 includes an adder 22, a comparator 23, and a feedback logic unit 24. The adder 22 adds the numerator data K and the added feedback value from the feedback logic unit 24. The comparator 23 compares the output value of the adder 22 with the reference value, gives a carry output signal to the frequency divider 12, and gives the output value of the adder 22 to the feedback logic unit 24 to hold it.

  When the frequency division ratio of the frequency divider 12 is M, the accumulator 21 outputs an overflow (OVF) signal when the content becomes L or more, and sets the frequency division ratio of the frequency divider 12 to M + 1. If the accumulator 21 increases the content by K in one reference cycle, the content becomes αK after α cycles. Here, K is an integer having a relationship of α> 1, K ≧ 0, and L> K.

  When αK ≧ L, the accumulator 21 outputs an overflow signal, sets the frequency division ratio of the frequency divider 12 to M + 1, and at the same time sets the content to αK−L and increments again every cycle.

  Since the accumulator 21 overflows K times during the L cycle, the frequency division ratio M of the frequency divider 12 is M + 1 for K times and M for the remaining LK times during the L cycle (see FIG. 12). Therefore, the average frequency division ratio per L cycle is M + K / L.

  Therefore, in the synthesizer shown in FIG. 10, since the average frequency division ratio becomes M + K / L, the frequency step can be made fine. However, the configuration as shown in FIG. 10 has a problem that a high level of spurious is generated in the vicinity of the center frequency. This is because the frequency division ratio M changes with the L cycle as a basic period, and 1 / L and an integer multiple of frequency components appear in the output signal of the phase comparator, so that the output signal of the VCO is modulated. In order to reduce this spurious, it can be considered that the frequency division ratio M is frequently changed, the low frequency component of the change is lowered, and the high frequency component is raised. If the frequency component is high, it can be easily reduced by the cut-off frequency of the loop filter 15.

  As a conventional synthesizer, there is one shown in FIG. 11 (see Patent Document 1). The synthesizer 30 has a multistage accumulator digital network 31 instead of the accumulator 21 in the synthesizer shown in FIG.

The multistage accumulator digital network 31 includes a plurality of stages of accumulators 32, a plurality of digital delay networks 33, and an adder 34. In the synthesizer 30, the multistage accumulator digital network 31 processes molecular data including modulation information, generates a precise carry output signal, and supplies it to the frequency divider 12 to make a precise change in the division ratio. In the synthesizer 30 shown in FIG. 11, the carry output signals of the accumulators (integrator circuits) in the second and subsequent stages are input to the differentiating circuit and averaged to be 0, so that the frequency division ratio frequently changes as shown in FIG. become.
Japanese Patent Publication No. 5-502154

  However, since the conventional synthesizer 30 shown in FIG. 11 can process only molecular data within the range of 0 or more and less than 1, the phase exceeds the range of 0 or more and less than 1. There is a problem that it cannot be used as it is in a frequency modulation apparatus for processing modulation data.

  The present invention has been made in view of this point, and an object of the present invention is to provide a high-accuracy frequency modulation device having a precise synthesizer and a simple configuration.

Frequency modulation apparatus according to the present onset Ming, synthesizers and, input data calculation means and the integral part M of the phase modulation data K3 and carrier frequency data is input and outputs the integer part input data M1 and the phase modulation data K4, Integer part data delay means for delaying the integer part input data M1 from the first generation time to the second generation time of the clock signal and giving it to the synthesizer, the phase modulation data K4 and the first addition feedback value A phase modulation input data adder that adds and outputs an addition output signal, and the synthesizer selects an output signal frequency of an oscillator that can be controlled by receiving a digital number of a plurality of bits, and outputs the output signal frequency. Is divided by a loop divider, and the loop divider has a variable divisor controlled by a control input signal and is to be compared with a reference signal. A synthesizer for generating a back signal, means for generating said clock signal, a first adder for adding the fractional portion K and the first adding the feedback value of the carrier frequency data, the first a first comparator for generating a first carry output signal by comparing the output value with a predetermined value of the adder, the first latches the output signal of the comparator of the first adder feedback value first and a feedback logic unit, a first storage means for generating a first of said latched output signal and a first carry output signal upon the occurrence of said clock signal, said phase modulated input data to be a second adder for adding the value of the sum output signal output from the adder and the second adder feedback value, the by comparing the output value with a predetermined value of the second adder 2 No ki And a second comparator for generating a Lee output signal, and a second feedback logic unit for latching the output signal of said second comparator and said second adder feedback value, the clock signal Second storage means for generating the second carry output signal upon a second occurrence, means for delaying the first carry output signal until the second occurrence of the clock signal, and the second carry A means for differentiating the output signal, the integer part input data M1 delayed by the integer part data delay means, the delayed first carry output signal, and the differentiated second carry output signal; Means for generating the control input signal, and the input data calculation means sets M1 = M−1 and K4 = K3 + 1 when K3 <0, and M1 = when 0 ≦ K3 <1. M, When K4 = K3 and 1 ≦ K3, a configuration is adopted in which M1 = M + 1 and K4 = K3-1.

  According to this configuration, M1 = M−1 and K4 = K3 + 1 when K3 <0 in response to the phase modulation data K3 and the integer part M of the carrier frequency data, and M1 when 0 ≦ K3 <1. = M, K4 = K3, and if 1 ≦ K3, then M1 = M + 1, K4 = K3-1, that is, a value that is greater than or equal to 0 and less than 1 in the phase modulation data K3 To generate integer part input data M1 and phase modulation data K4 and supply the phase modulation data K4 to the phase modulation input data adder. The phase modulation input data adder and the phase modulation data K4 The integrated value of the output signal latched by the first feedback logic unit of the synthesizer is added to generate an input data addition output signal, which is supplied to the second adder of the synthesizer It has a precise synthesizer, and can provide a frequency modulation apparatus of the high precision with a simple configuration. Further, according to this configuration, a differentiator for differentiating the phase modulation data to generate the differential phase modulation data is not required, so that the configuration can be simplified compared to the frequency modulation device according to the first aspect of the present invention. it can.

A frequency modulation apparatus according to the present invention is a frequency modulation apparatus used when phase modulation data is greater than −0.5 and less than 0.5, and includes a synthesizer and a predetermined fixed value for the value of the phase modulation data. And a phase modulation input data adder that adds the modulation input data K5 and the first addition feedback value and outputs an addition output signal. The synthesizer selects an output signal frequency of an oscillator that can be controlled in response to a digital number of a plurality of bits, divides the output signal frequency by a loop divider, and the loop divider controls a control input signal. A synthesizer for generating a feedback signal to be compared with a reference signal having a variable divisor controlled by means of: a means for generating a clock signal; A first adder for adding the fractional part K of the frequency data and the first addition feedback value, and comparing the output value of the first adder with a reference value to generate a first carry output signal first comparator, said first adder feedback value by latching an output signal of said first comparator for outputting an output value of the first adder to the first feedback logic unit as well as the said first and a feedback logic unit, a first storage means for generating a first of said latched output signal and a first carry output signal upon the occurrence of said clock signal, said phase modulated input data A second adder for adding the value of the addition output signal output from the adder and a second addition feedback value, and comparing the output value of the second adder with a predetermined numerical value No cat A second comparator that generates an output signal, and a second feedback logic unit that latches the output signal of the second comparator to obtain the second added feedback value, Second storage means for generating the second carry output signal upon a second occurrence, means for delaying the first carry output signal until the second occurrence of the clock signal, and the second carry A means for differentiating an output signal; an integer part input data M of the carrier frequency data; the delayed first carry output signal; and the differentiated second carry output signal to combine the control input signal. And the phase modulation input data adder adds the modulation input data K5 and the value of the output signal latched by the first feedback logic unit. It generates a pre Symbol pressurized calculated force signal by a configuration to be given to the second adder.

  According to this configuration, the input data calculation means for generating the modulation input data K5 by adding a predetermined fixed value to the value of the phase modulation data, and the phase modulation input data adder for receiving the phase modulation data K5 are provided. The phase modulation input data adder adds the phase modulation data K5 and the value of the output signal latched by the first feedback logic unit of the synthesizer to generate an input data addition output signal to generate the input data of the synthesizer. Since it is given to the second adder, a high-accuracy frequency modulation device having a precise synthesizer and a simple configuration can be provided. Further, according to this configuration, it is possible to process phase modulation data that is in the range of 0 or more and less than 1 by adding a predetermined fixed value.

The frequency modulation device according to the present invention is a frequency modulation device used when the phase modulation data is greater than 0 and less than 1, and adds the synthesizer, the phase modulation data, and the first addition feedback value, A phase modulation input data adder that outputs a summed output signal, and the synthesizer selects a controllable output signal frequency of an oscillator that receives a digital number of a plurality of bits, and divides the output signal frequency into a loop. Means for generating a clock signal, wherein the synthesizer generates a feedback signal to be compared with a reference signal having a variable divisor controlled by a control input signal; A first adder for adding the fractional part K of the carrier frequency data and the first addition feedback value; and an output value of the first adder. A first comparator for outputting an output value of said first adder with generating the first carry output signal is compared with the constant numerical value to the first feedback logic unit, said first comparator and a first feedback logic unit to said first adder feedback value by latching an output signal of the first occurrence in the latched output signal and a first carry output of said clock signal Means for generating a signal, a second adder for adding the value of the summed output signal output from the phase modulation input data adder and a second summed feedback value, and an output of the second adder A second comparator that generates a second carry output signal by comparing the value with a predetermined numerical value, and a second comparator that latches the output signal of the second comparator to provide the second added feedback value. A feedback logic unit, and means for generating the second carry output signal upon the second generation of the clock signal; and delaying the first carry output signal until the second generation of the clock signal Means for differentiating the second carry output signal; integer part input data M of the carrier frequency data; the delayed first carry output signal; and the differentiated second carry output signal. And means for generating the control input signal, wherein the phase modulation input data adder adds the phase modulation data and the value of the output signal latched by the first feedback logic unit. Then, a configuration is adopted in which the addition output signal is generated and supplied to the second adder.

  According to this configuration, the phase modulation input data adder that receives the phase modulation data is provided, and the phase modulation input data adder receives the phase modulation data and the output signal latched by the first feedback logic unit of the synthesizer. A high-accuracy frequency modulation device having a precise synthesizer and a simple configuration is provided for adding an input value to generate an input data addition output signal and supplying it to the second adder of the synthesizer. be able to. Further, according to this configuration, it is possible to process phase modulation data within a range of 0 or more and less than 1.

  According to the present invention, it is possible to provide a high-accuracy frequency modulation device having a precise synthesizer and a simple configuration.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a frequency modulation apparatus according to Embodiment 1 of the present invention.

  As shown in FIG. 1, a frequency modulation apparatus 100 according to Embodiment 1 of the present invention includes a synthesizer 101, a differentiator 102, an adder 103, an input data operation unit 104, and an integer part data delay unit 105. .

  The differentiator 102 differentiates the phase modulation data to generate differential phase modulation data (frequency modulation data). The adder 103 adds the differential phase modulation data from the differentiator 102 and the decimal part K of the carrier frequency data to generate an added decimal part K1. The input data calculation unit 104 receives the added fractional part K1 from the adder 103 and the integer part M of the carrier frequency data, generates integer part input data M1 and fractional part input data K2, and gives them to the synthesizer 101. The integer part data delay unit 105 delays the integer part input data M <b> 1 from the input data calculation unit 104 and gives the delayed data to the synthesizer 101. The integer part data delay unit 105 includes three delay elements 1051, 1052, and 1053.

  The synthesizer 101 includes a voltage controlled oscillator (VCO) 106, a variable frequency divider 107, a phase comparator 108, a reference oscillator 109, a loop filter 110, and a multistage accumulator digital network 111. The multistage accumulator digital network 111 constitutes a delta sigma modulation device.

  The VCO 106 provides a high-frequency phase modulation signal having a desired output frequency fo, and supplies an input to the frequency divider 107. The output of the frequency divider 107 provides one input of the phase comparator 108, and the other input of the phase comparator 108 is supplied from the reference oscillator 109. The output of the phase comparator 108 is filtered by the loop filter 110 to remove unwanted noise components.

  Next, the output of the loop filter 110 is fed back to the control input of the VOC 106 so that the VCO 106 adjusts its output frequency fo to be a value obtained by multiplying the frequency of the reference oscillator 109 by the digital divider 107. To do.

  The multistage accumulator digital network 111 is for giving a control signal for controlling the frequency division ratio to the variable frequency divider 107. The multistage accumulator digital network 111 includes a plurality of stages of accumulators 112, 113, 114, 115, a plurality of digital delay networks 116, 117, 118, 119 and an adder 120.

  The accumulator 112 includes an adder 1121, a comparator 1122, and a feedback logic unit 1123. The accumulator 113 also includes an adder 1131, a comparator 1132, and a feedback logic unit 1133. Also. The accumulators 114 and 115 have the same configuration as the accumulators 112 and 113.

  The digital delay network 116 includes three delay elements 1161, 1162, and 1163. The digital delay network 117 includes three delay elements 1171, 1172, and 1173. The digital delay network 118 includes three delay elements 1181, 1182 and 1183. The digital delay network 119 includes three delay elements 1191, 1192, and 1193.

  In the preferred embodiment, the divider ratio N of the divider 107 varies with a periodic sequence and the output frequency fo of the VCO 106 can be adjusted in frequency steps equal to a fraction of the frequency of the reference oscillator 109. This periodic sequence is generated by the multistage accumulator digital network 111. A multi-stage accumulator digital network 111 of four accumulators is shown in FIG.

  The decimal part input data K2 from the input data calculation unit 104 is directly applied to the adder 1121 of the accumulator 112. The adder 1121 adds the decimal part input data K2 and the first addition feedback value. The comparator 1122 compares the output value of the adder 1121 with a predetermined numerical value to generate a first carry output signal, and provides the output value of the adder 1121 to the feedback logic unit 1123. The feedback logic unit 1123 latches (holds) the output value (output signal) of the adder 1121.

  The data output from the accumulator 112 is processed by the comparator 1122 and then retrieved at the output of the feedback logic unit 1123. After the clock input signal extracted from the frequency divider 107 clocks the accumulator 112, the data output described above can be used.

  Data appearing from one accumulator to the next accumulator is only transferred to the next accumulator in the string during one clock cycle, thereby avoiding the problem of ripple through all accumulators within one clock pulse. it can.

  The contents of the next lower accumulator are supplied to each accumulator prior to the first accumulator. Each accumulator digitally integrates the contents of the next lower accumulator with the first accumulator 112 and executes digital integration of the fractional part input data K2. The second accumulator 113 performs double integration of the fractional part input data K2, the third accumulator 114 performs triple integration of the fractional part input data K2, and the fourth accumulator 115 performs the decimal part input data K2. Perform quadruple integration.

  The output of each accumulator is a carry output signal, that is, an overflow output signal. For the first accumulator 112, this output indicates that the VCO output frequency fo has obtained a 360 degree phase error relative to the frequency of the signal output from the reference oscillator 109. To correct this, the divider ratio of divider 107 is increased by one integer for the next clock interval, and the internal data of accumulator 112 is decreased by its capacity. This action eliminates one cycle of the output frequency fo from the input of the phase comparator 108, and therefore a 360 degree phase correction at the output of the VCO 106.

  This correction occurs only at the point where the output frequency fo achieves a 360 degree phase error without the loop filter 110. Such a condition results in a sawtooth waveform at the output of the phase comparator 108, which must then be filtered by the loop filter 110. The average value of the sawtooth waveform is a correct control signal for selecting a frequency that is a fractional increment interval of the reference frequency output from the reference oscillator 109.

  However, the internal data of the first accumulator 112 indicates an intermediate phase error. Higher accumulators are included to act on the internal data of the first accumulator 112, thereby providing an intermediate correction to the phase error so that the sawtooth waveform can be subdivided in frequency, Therefore, the noise output at the fundamental frequency of the original sawtooth waveform can be reduced.

  The output of the higher accumulator is fed through digital delay networks 116, 117, 118, 119 that perform a derivative operation on the carry output signal. Since these carry output signals of the accumulator are digital integrals of the molecular data input, there is a higher order correction for the desired phase.

  For example, the carry output signal of the second accumulator 113 is applied to the digital delay network 117, where the carry output signal is fed to the normal delay elements 1171 and 1172 and the delay element 1173 before being supplied to the normal digital adder 120. Delayed by.

  In the adder 120, the delay output of the second accumulator 113 is added to the negative value of the previous value obtained from the output of the normal delay element 1173. This is a first-order derivative in a digital sense. Since the output of the second accumulator 113 is the second integral of the fractional part input data K2, the net output of this configuration is a quadratic phase correction of the fractional frequency offset (the fractional part input data K2 phase derived). Note that it is a function frequency offset).

  The carry output signal of the third accumulator 114 is applied to the digital delay network 118, where the carry output signal is delayed by the delay element 1181 and added to the sum of the double value of the previous negative value and the previous value. . These previous value and previous value are obtained from the outputs of the delay elements 1182 and 1183, respectively. This corresponds to the second-order digital derivative. Since the output of the third accumulator 114 represents a third integral of the fractional input data K2, these overall effects are a third order correction to the phase of the fractional frequency offset.

This technique can be performed for the desired order of correction by adding more accumulator portions to the multi-stage accumulator digital network 111. The coefficient of addition of each sequence corresponds to the factor in the expansion of (1-z ⁻¹ ) ^X , where X is the order of the accumulator under consideration}. It is also possible to introduce other coefficients such that the sum of the coefficients for the first accumulator is 1 and the sum of the coefficients for all other high-order accumulators is 0. However, any selection other than the coefficients described above will result in performance below the optimal noise removal performance.

  For example, the carry-out output sequence of the fourth accumulator 115 applied to the digital delay network 119 is delayed by three cycles from the carry-out output sequence of the first accumulator 112, and the carry-out output sequence of the third accumulator 114 is the first The carry-out output sequence of the first accumulator 112 is delayed by two cycles, and the carry-out output sequence of the second accumulator 113 is delayed by one cycle from the carry-out output sequence of the first accumulator 112. In order to align these sequences in time, the output of the first accumulator 112 is delayed three times by delay elements 1161, 1162, and 1163, and the output of the second accumulator 113 is delayed twice by delay elements 1171 and 1172. The output of the third accumulator 114 is delayed once by the delay element 1181. All other delay elements of the digital delay networks 116, 117, 118, 119 are associated with the discriminant differentiation process. In this case, the integer part input data M1 from the input data calculation unit 104 is delayed three times by the three delay elements 1051, 1052, and 1053 of the integer part data delay unit 105.

  Next, the principle of operation of the frequency modulation apparatus 100 according to Embodiment 1 of the present invention will be described in detail.

  When the modulation output frequency is fo + Δf (t), the division ratio of the variable frequency divider 107 is M, the fractional part of the carrier frequency data is K, and the phase modulation signal is ΔK (t), the modulation output frequency fo + Δf (t ) Is represented by the following formula 1.

ΔＫ（ｔ）は、変調信号でありプラス又はマイナスの値で入力されるためアキュムレータ１１２に入力する小数部入力データＫ２がプラスオーバーフロー又はマイナスオーバーフローしてしまう場合がある。そのためアキュムレータ１１２に入力する前に入力データ演算部１０４が設けられることによりオーバーフロー対策が実施される。

Since ΔK (t) is a modulation signal and is input as a plus or minus value, the decimal part input data K2 input to the accumulator 112 may overflow plus or minus. Therefore, an overflow countermeasure is implemented by providing the input data calculation unit 104 before input to the accumulator 112.

  The input data calculation unit 104 sets M1 = M−1 and K2 = K1 + 1 when K1 <0, sets M1 = M and K2 = K1 when 0 ≦ K1 <1, and satisfies 1 ≦ K1. In this case, M1 = M + 1, K2 = K1-1, K2 is input to the accumulator 112, and M1 is input to the adder 120 via the integer data delay unit 105.

  As described above, in the first embodiment of the present invention, the differentiator 102 that differentiates the phase modulation data to generate differential phase modulation data, and the differential phase modulation data and the fractional part K of the carrier frequency data are added. In response to the adder 103 for generating the added fractional part K1, the added decimal part K1 and the integer part M of the carrier frequency data, the integer part input data M1 and the fractional part input data K2 are generated to generate the fractional part input data K2. Is input to the adder 1121 of the synthesizer 101, and the integer part of the integer part input data M1 is supplied to the adder 120 of the synthesizer 101 after being delayed from the first generation to the second generation of the clock signal. And when the input data operation unit 104 is K1 <0, M1 = M−1 and K2 = K1 + 1, and 0 ≦ K1 < Since M1 = M and K2 = K1 in the case of 1 and M1 = M + 1 and K2 = K1-1 in the case of 1 ≦ K1, the precise synthesizer 101 is provided and the configuration is simple. A highly accurate frequency modulation device 100 can be provided.

(Embodiment 2)
Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 2 is a block diagram showing the configuration of the frequency modulation apparatus according to Embodiment 2 of the present invention. In the second embodiment of the present invention, the same components as those in the first embodiment of the present invention are designated by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 2, the frequency modulation apparatus 200 according to the second embodiment of the present invention includes a synthesizer 101, an input data calculation unit 201, an integer data delay unit 105, and a phase modulation input data adder 202. .

  The frequency modulation apparatus 200 according to the second embodiment of the present invention has a configuration in which the differentiator 102 in the first embodiment of the present invention is reduced.

  The synthesizer 101 is the same as that of the first embodiment of the present invention. The input data calculation unit 201 receives the phase modulation data K3 and the integer part M of the carrier frequency data, and generates integer part input data M1 and phase modulation data K4. The integer part data delay unit 105 is the same as that of the first embodiment of the present invention. The phase modulation input data adder 202 receives the phase modulation data K4 directly, adds the phase modulation data K4 and the value of the output signal latched in the feedback logic unit 1123, and adds the output value to the adder of the accumulator 113. 1131.

  Next, the reason why the frequency modulator 200 according to Embodiment 2 of the present invention does not require the differentiator 102 will be described.

  The reason why the differentiation circuit 102 of FIG. 1 can be reduced with reference to the accumulator Z conversion model of FIG. 3 will be described below.

  FIG. 3 is a diagram showing the structure of the accumulator in a Z conversion model. X is input data, and Y is a carry output signal. The integrator outputs a carry output signal when the integration result exceeds a certain value. The output signal Y, which is equivalent to passing through a 1-bit quantizer, is expressed by the following equations 2 and 3.

出力信号Ｙは、量子化ノイズＱが微分されており低周波域ほどノイズが減衰していることになる。

In the output signal Y, the quantization noise Q is differentiated, and the noise is attenuated in the lower frequency range.

  Next, FIG. 4 shows a Z conversion model of a two-stage accumulator. When the phase modulation signal K is input to the two-stage accumulator and calculation is performed in the same manner as described above, the output signal Y is obtained by the following equations 4 to 12.

出力信号Ｙは、量子化ノイズは２次微分され位相変調データＫが１次微分される。したがって、図１に示す位相変調データΔＫ（ｔ）の入力を受ける微分回路が削除される。

In the output signal Y, the quantization noise is second-order differentiated, and the phase modulation data K is first-order differentiated. Therefore, the differentiation circuit that receives the input of the phase modulation data ΔK (t) shown in FIG. 1 is deleted.

  Further, when phase modulation data is input to the input of the three-stage accumulator, the input phase modulation data needs to be first-order integrated and input to the four-stage accumulator.

  As described above, in the second embodiment of the present invention, the input data calculation unit 201 that receives the phase modulation data K3 and the integer part M of the carrier frequency data and generates the integer part input data M1 and the phase modulation data K4, An integer part data delay unit 105 that delays the integer part input data M1 from the first generation time to the second generation time of the clock signal and applies it to the adder 120 of the synthesizer 101, and phase modulation input data that receives the phase modulation data K4 An adder 202, and the input data calculation unit 201 sets M1 = M−1 and K4 = K3 + 1 when K3 <0, and M1 = M and K4 = K3 when 0 ≦ K3 <1. When 1 ≦ K3, M1 = M + 1 and K4 = K3-1, and the phase modulation input data adder 202 is connected to the phase modulation data K4 and the first feedback logic. In order to add the integrated value of the output signal latched by the unit 1121 to generate the input data addition output signal and supply it to the second adder 1131, it has a precise synthesizer 101 and has a simple configuration It is possible to provide a highly accurate frequency modulation device 200 having

(Embodiment 3)
Next, Embodiment 3 of the present invention will be described in detail with reference to the drawings.

  FIG. 5 is a block diagram showing a configuration of a frequency modulation apparatus according to Embodiment 3 of the present invention. In the third embodiment of the present invention, the same components as those in the first embodiment of the present invention are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 5, the frequency modulation apparatus 500 according to the third embodiment of the present invention includes a synthesizer 101, an input data calculation unit 501, and a phase modulation input data adder 502. The frequency modulation apparatus 500 according to the third embodiment of the present invention is applied when the phase modulation data ΔK is −0.5 <ΔK <0.5.

  The synthesizer 101 is the same as that of the first embodiment of the present invention. The input data arithmetic unit 501 adds 0.5 to the value of the phase modulation data (converts to 0 <ΔK <1) to generate modulation input data K5. The phase modulation input data adder 502 receives the phase modulation data K5, adds the phase modulation data K5 and the value of the output signal latched in the feedback logic unit 1123, and adds the output value to the adder 1131 of the accumulator 113. To give.

  The third embodiment of the present invention is applied when the absolute value of the phase modulation data ΔK is larger than 0 and smaller than 1. In this case, if the predetermined fixed value is L, it is necessary to input a predetermined fixed value L such that 0 <(ΔK + L) <1 to the input data calculation unit 501.

  As described above, in the third embodiment of the present invention, the input data calculation unit 501 for generating the modulation input data K5 by adding 0.5 to the value of the phase modulation data, and the phase modulation input for receiving the phase modulation data K5 A data adder 502, and the phase modulation input data adder 502 adds the phase modulation data K5 and the value of the output signal latched by the first feedback logic unit 1121 to obtain an input data addition output signal. Since it is generated and supplied to the second adder 1131, it is possible to provide a high-accuracy frequency modulation device 500 having a precise synthesizer 101 and a simple configuration.

(Embodiment 4)
Next, a fourth embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 6 is a block diagram showing a configuration of a frequency modulation apparatus according to Embodiment 4 of the present invention. In the fourth embodiment of the present invention, the same components as those in the first embodiment of the present invention are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 6, the frequency modulation apparatus 600 according to the fourth embodiment of the present invention includes a synthesizer 101 and a phase modulation input data adder 601. Frequency modulation apparatus 600 according to Embodiment 4 of the present invention is applied when phase modulation data ΔK is 0 <ΔK <1.

  The phase modulation input data adder 601 adds the phase modulation data ΔK and the value of the output signal latched in the feedback logic unit 1123, and gives the output value to the adder 1131 of the accumulator 113.

  As described above, the fourth embodiment of the present invention includes the phase modulation input data adder 601 that receives the phase modulation data, and the phase modulation input data adder 601 includes the phase modulation data and the first feedback logic unit. In order to add the value of the output signal latched by 1121 to generate an input data addition output signal and give it to the second adder 1131, it has a precise synthesizer 101 and has a simple structure Frequency modulation apparatus 600 can be provided.

(Embodiment 5)
Next, a fifth embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 7 is a block diagram showing a configuration of a transmission apparatus according to Embodiment 5 of the present invention. In the fifth embodiment of the present invention, the same components as those in the first embodiment of the present invention are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 7, a transmission apparatus 700 according to Embodiment 5 of the present invention includes an amplitude phase separation unit 701, an amplitude modulation data amplifier 702, a frequency modulation apparatus 100, a high frequency power amplifier 703, a carrier signal generation unit 704, data An integer part generator 705 and a data fraction part generator 706 are provided.

  The amplitude phase separation unit 701 receives the baseband modulation signal S101 and separates it into amplitude modulation data S102 and phase modulation data S104. The amplitude modulation data amplifier 702 receives and amplifies the amplitude modulation data S102 from the amplitude phase separation unit 701, and supplies the amplitude modulation data S102 to the high frequency power amplifier 703 as the power supply voltage S103.

  The carrier signal generation unit 704 generates a carrier signal S107 and supplies it to the data integer part generation unit 705 and the data fractional part generation unit 706. The data integer part generation unit 705 receives the carrier signal S107 from the carrier signal generation unit 704, generates an integer part M of carrier frequency data, and supplies the generated integer part M to the frequency modulation apparatus 100. The data fractional part generation unit 706 receives the carrier signal S107 from the carrier signal generation part 704, generates a fractional part K of the carrier frequency data, and gives it to the frequency modulation apparatus 100.

  The frequency modulation apparatus 100 includes a phase modulation data S104 from the amplitude / phase separation unit 701, an integer part M of carrier frequency data from the data integer part generation unit 705, and a fractional part of carrier frequency data from the data fractional part generation unit 706. In response to K, as described above, the high-frequency phase modulation signal S105 having the output frequency fo is generated and applied to the high-frequency power amplifier 703. The high frequency power amplifier 703 amplifies the high frequency phase modulation signal S105 in accordance with the power supply voltage S103 from the amplitude modulation data amplifier 702, and supplies the amplified output signal S106 to the antenna. This antenna receives the transmission output signal S106 and generates and transmits a wireless transmission signal.

  Note that transmitting apparatus 700 according to Embodiment 5 of the present invention includes frequency modulation apparatus 200, frequency modulation apparatus 500, or frequency modulation apparatus 600 described in each of the above-described embodiments instead of frequency modulation apparatus 100. It may be configured.

  According to the above configuration, since the high-precision frequency modulation device of the present invention having a precise synthesizer and a simple configuration is provided, a high-quality radio transmission signal can be generated. A high-quality and low-cost transmitter can be realized.

(Embodiment 6)
Next, a sixth embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 8 is a block diagram showing a configuration of a wireless communication device according to Embodiment 6 of the present invention. In the sixth embodiment of the present invention, the same components as those in the fifth embodiment of the present invention are designated by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 8, radio communication apparatus 800 according to Embodiment 6 of the present invention includes antenna 801, transmission / reception switching section 802, transmission apparatus 700, and reception apparatus 803.

  Transmitting apparatus 700 provides transmission output signal S106 to antenna 801 via transmission / reception switching section 802. The antenna 801 receives the transmission output signal S106 from the transmission device 700 via the transmission / reception switching unit 802, generates a wireless transmission signal, and transmits it.

  The antenna 801 receives a wireless transmission signal from the partner wireless communication device, generates a reception signal, and provides the reception device 803 via the transmission / reception switching unit 802.

  According to the above configuration, a high-quality radio transmission signal can be generated because the transmitter includes the precise frequency synthesizer of the present invention having a precise synthesizer and a simple configuration. As a result, a high-quality and low-cost wireless communication device can be realized.

  The present invention is useful for a frequency modulation apparatus having a precise synthesizer.

1 is a block diagram showing a configuration of a frequency modulation apparatus according to Embodiment 1 of the present invention. Block diagram showing the configuration of a frequency modulation apparatus according to Embodiment 2 of the present invention The figure which shows the accumulator Z conversion model for demonstrating operation | movement of the frequency modulation apparatus which concerns on Embodiment 2 of this invention. The figure which shows the other accumulator Z conversion model for demonstrating operation | movement of the frequency modulation apparatus which concerns on Embodiment 2 of this invention. Block diagram showing the configuration of a frequency modulation apparatus according to Embodiment 3 of the present invention The block diagram which shows the structure of the frequency modulation apparatus which concerns on Embodiment 4 of this invention. The block diagram which shows the structure of the transmitter which concerns on Embodiment 5 of this invention. Block diagram showing a configuration of a wireless communication device according to a sixth embodiment of the present invention Block diagram showing the configuration of a conventional synthesizer Block diagram showing the configuration of another conventional synthesizer Block diagram showing the configuration of another conventional synthesizer The figure for demonstrating operation | movement of the conventional synthesizer shown in FIG. The figure for demonstrating operation | movement of the other conventional synthesizer shown in FIG.

Explanation of symbols

100, 200, 500, 600 Frequency modulator 101 Synthesizer 102 Differentiator 103 Adder 104, 201, 501 Input data calculation unit 105 Integer data delay unit 202, 502, 601 Phase modulation input data adder 106 Voltage controlled oscillator (VCO) )
107 frequency divider 108 phase comparator 109 reference oscillator 110 loop filter 111 multistage accumulator digital network 112, 113, 114, 115 accumulator 116, 117, 118, 119 digital delay network 1051-1053, 1161-1163, 1171-1173, 1181 1183, 1191 to 1193 Delay element 1121, 1131 Adder 1122, 1132 Comparator 1123, 1133 Feedback logic unit 700 Transmitting device 701 Amplitude phase separation unit 702 Amplitude modulation data amplifier 703 High frequency power amplifier 704 Carrier signal generation unit 705 Data integer unit Generation unit 706 Data fractional part generation unit 800 Wireless communication device 801 Antenna 802 Transmission / reception switching unit 803 Receiver

Claims (5)

A synthesizer; input data calculation means for inputting the integer part M of the phase modulation data K3 and the carrier frequency data and outputting the integer part input data M1 and the phase modulation data K4; and the integer part input data M1 for the clock signal. A phase for delaying from the first occurrence time to the second occurrence time and adding the integer part data delay means to the synthesizer, the phase modulation data K4 and the first addition feedback value, and outputting an addition output signal A modulation input data adder,
The synthesizer
A variable divisor in which an output signal frequency of an oscillator that can be controlled in response to a digital number of bits is selected, the output signal frequency is divided by a loop divider, and the loop divider is controlled by a control input signal A synthesizer for generating a feedback signal to be compared with a reference signal,
Means for generating the clock signal;
A first adder for adding the fractional part K of the carrier frequency data and the first addition feedback value, and a first carry output by comparing the output value of the first adder with a predetermined numerical value. A first comparator that generates a signal; and a first feedback logic unit that latches an output signal of the first comparator to obtain the first addition feedback value, First storage means for generating the latched output signal and the first carry output signal upon occurrence of
A second adder for adding a value of the addition output signal output from the phase modulation input data adder and a second addition feedback value; an output value of the second adder and a predetermined numerical value; A second comparator for comparing and generating a second carry output signal; and a second feedback logic unit for latching the output signal of the second comparator to obtain the second added feedback value. And second storage means for generating the second carry output signal upon the second generation of the clock signal;
Means for delaying the first carry output signal until a second occurrence of the clock signal;
Means for differentiating the second carry output signal;
Means for combining the integer part input data M1 delayed by the integer part data delay means, the delayed first carry output signal, and the differentiated second carry output signal to generate the control input signal. When,
Comprising
The input data calculation means includes
M1 = M-1 and K4 = K3 + 1 when K3 <0, M1 = M, K4 = K3 when 0 ≦ K3 <1, and M1 = M + 1, K4 when 1 ≦ K3 = K3-1, a frequency modulation device characterized by that. A frequency modulation device used when the phase modulation data is greater than -0.5 and less than 0.5,
A synthesizer; input data calculation means for generating modulation input data K5 by adding a predetermined fixed value to the value of the phase modulation data; and adding the modulation input data K5 and the first addition feedback value to obtain an addition output A phase modulation input data adder for outputting a signal,
The synthesizer
A variable divisor in which an output signal frequency of an oscillator that can be controlled in response to a digital number of bits is selected, the output signal frequency is divided by a loop divider, and the loop divider is controlled by a control input signal A synthesizer for generating a feedback signal to be compared with a reference signal,
Means for generating a clock signal;
A first adder for adding the fractional part K of the carrier frequency data and the first addition feedback value, and comparing the output value of the first adder with a reference value to obtain a first carry output signal. a first comparator for outputting an output value of the first adder to the first feedback logic unit as well as generating said first adder feedback value by latching an output signal of said first comparator said first and a feedback logic unit, a first storage means for generating a first output signal the latched upon the occurrence and the first carry output signal of the clock signal to,
A second adder for adding a value of the addition output signal output from the phase modulation input data adder and a second addition feedback value; an output value of the second adder and a predetermined numerical value; A second comparator for comparing and generating a second carry output signal; and a second feedback logic unit for latching the output signal of the second comparator to obtain the second added feedback value. And second storage means for generating the second carry output signal upon the second generation of the clock signal;
Means for delaying the first carry output signal until a second occurrence of the clock signal;
Means for differentiating the second carry output signal;
Means for combining the integer part input data M of the carrier frequency data, the delayed first carry output signal and the differentiated second carry output signal to generate the control input signal;
Comprising
The phase modulation input data adder is
Characterized in providing the generated pre Symbol pressurized calculated force signal by adding the value of the latch output signal to the second adder by the modulated input data K5 and the first feedback logic unit Frequency modulation device. A frequency modulation device used when the phase modulation data is greater than 0 and less than 1,
A synthesizer, and a phase modulation input data adder that adds the phase modulation data and the first addition feedback value and outputs an addition output signal;
The synthesizer
A variable divisor in which an output signal frequency of an oscillator that can be controlled in response to a digital number of bits is selected, the output signal frequency is divided by a loop divider, and the loop divider is controlled by a control input signal A synthesizer for generating a feedback signal to be compared with a reference signal,
Means for generating a clock signal;
A first adder for adding the fractional part K of the carrier frequency data and the first addition feedback value; a first carry output signal by comparing the output value of the first adder with a predetermined numerical value; a first comparator for outputting an output value of the first adder to the first feedback logic unit as well as generating said first adder fed back by latching the output signal of said first comparator means and a first feedback logic unit to a value, to generate a first said latch output signal and a first carry output signal upon the occurrence of said clock signal,
A second adder for adding a value of the addition output signal output from the phase modulation input data adder and a second addition feedback value; an output value of the second adder and a predetermined numerical value; A second comparator for comparing and generating a second carry output signal; and a second feedback logic unit for latching the output signal of the second comparator to obtain the second added feedback value. And means for generating the second carry output signal upon the second generation of the clock signal;
Means for delaying the first carry output signal until a second occurrence of the clock signal;
Means for differentiating the second carry output signal;
Means for combining the integer part input data M of the carrier frequency data, the delayed first carry output signal and the differentiated second carry output signal to generate the control input signal;
Comprising
The phase modulation input data adder is
A frequency modulation device characterized in that the phase modulation data and the value of the output signal latched by the first feedback logic unit are added to generate the added output signal, which is supplied to the second adder. .   A transmission apparatus comprising the frequency modulation apparatus according to claim 1.   A wireless communication device comprising the transmission device according to claim 4.

Images