WO2008032510A1 - Process for producing semiconductor device - Google Patents

Process for producing semiconductor device Download PDF

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Publication number
WO2008032510A1
WO2008032510A1 PCT/JP2007/065418 JP2007065418W WO2008032510A1 WO 2008032510 A1 WO2008032510 A1 WO 2008032510A1 JP 2007065418 W JP2007065418 W JP 2007065418W WO 2008032510 A1 WO2008032510 A1 WO 2008032510A1
Authority
WO
WIPO (PCT)
Prior art keywords
adhesive layer
chip
semiconductor device
wiring board
adhesive
Prior art date
Application number
PCT/JP2007/065418
Other languages
French (fr)
Japanese (ja)
Inventor
Osamu Yamazaki
Isao Ichikawa
Naoya Saiki
Original Assignee
Lintec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lintec Corporation filed Critical Lintec Corporation
Priority to EP07792087A priority Critical patent/EP2063465A4/en
Priority to KR1020117025251A priority patent/KR101299773B1/en
Publication of WO2008032510A1 publication Critical patent/WO2008032510A1/en

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    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device. More specifically, the present invention relates to a method of manufacturing a semiconductor device by heating a wiring board on which a chip and an uncured adhesive layer are laminated, and curing the uncured adhesive layer.
  • a semiconductor device is manufactured through a die bonding process (die bonding process) between a chip and a wiring board using a liquid or film thermosetting adhesive, followed by a wire bonding process and a molding process.
  • die bonding process die bonding process
  • void 5 is present in the adhesive
  • void 6 is present at the adhesive chip side or wiring board side interface.
  • Figure 4 These voids do not disappear after the die bonding process (Fig. 4).
  • a liquid adhesive is used, voids are often found in the adhesive, and when a film-like adhesive is used, the adhesive force is insufficient and the adherence to the unevenness of the adherend surface is followed. Voids often exist at the interface due to lack of properties.
  • Patent Document 1 International Publication No. 2005/004216 Pamphlet
  • an object of the present invention is to provide a method that can easily manufacture a semiconductor device without voids, which does not depend on the substrate design, and in this case, the adhesive is not rolled up.
  • An object of the present invention is to provide a method capable of manufacturing a semiconductor device.
  • a method for manufacturing a semiconductor device according to the present invention includes:
  • a wiring board in which a chip and an uncured adhesive layer are laminated (wiring board in which a chip is laminated through an uncured adhesive layer) is heated to cure the uncured adhesive layer and to make a half
  • a method of manufacturing a conductor device comprising:
  • thermosetting is performed by heating the wiring substrate in which the chip and the uncured adhesive layer are laminated while the pressurized state in the static pressure pressing process is performed, thereby curing the uncured adhesive layer. It is preferable to further include a step.
  • the normal condition can be applied and the subsequent static pressure application can be performed.
  • the void can be easily eliminated without depending on the board design depending on the pressure range.
  • this static pressure press In this process, since the pressure is applied by static pressure, the adhesive's winding force S does not occur.
  • FIG. 1 is a diagram for explaining a method for manufacturing a semiconductor device of the present invention.
  • FIG. 2 shows an example of a wiring board in which a chip used in the present invention and an uncured adhesive layer are laminated.
  • FIG. 3 shows an example of a wiring board in which a chip used in the present invention and an uncured adhesive layer are laminated.
  • FIG. 4 is a diagram for explaining a conventional method of manufacturing a semiconductor device.
  • a wiring substrate 1 (chip 2 is bonded via an uncured adhesive layer 3) in which a chip 2 and an uncured adhesive layer 3 are stacked (die-bonded).
  • the laminated wiring board 1. The same applies hereinafter) is heated to cure the uncured adhesive layer 3 to manufacture a semiconductor device (FIG. 1). Finally, this adhesive layer is sufficiently cured.
  • the chip 2 a chip obtained by individually cutting a semiconductor wafer for each circuit is used.
  • the wiring substrate 4 for example, a lead frame made of metal, a substrate made of an organic material or an inorganic material, or a laminated substrate made of a metal and an organic material or an inorganic material is used.
  • a relatively lower chip is also regarded as a wiring board.
  • the uncured adhesive layer 3 is formed of a film-like or liquid adhesive. Preferably, it is formed from a film adhesive.
  • the adhesive used in the present invention is a thermosetting adhesive. It is an adhesive and may contain a thermosetting resin.
  • Thermosetting resins are, for example, epoxy, phenoxy, phenol, resorcinol, urea, melamine, furan, unsaturated polyester, silicone, etc., combined with appropriate curing agents and curing accelerators added as necessary. Used.
  • Various such thermosetting resins are known, and various known thermosetting resins are used in the present invention without particular limitation.
  • the thermosetting adhesive may be an adhesive having tackiness at room temperature.
  • An adhesive is an adhesive that exhibits tackiness at room temperature in the initial state and exhibits strong adhesiveness when cured by a trigger such as heating.
  • Examples of the adhesive having tackiness at normal temperature include a mixture of a binder resin having pressure-sensitive adhesive property at normal temperature and the thermosetting resin as described above.
  • Examples of the binder resin having pressure-sensitive adhesive property at normal temperature include acrylic resin, polyester resin, polybutyl ether, urethane resin, and polyamide.
  • a dicing die bonding sheet provided with a film adhesive layer is used.
  • the dicing die bonding sheet has a structure in which a film-like adhesive layer having the above-described composition is laminated on a base film so as to be peeled.
  • an urethane acrylate oligomer or the like is included in the composition of the adhesive forming the film-like adhesive layer. It is preferable to further blend an energy line curable resin. When an energy ray curable resin is blended, it is possible to impart an effect that it adheres well to the base material before irradiation with energy rays and is easily peeled off from the base material after irradiation with energy rays.
  • the thickness of the film-like adhesive layer formed on the dicing die-bonding sheet varies depending on the height of the uneven surface of the wiring board to be bonded, etc. Usually 3 to 10 ( ⁇ 111, preferably 10 ⁇ 50 111.
  • a liquid adhesive for example, from a thermosetting resin obtained by removing the binder resin from the composition of the film-like adhesive layer described above and its curing agent.
  • a liquid (paste-like) adhesive having the following composition is used.
  • thermosetting When using a die bonding sheet, for example, (1) dicing step, (2) die bonding step, (3) static pressure step, (4) thermosetting A semiconductor device is manufactured through each step of (5) assembly process.
  • the dicing process is a process in which a dicing die bonding sheet is attached to a wafer made of silicon or the like, and the wafer and the uncured adhesive layer are diced together. By this step, a chip having an uncured adhesive layer on one side is obtained. Dicing If the die bonding sheet has energy ray curability, the energy beam before the dicing step is irradiated after the dicing step to reduce the adhesion to the base film. Depending on the conditions for attaching the dicing die bonding sheet, a void may be formed at the interface between the chip and the uncured adhesive layer.
  • the dicing / peeling is performed at the interface between the substrate film of the die bonding sheet and the uncured adhesive layer 3, and the separated uncured adhesive layer is removed.
  • This is a step of stacking (die-bonding) a chip having a chip on a chip mounting portion of a wiring board.
  • the wiring substrate 1 in which the chip 2 and the uncured adhesive layer 3 are laminated is obtained.
  • void 6 may be formed at the interface between uncured adhesive layer 3 and wiring board 4 (Fig. 1).
  • the static pressure pressing step is a step of applying pressure (static pressure pressing) evenly from all directions of the die-bonded wiring board before the uncured adhesive layer is sufficiently cured.
  • the pressurizing condition in the present invention is 0.05 MPa or more with respect to the normal pressure, preferably 0.1 to 1. OMPa with respect to the normal pressure. That is, a pressure greater than 0.05 MPa, preferably 0.;! ⁇ 1.
  • the static pressure step include the following modes. First, the wiring board 1 to which the uncured adhesive layer 3 is die-bonded is pressed by the static pressure (FIGS. 1 and 1). By this pressurization by static pressure, voids (not shown) generated between the adhesive layer 3 and the chip 2 or voids 6 generated between the adhesive layer 3 and the wiring board 4 disappear. Even if the circuit board 4 is fine and the circuit design is large, the void 6 generated at the interface between the adhesive layer 3 and the circuit board 4 can be eliminated by performing this hydrostatic pressure process. . Thus, chip 2 The void 6 can be easily eliminated without specially controlling the conditions for laminating the wiring board 4 with the uncured adhesive layer 3. Further, in this static pressure pressurizing step, since the pressure is applied by static pressure, only the adhesive layer is not pressurized, and the adhesive is not rolled up.
  • the time for applying pressure is preferably 1 to 120 minutes, more preferably 5 to 90 minutes.
  • the static pressure device is not particularly limited as long as a static pressure can be applied to the die-bonded wiring board 1, but is preferably performed by an autoclave (a pressure vessel with a compressor) or the like.
  • autoclave a pressure vessel with a compressor
  • the temperature may be controlled so that the uncured adhesive layer 3 is not cured.
  • voids generated by the fluidization of the adhesive layer are likely to move and disappear easily.
  • Such a temperature is a force appropriately set according to the composition of the adhesive forming the adhesive layer 3, for example, about 30 to 120 ° C.
  • the thermosetting step is a step in which the adhesive layer 3 of the die-bonded wiring board 1 is heated to change from an uncured state to a sufficiently cured state (FIG. 1, II).
  • the uncured state means that the curing reaction of the adhesive is not progressing.
  • a sufficiently cured state that is, a state where curing is completed means that the reaction proceeds and the adhesive cannot be deformed.
  • the uncured adhesive layer 3 is cured to form a cured adhesive layer 8, and the adhesive performance necessary as an adhesive for die bonding of a semiconductor device is given.
  • the die-bonded wiring board maintains the state of (3) static pressure application process, and there are no voids on both sides of the adhesive layer 8, and the chip 2 and the wiring board 4 Are firmly bonded.
  • the heating temperature and the heating time are not particularly limited as long as the adhesive layer can be sufficiently cured, and depend on the composition of the adhesive.
  • the heating temperature is preferably 100 to 200 ° C, more preferably 120 to 160 ° C, and the heating time is preferably 15-300 minutes, more preferably 30-; 180 minutes
  • thermosetting device As a heating device for performing thermosetting, a conventionally used thermosetting device (oven) without particular limitation can be used as it is.
  • the assembly step is a step of assembling a die-bonded wiring board on which the adhesive layer has been heat-cured into a semiconductor device. For example, a wire bonding process for connecting the wires 9 as shown in FIG. 1 and a molding process using the sealing resin 11 are performed (FIGS. 1, III, and IV). In this way, the semiconductor device 10 is manufactured. Since the semiconductor device 10 obtained by the manufacturing method of the present invention has no voids at the interface of the adhesive layer, the reliability is evaluated and package cracks do not occur.
  • thermosetting step As described above, the method for manufacturing the semiconductor device in which (3) the pressure is returned to the normal pressure after the static pressure pressing step and (4) the thermosetting step is described, but the method for manufacturing the semiconductor device according to the present invention has been described.
  • a manufacturing method for performing a thermosetting step of heating and curing the uncured adhesive layer 3 in a static pressure state may be used.
  • the void is eliminated by performing a static pressure pressing step, and after the adhesive layer 3 is sufficiently cured by performing a heat curing step under a pressure, the static pressure is applied.
  • the press process and the thermosetting process may be completed at the same time.
  • it is preferable that voids in the adhesive layer considered to be generated at a high temperature at which thermosetting is performed are considered to be eliminated at the same time as static pressure is applied.
  • the semiconductor device has no voids in the adhesive layer or at the interface, and the adhesive is sufficiently cured, and the chip and the wiring board are firmly bonded.
  • the pressurizing condition in this embodiment is 0.05 MPa or more, preferably 0.;! To 1.0 MPa with respect to normal pressure, and the heating temperature is not particularly limited as long as the adhesive layer can be sufficiently cured. Preferably (100 to 200 ° C, more preferably (120 to 160 ° C).
  • the pressurization and heating time are not particularly limited as long as voids can be eliminated and the adhesive layer can be sufficiently cured, but preferably 15 to 300 minutes, more preferably 30 to 180 minutes.
  • thermosetting process is divided into two stages, the first stage is set to not cure the adhesive layer! /, The heating condition, and the second stage is set to the heating condition to cure the adhesive layer. May be.
  • the heating conditions for the first stage are, for example, a heating temperature of 30 to about 120 ° C., and a heating time is preferably 1 to 120 minutes, more preferably 5 to 90 minutes.
  • the second stage heating conditions are, for example, a heating temperature of 120 to 200 ° C., and a heating time of preferably 15 to 300 minutes, more preferably ⁇ 30 to 180 minutes.
  • a liquid (pasted) adhesive may be used as the adhesive layer 3.
  • a liquid adhesive a normal dicing sheet having no die bonding function is used instead of the dicing die bonding sheet in the above-mentioned (1) dicing process, and the wafer is made into chips.
  • die bonding is performed on the wiring board coated with the liquid adhesive.
  • the (3) static pressure pressing step, (4) thermosetting step, and (5) assembly step can be performed by the same method as described above. In order to make it easier to handle and / or handle die-bonded wiring boards!
  • the configuration of the semiconductor device obtained by the manufacturing method of the present invention is not limited to the above-described embodiment, and can be applied to the manufacture of semiconductor devices having various configurations.
  • the semiconductor device manufacturing method of the present invention may be applied to the manufacture of a multi-stack type semiconductor device. That is, an uncured adhesive layer is formed by connecting the chip 22 constituting the upper part and the wire 25! /, Or even! / And the chip 25 (wiring board) constituting the lower part relatively. It may be used in the die-bonding process between chips stacked via 23 (Fig. 2).
  • a semiconductor device may be a same size stack type semiconductor device having the same upper and lower sizes as shown in FIG. 2, or may be a stepped multi-stack type semiconductor device having different sizes. good.
  • the adhesive layer 23 may be a size-size stack type semiconductor device that is laminated so as to embed a wired wire. In this case, according to the present invention, voids generated around the wire are eliminated. It is more preferable because it is possible.
  • Such a method for manufacturing a multi-stack semiconductor device can be achieved by replacing the lower chip 25 with the wiring substrate 1 in the above-described embodiment.
  • the method for manufacturing a semiconductor device of the present invention may be used for a flip chip type semiconductor device as shown in FIG.
  • the underfine material used for flip chip bonding corresponds to the uncured adhesive layer.
  • the underfill material a liquid (paste-like) underfill material or a sheet-like underfill material may be used.
  • the thermosetting sheet-like underfill material for example, those described in Japanese Patent Application 2005-129502 by the applicants of the present application can be used.
  • a manufacturing method in the case of using a sheet-like underfill material is as follows. First, prepare a semiconductor wafer with bumps formed on the circuit surface. Affix the underfill layer (adhesive layer 33) of the above sheet to the circuit surface of the semiconductor wafer so as to penetrate the bumps. Next, a normal dicing tape is attached to the back surface of the semiconductor wafer, fixed to the ring frame through this, and the semiconductor wafer is cut and separated using a dicing apparatus to obtain a chip. Subsequently, only the base material of the said sheet
  • the flip-chip bonded wiring board obtained as described above is used in the same manner as in the above-described embodiment (3) static pressure pressing step, (4) thermosetting step, and (5) assembly.
  • the process is performed to manufacture a semiconductor device.
  • the wire-bonding step (5) in the assembly step is unnecessary, the semiconductor device is manufactured through the molding step after the uncured adhesive layer 33 (underfill material) is cured.
  • a circuit pattern is formed on the copper foil of a copper foil-clad laminate (Mitsubishi Gas Chemical Co., Ltd., CCL-HL830), and a solder resist (Taiyo Inki Co., PSR-4000 AUS5) is formed on the pattern. ) was used (made by Chino Giken Co., Ltd.).
  • the silicon chip obtained in (1) was picked up together with the adhesive layer (uncured adhesive layer) and placed on the wiring board via the adhesive layer, and then 100 ° C. , 300 gf for 1 second under pressure (die bond).
  • the adhesive layer After taking out the die-bonded wiring board from the heating and pressurizing device, the adhesive layer is cured by heating in a normal pressure oven at 120 ° C for 1 hour, followed by 140 ° C for 1 hour. I let you.
  • the die-bonded wiring board obtained in (3) is sealed with a mold resin (KE-1100AS3 manufactured by Kyocera Chemical Co., Ltd.) so that the sealing thickness is 400 m. Sealed. Next, the sealing resin was cured at 175 ° C. for 5 hours. In addition, the sealed wiring board is affixed to dicing tape (Adwill D-510T manufactured by Lintec), and diced to 12mm x 12mm size with a dicing device (DFD651 manufactured by Disco). Obtained a semiconductor device.
  • dicing tape Adwill D-510T manufactured by Lintec
  • Example 2 to [Example 6]
  • Example 1 a simulated semiconductor device was obtained in the same manner as in Example 1 except that the processing conditions in the (3) static pressure application step were changed to the conditions shown in Table 1.
  • Table 1 the pressure value indicates how much larger than the normal pressure.
  • a simulated semiconductor device was obtained in the same manner as in Example 1 except that the die bonding sheet was changed to Adwill LE-5006 (manufactured by Lintec).
  • Adhere UV curing dicing tape (Ad will D-628 Lintec) to a dummy silicon wafer (200mm diameter, thickness 150 / im) using tape mounter (Lintech, Adwill RAD2500 m / 8). At the same time, fixed to the ring frame. Next, dicing equipment (disco Using a DFD651), dicing into 8mm x 8mm size chips. The amount of cut when dicing was set to cut 20 m with respect to the base material. Thereafter, the substrate surface was irradiated with ultraviolet rays using a UV irradiation device (Adwill RAD 2000 m / 8 manufactured by Lintec Corporation).
  • a UV irradiation device (Adwill RAD 2000 m / 8 manufactured by Lintec Corporation).
  • a circuit pattern is formed on the copper foil of a copper foil-clad laminate (Mitsubishi Gas Chemical Co., Ltd., CCL-HL830), and a solder resist (Taiyo Inki Co., PSR-4000 AUS5) is formed on the pattern. ) was used (made by Chino Giken Co., Ltd.).
  • a paste adhesive consisting of the following combinations is applied onto the wiring board, and the silicon chip obtained in (1) is picked up and placed on the paste adhesive on the wiring board. After that, pressure bonding (die bonding) was performed under conditions of 23 ° C., 100 gf, and 1 second.
  • Liquid bisphenol A type skeleton epoxy resin (Japan Epoxy Resin Co., Ltd., Epicoat 828): 30 parts by weight, glycidinoreamine type epoxy resin (Japan Epoxy Resin Co., Ltd., Epicoat 630): 15 Parts by weight, nopolac-type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., EO CN-102S): 5 parts by weight, a solution in which a curing agent (manufactured by Asahi Denka, Ade force Hardener 3636AS) is dispersed in an organic solvent (methylethyl ketone) ( (Solid concentration is 15%): 5 parts by weight, curing accelerator (Shikoku Kasei Kogyo Co., Ltd. Curesol 2PHZ) dispersed in organic solvent (methyl ethyl ketone) (solid concentration is 15%): 10 parts by weight
  • a curing agent manufactured by Asahi Denka, Ade force Hard
  • thermosetting step (3) the static pressure application step and (4) the thermosetting step were started and ended simultaneously.
  • the circuit board on which the chip was die-bonded was placed in a heating and pressurizing device (autoclave manufactured by Kurihara Seisakusho) and subjected to a static pressure of 0.5 MPa at 120 ° C for 1 hour, followed by 140 ° C for 1 hour.
  • the adhesive layer was cured under pressure.
  • the die-bonded wiring board obtained in (3) is sealed with a mold resin (KE-1100AS3 manufactured by Kyocera Chemical Co., Ltd.) so that the sealing thickness is 400 m. Sealed. Next, the sealing resin was cured at 175 ° C. for 5 hours. Next, the sealed wiring board is diced with tape (Adwill D-510T manufactured by Lintec). A dummy semiconductor device was obtained by dicing into a 12 mm ⁇ 12 mm size with a dicing apparatus (DFD651, manufactured by DISCO Corporation).
  • a dicing apparatus D651, manufactured by DISCO Corporation.
  • Example 9 In the (2) die bonding step of Example 9, the same evaluation as in Example 9 was performed, except that the chip pressing condition was 23 ° C., 500 gf, 1 second. In addition, since there was too much roll-up of the adhesive after the die bonding process, the subsequent process was not performed.
  • Test 1 Check for voids
  • the same operation was performed using a transparent disc glass (manufactured by ENSG Precision Co., Ltd., diameter 8 inches, thickness 100 ⁇ m) instead of the silicon wafer. went.
  • the obtained wiring board on which the glass chip was die-bonded had an adhesive layer that could be seen through from the glass chip side, and the presence or absence of voids was observed with a digital microscope. The results are shown in Table 2.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Die Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A process for producing a semiconductor device which comprises heating a wiring board having a chip and uncured adhesive layer superposed thereon to cure the uncured adhesive layer, characterized by including a static pressing step in which before the curing, the wiring board having a chip and uncured adhesive layer superposed thereon is statically pressed at a pressure higher by at least 0.05 MPa than ordinary pressure. In the process for semiconductor device production, voids can be easily eliminated regardless of board design and the adhesive is prevented from curling up during the void-eliminating operation.

Description

明 細 書  Specification
半導体装置の製造方法  Manufacturing method of semiconductor device
技術分野  Technical field
[0001] 本発明は、半導体装置を製造する方法に関する。より詳しくは、本発明は、チップと 未硬化の接着剤層とが積層された配線基板を加熱して、上記未硬化の接着剤層を 硬化させて半導体装置を製造する方法に関する。  The present invention relates to a method for manufacturing a semiconductor device. More specifically, the present invention relates to a method of manufacturing a semiconductor device by heating a wiring board on which a chip and an uncured adhesive layer are laminated, and curing the uncured adhesive layer.
背景技術  Background art
[0002] 従来、半導体装置は、液状またはフィルム状の熱硬化性の接着剤によってチップと 配線基板とがダイボンドされ (ダイボンディング工程）、続いてワイヤーボンディングェ 程、モールディング工程を経て製造されている（図 4、 V〜VII)。チップ 2と配線基板 4 とを未硬化の接着剤層 3を介して積層する際に、接着剤中にボイド 5が存在したり、 接着剤のチップ側または配線基板側の界面にボイド 6が存在したりする場合がある（ 図 4)。これらのボイドはダイボンディング工程後にも消滅せずに存在する（図 4)。特 に、液状の接着剤を用いた場合は接着剤中にボイドが見られることが多ぐまた、フィ ルム状の接着剤を用いた場合は、接着力不足や被着面の凹凸への追従性不足のた め、上記界面にボイドが存在することが多い。  Conventionally, a semiconductor device is manufactured through a die bonding process (die bonding process) between a chip and a wiring board using a liquid or film thermosetting adhesive, followed by a wire bonding process and a molding process. (Figure 4, V-VII). When chip 2 and wiring board 4 are laminated via uncured adhesive layer 3, void 5 is present in the adhesive, or void 6 is present at the adhesive chip side or wiring board side interface. (Figure 4). These voids do not disappear after the die bonding process (Fig. 4). In particular, when a liquid adhesive is used, voids are often found in the adhesive, and when a film-like adhesive is used, the adhesive force is insufficient and the adherence to the unevenness of the adherend surface is followed. Voids often exist at the interface due to lack of properties.
[0003] しかしながら、このようなボイドは、半導体装置の信頼性評価においてパッケージク ラックの起点となるため、ボイドをなくす必要があった。 However, since such voids are the starting point of the package clock in the reliability evaluation of the semiconductor device, it is necessary to eliminate the voids.
[0004] これに対して、液状の接着剤であれば塗布時の低!/、粘度により、フィルム状の接着 剤であればダイボンド時の弾性率の低減化により、あるいは、ダイボンド条件の最適 化により、配線基板の凹凸に追従させることが試みられている（特許文献 1)。 [0004] On the other hand, if it is a liquid adhesive, it is low at the time of application / viscosity, and if it is a film adhesive, it reduces the elastic modulus at the time of die bonding, or optimizes the die bonding conditions. Therefore, it is attempted to follow the unevenness of the wiring board (Patent Document 1).
特許文献 1：国際公開第 2005/004216号パンフレット  Patent Document 1: International Publication No. 2005/004216 Pamphlet
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0005] 液状またはフィルム状の接着剤を用いた場合、上記の方法によりボイドを減らせる [0005] When a liquid or film adhesive is used, voids can be reduced by the above method.
1S 低粘度あるいは低弾性率化すると、ダイボンド時にチップ端面へ接着剤がはみ 出す不具合が発生する。特に近年の薄型化されたチップにおいては、そのはみ出し た接着剤がチップ回路面に巻き上がり、ワイヤーパッドを汚染して、ワイヤー接合強 度を低下させるという問題がある。 1S If the viscosity or elastic modulus is lowered, there will be a problem that the adhesive protrudes from the chip end face during die bonding. Especially in recent thinned chips As a result, the adhesive rolls up on the chip circuit surface, contaminates the wire pad, and lowers the wire bonding strength.
[0006] また、特にフィルム状の接着剤を用いた場合、上記界面に存在するボイドの発生に ついては、基板デザインにも依存する。このため、基板デザインが変更になるたびに 配合変更による粘度コントロールや弾性率の低下、あるいはダイボンド条件の見直し 、最適化を行わなければならず、その极いも困難である。特に近年の高密度な配線 基板においては、凹凸の段差が大きぐその段差を埋めるべくダイボンドを行うのは かなり困難である。 [0006] In particular, when a film-like adhesive is used, the generation of voids existing at the interface depends on the substrate design. For this reason, each time the substrate design is changed, viscosity control, a decrease in elastic modulus due to a change in composition, or a review and optimization of die bonding conditions must be performed, which is extremely difficult. In particular, in recent high-density wiring boards, it is quite difficult to perform die bonding to fill in the uneven step.
[0007] したがって、本発明の目的は、基板デザインに依存せず、ボイドのない半導体装置 が簡便に製造できる方法を提供することであり、さらに、この際に接着剤の巻き上がり も見られない半導体装置が製造できる方法を提供することにある。  [0007] Therefore, an object of the present invention is to provide a method that can easily manufacture a semiconductor device without voids, which does not depend on the substrate design, and in this case, the adhesive is not rolled up. An object of the present invention is to provide a method capable of manufacturing a semiconductor device.
課題を解決するための手段  Means for solving the problem
[0008] 本発明者らは鋭意研究した結果、特定の静圧加圧工程により上記課題を解決でき ることを見出し、本発明を完成するに至った。 [0008] As a result of intensive studies, the present inventors have found that the above-mentioned problems can be solved by a specific hydrostatic pressure step, and have completed the present invention.
[0009] すなわち、本発明に係る半導体装置の製造方法は、 That is, a method for manufacturing a semiconductor device according to the present invention includes:
チップと未硬化の接着剤層とが積層された配線基板 (チップが未硬化の接着剤層 を介して積層された配線基板）を加熱して、上記未硬化の接着剤層を硬化させて半 導体装置を製造する方法であって、  A wiring board in which a chip and an uncured adhesive layer are laminated (wiring board in which a chip is laminated through an uncured adhesive layer) is heated to cure the uncured adhesive layer and to make a half A method of manufacturing a conductor device, comprising:
上記硬化前（上記硬化が完了する前）に、上記チップと未硬化の接着剤層とが積 層された配線基板を常圧に対して 0. 05MPa以上の静圧により加圧する静圧加圧 工程を含むことを特徴とする。  Static pressure pressurizing the circuit board on which the chip and uncured adhesive layer are stacked before the above curing (before the curing is completed) with a static pressure of 0.05 MPa or more against normal pressure Including a process.
[0010] また、上記静圧加圧工程による加圧状態のまま、上記チップと未硬化の接着剤層と が積層された配線基板を加熱して上記未硬化の接着剤層を硬化する熱硬化工程を さらに含むことが好ましい。 [0010] In addition, thermosetting is performed by heating the wiring substrate in which the chip and the uncured adhesive layer are laminated while the pressurized state in the static pressure pressing process is performed, thereby curing the uncured adhesive layer. It is preferable to further include a step.
発明の効果  The invention's effect
[0011] 本発明に係る半導体装置の製造方法によれば、チップと配線基板とを未硬化の接 着剤層により積層する際は、通常通りの条件で行うことができ、その後の静圧加圧ェ 程により基板デザインに依存せず簡便にボイドを消滅できる。また、この静圧加圧ェ 程においては静圧により加圧するため、接着剤の巻き上力 Sりも起こらない。 [0011] According to the method for manufacturing a semiconductor device according to the present invention, when the chip and the wiring board are laminated with the uncured adhesive layer, the normal condition can be applied and the subsequent static pressure application can be performed. The void can be easily eliminated without depending on the board design depending on the pressure range. In addition, this static pressure press In this process, since the pressure is applied by static pressure, the adhesive's winding force S does not occur.
図面の簡単な説明  Brief Description of Drawings
[0012] [図 1]図 1は、本発明の半導体装置の製造方法を説明するための図である。  FIG. 1 is a diagram for explaining a method for manufacturing a semiconductor device of the present invention.
[図 2]図 2は、本発明に用いられるチップと未硬化の接着剤層とが積層された配線基 板の例を示す。  FIG. 2 shows an example of a wiring board in which a chip used in the present invention and an uncured adhesive layer are laminated.
[図 3]図 3は、本発明に用いられるチップと未硬化の接着剤層とが積層された配線基 板の例を示す。  FIG. 3 shows an example of a wiring board in which a chip used in the present invention and an uncured adhesive layer are laminated.
[図 4]図 4は、従来の半導体装置の製造方法を説明するための図である。  FIG. 4 is a diagram for explaining a conventional method of manufacturing a semiconductor device.
符号の説明  Explanation of symbols
[0013] 1: チップと未硬化の接着剤層とが積層された配線基板  [0013] 1: Wiring board in which chip and uncured adhesive layer are laminated
2:  2:
3: 未硬化の接着剤層  3: Uncured adhesive layer
4: 配線基板  4: Wiring board
5: 接着剤層中に存在するボイド  5: Void present in the adhesive layer
6: 配線基板と接着剤層との界面に存在するボイド  6: Void present at the interface between the wiring board and adhesive layer
8: 硬化した接着剤層  8: Hardened adhesive layer
9: ワイヤー  9: Wire
10:  Ten:
11: 封止樹脂  11: Sealing resin
I： 静圧加圧工程  I: Static pressure application process
II： 熱硬化工程  II: Thermosetting process
III： ワイヤーボンディング工程  III: Wire bonding process
IV： モールディング工程  IV: Molding process
21: 封止前のマルチスタック型半導体装置  21: Multi-stack semiconductor device before sealing
22: 相対的に上部 (第 2層）を構成 - 22: Relatively upper part (2nd layer)-
23: 未硬化の接着剤層 23: Uncured adhesive layer
25: 相対的に下部 (第 1層）を構成 - (配線基板)  25: Relatively lower part (first layer)-(wiring board)
26: 27： チップ搭載用配線基板 26: 27: Chip mounting circuit board
31： チップと未硬化の接着剤層（アンダーフィル材）とが積層（フリップチップ ボンド）された配線基板  31: Wiring board in which chip and uncured adhesive layer (underfill material) are laminated (flip chip bond)
32 : チップ  32: Chip
33 : 未硬化の接着剤層  33: Uncured adhesive layer
34： 配線基板  34: Wiring board
35 : バンプ  35: Bump
41： 充分に硬化した接着剤層を有する配線基板  41: Wiring board with a fully cured adhesive layer
42 : 硬化した接着剤層  42: hardened adhesive layer
43 : ワイヤー  43: Wire
44 : 半導体装置  44: Semiconductor device
45 : 封止樹脂  45: Sealing resin
V： ダイボンディング工程  V: Die bonding process
VI： ワイヤーボンディング工程  VI: Wire bonding process
VII： モールディング工程  VII: Molding process
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0014] 以下、本発明について具体的に説明する。  Hereinafter, the present invention will be specifically described.
[0015] 本発明に係る半導体装置の製造方法では、チップ 2と未硬化の接着剤層 3とが積 層（ダイボンド）された配線基板 1 (チップ 2が未硬化の接着剤層 3を介して積層された 配線基板 1。以下同様。）を加熱して、上記未硬化の接着剤層 3を硬化させて半導体 装置を製造する（図 1)。なお、最終的にはこの接着剤層は充分に硬化されている。  In the method for manufacturing a semiconductor device according to the present invention, a wiring substrate 1 (chip 2 is bonded via an uncured adhesive layer 3) in which a chip 2 and an uncured adhesive layer 3 are stacked (die-bonded). The laminated wiring board 1. The same applies hereinafter) is heated to cure the uncured adhesive layer 3 to manufacture a semiconductor device (FIG. 1). Finally, this adhesive layer is sufficiently cured.
[0016] チップ 2としては、半導体ウェハを回路ごとに個別に切断して得られたチップを用い る。また、配線基板 4としては、例えば金属からなるリードフレーム、有機材料または 無機材料からなる基板、または金属および有機材料または無機材料からなる積層基 板などが用いられる。また、本発明において、マルチスタック型半導体装置を製造す る場合は、相対的に下側に位置するチップも配線基板とみなす。  [0016] As the chip 2, a chip obtained by individually cutting a semiconductor wafer for each circuit is used. As the wiring substrate 4, for example, a lead frame made of metal, a substrate made of an organic material or an inorganic material, or a laminated substrate made of a metal and an organic material or an inorganic material is used. In the present invention, when a multi-stack type semiconductor device is manufactured, a relatively lower chip is also regarded as a wiring board.
[0017] 未硬化の接着剤層 3は、フィルム状または液状の接着剤から形成される。好ましく はフィルム状の接着剤から形成される。本発明に用いられる接着剤は熱硬化性の接 着剤であり、熱硬化性樹脂を含んでいればよい。熱硬化性樹脂は、たとえば、ェポキ シ、フエノキシ、フエノール、レゾルシノール、ユリア、メラミン、フラン、不飽和ポリエス テル、シリコーンなどであり、適当な硬化剤及び必要に応じて添加される硬化促進剤 と組み合わせて用いられる。このような熱硬化性樹脂は種々知られており、本発明に おいては特に制限されることなく公知の様々な熱硬化性樹脂が用いられる。また、熱 硬化性の接着剤としては、常温で粘着性を有する粘接着剤であってもよい。粘接着 剤とは、初期状態において常温で粘着性を示し、加熱のようなトリガーにより硬化し強 固な接着性を示す接着剤をいう。常温で粘着性を有する粘接着剤としては、たとえば 常温で感圧接着性を有するバインダー樹脂と、上記のような熱硬化性樹脂との混合 物が挙げられる。常温で感圧接着性を有するバインダー樹脂としては、たとえばァク リル樹脂、ポリエステル樹脂、ポリビュルエーテル、ウレタン樹脂、ポリアミド等が挙げ られる。 [0017] The uncured adhesive layer 3 is formed of a film-like or liquid adhesive. Preferably, it is formed from a film adhesive. The adhesive used in the present invention is a thermosetting adhesive. It is an adhesive and may contain a thermosetting resin. Thermosetting resins are, for example, epoxy, phenoxy, phenol, resorcinol, urea, melamine, furan, unsaturated polyester, silicone, etc., combined with appropriate curing agents and curing accelerators added as necessary. Used. Various such thermosetting resins are known, and various known thermosetting resins are used in the present invention without particular limitation. Further, the thermosetting adhesive may be an adhesive having tackiness at room temperature. An adhesive is an adhesive that exhibits tackiness at room temperature in the initial state and exhibits strong adhesiveness when cured by a trigger such as heating. Examples of the adhesive having tackiness at normal temperature include a mixture of a binder resin having pressure-sensitive adhesive property at normal temperature and the thermosetting resin as described above. Examples of the binder resin having pressure-sensitive adhesive property at normal temperature include acrylic resin, polyester resin, polybutyl ether, urethane resin, and polyamide.
[0018] 本発明において、接着剤層 3としてフィルム状の接着剤を使用する場合は、例えば 、フィルム状の接着剤層が設けられたダイシング 'ダイボンディングシートが用いられ る。ダイシング'ダイボンディングシートは、基材フィルム上に前述した組成のフィルム 状の接着剤層が剥離可能に積層した構成を有する。ダイシング ·ダイボンディングシ ートの基材フィルムとフィルム状の接着剤層との剥離性を制御するため、フィルム状 の接着剤層を形成する接着剤の組成中にウレタン系アタリレートオリゴマーなどのェ ネルギ一線硬化性樹脂をさらに配合することが好ましい。エネルギー線硬化性樹脂 を配合すると、エネルギー線照射前は基材とよく密着し、エネルギー線照射後は基 材から剥離しやすくなるという効果を付与できる。  In the present invention, when a film adhesive is used as the adhesive layer 3, for example, a dicing die bonding sheet provided with a film adhesive layer is used. The dicing die bonding sheet has a structure in which a film-like adhesive layer having the above-described composition is laminated on a base film so as to be peeled. In order to control the peelability between the base film of the dicing die-bonding sheet and the film-like adhesive layer, an urethane acrylate oligomer or the like is included in the composition of the adhesive forming the film-like adhesive layer. It is preferable to further blend an energy line curable resin. When an energy ray curable resin is blended, it is possible to impart an effect that it adheres well to the base material before irradiation with energy rays and is easily peeled off from the base material after irradiation with energy rays.
[0019] ダイシング'ダイボンディングシートに形成されるフィルム状の接着剤層の厚みは、 接着する配線基板の凹凸の高さ形状等によって異なる力 通常 3〜； 10(^ 111、好まし くは 10〜50 111である。  [0019] The thickness of the film-like adhesive layer formed on the dicing die-bonding sheet varies depending on the height of the uneven surface of the wiring board to be bonded, etc. Usually 3 to 10 (^ 111, preferably 10 ~ 50 111.
[0020] また、本発明において接着剤層 3として液状の接着剤を使用する場合は、例えば、 前述したフィルム状の接着剤層の組成からバインダー樹脂を除いた熱硬化性樹脂と その硬化剤からなる配合の液状 (ペースト状)接着剤が用いられる。  [0020] Further, when a liquid adhesive is used as the adhesive layer 3 in the present invention, for example, from a thermosetting resin obtained by removing the binder resin from the composition of the film-like adhesive layer described above and its curing agent. A liquid (paste-like) adhesive having the following composition is used.
[0021] 次に、本発明の半導体装置の製造方法について、ダイシング 'ダイボンディングシ ート（フィルム状の接着剤）を使用した場合の具体例について説明する。 Next, with respect to the method for manufacturing a semiconductor device of the present invention, dicing and die bonding A specific example of using a sheet (film adhesive) will be described.
[0022] 本発明にお!/、て、ダイシング 'ダイボンディングシートを使用する場合、例えば、（1) ダイシング工程、（2)ダイボンド工程、（3)静圧加圧工程、（4)熱硬化工程、（5)組立 工程の各工程を経て半導体装置が製造される。  [0022] In the present invention! /, Dicing When using a die bonding sheet, for example, (1) dicing step, (2) die bonding step, (3) static pressure step, (4) thermosetting A semiconductor device is manufactured through each step of (5) assembly process.
[0023] (1)ダイシング工程は、シリコン等からなるウェハにダイシング ·ダイボンディングシ 一トを貼着して、ウェハと未硬化の接着剤層をともにダイシングする工程である。この 工程により、片面に未硬化の接着剤層を有するチップが得られる。ダイシング 'ダイボ ンデイングシートがエネルギー線硬化性を有する場合は、ダイシング工程前あるレ、は ダイシング工程後にエネルギー線を照射し、基材フィルムとの密着性を低下させてお く。ダイシング'ダイボンディングシートを貼着する条件によっては、チップと未硬化の 接着剤層との界面にボイドが形成される場合がある。  [0023] (1) The dicing process is a process in which a dicing die bonding sheet is attached to a wafer made of silicon or the like, and the wafer and the uncured adhesive layer are diced together. By this step, a chip having an uncured adhesive layer on one side is obtained. Dicing If the die bonding sheet has energy ray curability, the energy beam before the dicing step is irradiated after the dicing step to reduce the adhesion to the base film. Depending on the conditions for attaching the dicing die bonding sheet, a void may be formed at the interface between the chip and the uncured adhesive layer.
[0024] (2)ダイボンド工程は、ダイシング.ダイボンディングシートの基材フィルムと未硬化 の接着剤層 3の界面で剥離 (ピックアップ)を行!/、、分離された未硬化の接着剤層を 有するチップを配線基板のチップ搭載部に積層（ダイボンド)する工程である。このェ 程により、チップ 2と未硬化の接着剤層 3とが積層された配線基板 1が得られる。ダイ ボンドの条件 (圧力、温度、時間等）によっては、未硬化の接着剤層 3と配線基板 4と の界面にボイド 6が形成される場合がある (図 1)。  [0024] (2) In the die bonding step, the dicing / peeling is performed at the interface between the substrate film of the die bonding sheet and the uncured adhesive layer 3, and the separated uncured adhesive layer is removed. This is a step of stacking (die-bonding) a chip having a chip on a chip mounting portion of a wiring board. Through this process, the wiring substrate 1 in which the chip 2 and the uncured adhesive layer 3 are laminated is obtained. Depending on the die bonding conditions (pressure, temperature, time, etc.), void 6 may be formed at the interface between uncured adhesive layer 3 and wiring board 4 (Fig. 1).
[0025] (3)静圧加圧工程は、未硬化の接着剤層が充分に硬化される前に、ダイボンドされ た配線基板の全方位から均等に加圧（静圧加圧）を行う工程である（図 1、 1)。本発明 における加圧条件は、常圧に対し 0. 05MPa以上であり、好ましくは常圧に対し 0. 1 〜； 1. OMPaである。すなわち、常圧に比較して 0. 05MPa以上大きな圧力、好ましく は 0.；!〜 1. OMPa大きな圧力を印加する。  [0025] (3) The static pressure pressing step is a step of applying pressure (static pressure pressing) evenly from all directions of the die-bonded wiring board before the uncured adhesive layer is sufficiently cured. (Fig. 1, 1). The pressurizing condition in the present invention is 0.05 MPa or more with respect to the normal pressure, preferably 0.1 to 1. OMPa with respect to the normal pressure. That is, a pressure greater than 0.05 MPa, preferably 0.;! ~ 1.
[0026] 静圧加圧工程には、具体的には、以下のような態様が挙げられる。まず、未硬化状 態の接着剤層 3がダイボンドされた配線基板 1を上記静圧により加圧する（図 1、 1)。 この静圧による加圧により、接着剤層 3とチップ 2との間に発生したボイド（図示せず） または接着剤層 3と配線基板 4との間に発生したボイド 6が消滅する。配線基板 4が微 細で高低差が大きな回路デザインであったとしても、この静圧加圧工程を行えば、接 着剤層 3と配線基板 4との界面に生じたボイド 6も消滅させられる。このように、チップ 2 と配線基板 4とを未硬化の接着剤層 3により積層する際の条件を特別に制御すること なぐ簡便にボイド 6を消滅できる。また、この静圧加圧工程においては静圧による加 圧であるため、接着剤層のみが加圧されず、接着剤の巻き上がりも起こらない。 [0026] Specific examples of the static pressure step include the following modes. First, the wiring board 1 to which the uncured adhesive layer 3 is die-bonded is pressed by the static pressure (FIGS. 1 and 1). By this pressurization by static pressure, voids (not shown) generated between the adhesive layer 3 and the chip 2 or voids 6 generated between the adhesive layer 3 and the wiring board 4 disappear. Even if the circuit board 4 is fine and the circuit design is large, the void 6 generated at the interface between the adhesive layer 3 and the circuit board 4 can be eliminated by performing this hydrostatic pressure process. . Thus, chip 2 The void 6 can be easily eliminated without specially controlling the conditions for laminating the wiring board 4 with the uncured adhesive layer 3. Further, in this static pressure pressurizing step, since the pressure is applied by static pressure, only the adhesive layer is not pressurized, and the adhesive is not rolled up.
[0027] 印加する圧力が上記範囲にあると、効率的にボイドの消滅が促されるとともに、汎用 の加圧装置、耐圧防爆設備が使用でき、生産ラインをコンパクトにできる。また、設定 圧力までの時間をほとんど要しな!/、点で好ましレ、。  [0027] When the applied pressure is within the above range, void disappearance is efficiently promoted, and a general-purpose pressurizing device and explosion-proof equipment can be used, making the production line compact. Also, it takes almost no time to set pressure!
[0028] また、圧力を印加する時間は、好ましくは 1〜； 120分、より好ましくは 5〜90分である [0028] The time for applying pressure is preferably 1 to 120 minutes, more preferably 5 to 90 minutes.
〇 Yes
[0029] 静圧加圧装置としては、ダイボンドされた配線基板 1に静圧が印加できれば特に制 限されないが、好ましくは、オートクレープ（コンプレッサー付き耐圧容器)などにより 行われる。ところで、オートクレープなど一定容積内で圧力が加えられると雰囲気温 度の上昇が起こる。半導体装置の安定生産を行うためには温度を一定に保つことが 好ましいため、未硬化の接着剤層 3が硬化しない程度の温度に制御してもよい。また 、温度を上げることにより、接着剤層が流動化して発生したボイドが動きやすくなり、 消滅しやすくなることも期待できる。このような温度としては、接着剤層 3を形成する接 着剤の組成によって適宜設定される力 例えば、 30〜； 120°C程度である。  [0029] The static pressure device is not particularly limited as long as a static pressure can be applied to the die-bonded wiring board 1, but is preferably performed by an autoclave (a pressure vessel with a compressor) or the like. By the way, when pressure is applied within a certain volume such as autoclave, the ambient temperature rises. Since it is preferable to keep the temperature constant for stable production of semiconductor devices, the temperature may be controlled so that the uncured adhesive layer 3 is not cured. In addition, it can be expected that by increasing the temperature, voids generated by the fluidization of the adhesive layer are likely to move and disappear easily. Such a temperature is a force appropriately set according to the composition of the adhesive forming the adhesive layer 3, for example, about 30 to 120 ° C.
[0030] (4)熱硬化工程は、ダイボンドされた配線基板 1の接着剤層 3を加熱して未硬化状 態から充分な硬化状態にする工程である（図 1、 II) なお、本明細書において、未硬 化状態とは、接着剤の硬化反応が進行していない状態にあることをいう。充分な硬化 状態、すなわち、硬化が完了した状態とは、反応が進行し、接着剤が変形できない 状態にあることを!/、う。 （3)静圧加圧工程でボイドが消滅したダイボンドされた配線基 板 1を加圧装置から開放し、大気圧下で使用する加熱装置に投入する。これにより、 未硬化の接着剤層 3を硬化させて硬化した接着剤層 8とし、半導体装置のダイボンド 用接着剤として必要な接着性能が与えられる。この状態におけるダイボンドされた配 線基板は、（3)静圧加圧工程の状態を維持しており、接着剤層 8の両側の界面には ボイドが存在せず、チップ 2と配線基板 4とが強固に接着されている。  [0030] (4) The thermosetting step is a step in which the adhesive layer 3 of the die-bonded wiring board 1 is heated to change from an uncured state to a sufficiently cured state (FIG. 1, II). In the text, the uncured state means that the curing reaction of the adhesive is not progressing. A sufficiently cured state, that is, a state where curing is completed means that the reaction proceeds and the adhesive cannot be deformed. (3) Release the die-bonded wiring board 1 from which the voids disappeared in the hydrostatic pressing process from the pressurizing device, and put it in the heating device used under atmospheric pressure. As a result, the uncured adhesive layer 3 is cured to form a cured adhesive layer 8, and the adhesive performance necessary as an adhesive for die bonding of a semiconductor device is given. In this state, the die-bonded wiring board maintains the state of (3) static pressure application process, and there are no voids on both sides of the adhesive layer 8, and the chip 2 and the wiring board 4 Are firmly bonded.
[0031] 加熱温度及び加熱時間は、接着剤層が充分に硬化できれば特に制限されず、接 着剤組成に依存する。加熱温度は、好ましくは、 100〜200°C、より好ましくは 120〜 160°Cであり、加熱時間は、好ましくは 1 5〜300分、より好ましくは 30〜； 180分であ [0031] The heating temperature and the heating time are not particularly limited as long as the adhesive layer can be sufficiently cured, and depend on the composition of the adhesive. The heating temperature is preferably 100 to 200 ° C, more preferably 120 to 160 ° C, and the heating time is preferably 15-300 minutes, more preferably 30-; 180 minutes
[0032] 熱硬化を行うための加熱装置としては、特に制限はなぐ従来使用される熱硬化装 置 (オーブン）がそのまま使用できる。 [0032] As a heating device for performing thermosetting, a conventionally used thermosetting device (oven) without particular limitation can be used as it is.
[0033] ( 5)組立工程は、接着剤層の熱硬化が行われたダイボンドされた配線基板を半導 体装置に組立加工する工程である。例えば、図 1に示す工程のようにワイヤー 9を結 線するワイヤーボンディング工程、封止樹脂 1 1を用いたモールディング工程などが 行われる（図 1、 III、 IV)。このようにして半導体装置 10が製造される。本発明の製造 方法によって得られた半導体装置 10は、接着剤層の界面にボイドが存在しないため 、信頼性評価にぉレ、てパッケージクラックが生じなレ、。  [0033] (5) The assembly step is a step of assembling a die-bonded wiring board on which the adhesive layer has been heat-cured into a semiconductor device. For example, a wire bonding process for connecting the wires 9 as shown in FIG. 1 and a molding process using the sealing resin 11 are performed (FIGS. 1, III, and IV). In this way, the semiconductor device 10 is manufactured. Since the semiconductor device 10 obtained by the manufacturing method of the present invention has no voids at the interface of the adhesive layer, the reliability is evaluated and package cracks do not occur.
[0034] 以上、（3)静圧加圧工程の後に常圧に戻してから（4)熱硬化工程を行う半導体装 置を製造する方法について説明したが、本発明に係る半導体装置の製造方法は、（ 3)静圧加圧工程において、静圧加圧状態のまま、上記未硬化の接着剤層 3を加熱 して硬化する熱硬化工程を行う製造方法でもよい。  As described above, the method for manufacturing the semiconductor device in which (3) the pressure is returned to the normal pressure after the static pressure pressing step and (4) the thermosetting step is described, but the method for manufacturing the semiconductor device according to the present invention has been described. (3) In the static pressure application step, a manufacturing method for performing a thermosetting step of heating and curing the uncured adhesive layer 3 in a static pressure state may be used.
[0035] 具体的には、静圧加圧工程を行ってボイドを消滅させるとともに、加圧下におきな 力 ¾熱硬化工程を行って接着剤層 3を充分に硬化させた後に、静圧加圧工程と熱硬 化工程とを同時に終了する態様であってもよい。この場合は、熱硬化が行われるよう な高温で発生すると考えられる接着剤層中のボイドを、発生すると同時に静圧加圧 により消滅させられると考えられるので好ましい。最終的に、半導体装置は接着剤層 中にも界面にもボイドが存在せず、充分に接着剤が硬化した状態となり、チップと配 線基板とが強固に接着される。  [0035] Specifically, the void is eliminated by performing a static pressure pressing step, and after the adhesive layer 3 is sufficiently cured by performing a heat curing step under a pressure, the static pressure is applied. The press process and the thermosetting process may be completed at the same time. In this case, it is preferable that voids in the adhesive layer considered to be generated at a high temperature at which thermosetting is performed are considered to be eliminated at the same time as static pressure is applied. Ultimately, the semiconductor device has no voids in the adhesive layer or at the interface, and the adhesive is sufficiently cured, and the chip and the wiring board are firmly bonded.
[0036] 本態様における加圧条件は、常圧に対し 0. 05MPa以上、好ましくは 0.；!〜 1 . 0 MPaであり、加熱温度は、接着剤層が充分に硬化できれば特に制限されないが、好 ましく (ま、 100〜200°C、より好ましく (ま 120〜； 160°Cである。  [0036] The pressurizing condition in this embodiment is 0.05 MPa or more, preferably 0.;! To 1.0 MPa with respect to normal pressure, and the heating temperature is not particularly limited as long as the adhesive layer can be sufficiently cured. Preferably (100 to 200 ° C, more preferably (120 to 160 ° C).
[0037] また、加圧および加熱時間は、ボイドが消滅でき、接着剤層が充分に硬化できれば 特に制限されないが、好ましくは 1 5〜300分、より好ましくは 30〜； 180分である。  [0037] The pressurization and heating time are not particularly limited as long as voids can be eliminated and the adhesive layer can be sufficiently cured, but preferably 15 to 300 minutes, more preferably 30 to 180 minutes.
[0038] また、熱硬化工程を 2段階に分けて、第 1段階を接着剤層を硬化させな!/、加熱条件 とし、第 2段階を接着剤層を硬化させる加熱条件とする態様であっても良い。この場 合、第 1段階の加熱条件は、例えば、加熱温度が 30〜； 120°C程度であり、加熱時間 は、好ましくは 1〜120分、より好ましくは 5〜90分である。また、第 2段階の加熱条件 は、例えば、加熱温度が 120〜200°Cであり、加熱時間は、好ましくは 15〜300分、 より好まし <は 30〜； 180分である。 [0038] In addition, the thermosetting process is divided into two stages, the first stage is set to not cure the adhesive layer! /, The heating condition, and the second stage is set to the heating condition to cure the adhesive layer. May be. This place In this case, the heating conditions for the first stage are, for example, a heating temperature of 30 to about 120 ° C., and a heating time is preferably 1 to 120 minutes, more preferably 5 to 90 minutes. The second stage heating conditions are, for example, a heating temperature of 120 to 200 ° C., and a heating time of preferably 15 to 300 minutes, more preferably <30 to 180 minutes.
[0039] また、本発明の半導体装置の製造方法においては、接着剤層 3として液状 (ペース ト状）の接着剤が使用されても良い。液状の接着剤を使用する場合は、前述の（1)ダ イシング工程において、ダイシング 'ダイボンディングシートの代わりにダイボンド機能 のない通常のダイシングシートが使用され、ウェハがチップ化される。 （2)ダイボンド 工程でチップをピックアップした後、液状接着剤を塗布した配線基板にダイボンドを 行う。 （3)静圧加圧工程、（4)熱硬化工程及び（5)組み立て工程は、前述の態様と 同様の方法で行うことができる。ダイボンドされた配線基板の取扱!/、を行!/、易くする ため、（3)静圧加圧工程の前で液状の接着剤を半硬化（Bステージ化）させる加熱ェ 程を加えても良い。なお、液状の接着剤を用いた場合は、ダイボンド工程で接着剤 層 3中にボイド 5が存在していても、静圧加圧工程によってボイド 5が消滅できる（図 4 参照)。 In the method for manufacturing a semiconductor device of the present invention, a liquid (pasted) adhesive may be used as the adhesive layer 3. When a liquid adhesive is used, a normal dicing sheet having no die bonding function is used instead of the dicing die bonding sheet in the above-mentioned (1) dicing process, and the wafer is made into chips. (2) After the chip is picked up in the die bonding process, die bonding is performed on the wiring board coated with the liquid adhesive. The (3) static pressure pressing step, (4) thermosetting step, and (5) assembly step can be performed by the same method as described above. In order to make it easier to handle and / or handle die-bonded wiring boards! (3) Even if a heating process that semi-cures the liquid adhesive (B-stage) is added before the static pressure process good. When a liquid adhesive is used, even if the void 5 is present in the adhesive layer 3 in the die bonding process, the void 5 can be eliminated by the hydrostatic pressing process (see FIG. 4).
[0040] 本発明の製造方法によって得られる半導体装置の構成は前述の態様のものに限 定されず、種々の構成の半導体装置の製造に適用できる。  [0040] The configuration of the semiconductor device obtained by the manufacturing method of the present invention is not limited to the above-described embodiment, and can be applied to the manufacture of semiconductor devices having various configurations.
[0041] 例えば、本発明の半導体装置の製造方法は、マルチスタック型の半導体装置の製 造に適用してもよい。すなわち、相対的に上部を構成するチップ 22と、ワイヤーが結 線されて!/、てもよ!/、相対的に下部を構成するチップ 25 (配線基板）とを未硬化の接 着剤層 23を介して積層するチップどうしのダイボンド工程に用いても良い（図 2)。こ のような半導体装置は、図 2のように上部と下部のサイズが同じセィムサイズスタック 型半導体装置であっても良いし、サイズの異なる階段状のマルチスタック型半導体装 置であっても良い。さらに、接着剤層 23が、結線されたワイヤーを埋め込む形で積層 されたセィムサイズスタック型半導体装置であっても良ぐこの場合、本発明によれば 、ワイヤーの周辺に発生するボイドを消滅できるのでより好ましい。  For example, the semiconductor device manufacturing method of the present invention may be applied to the manufacture of a multi-stack type semiconductor device. That is, an uncured adhesive layer is formed by connecting the chip 22 constituting the upper part and the wire 25! /, Or even! / And the chip 25 (wiring board) constituting the lower part relatively. It may be used in the die-bonding process between chips stacked via 23 (Fig. 2). Such a semiconductor device may be a same size stack type semiconductor device having the same upper and lower sizes as shown in FIG. 2, or may be a stepped multi-stack type semiconductor device having different sizes. good. Furthermore, the adhesive layer 23 may be a size-size stack type semiconductor device that is laminated so as to embed a wired wire. In this case, according to the present invention, voids generated around the wire are eliminated. It is more preferable because it is possible.
[0042] このようなマルチスタック型半導体装置の製造方法は、前述の態様において下部の チップ 25を配線基板 1の代わりとすることにより達成できる。 [0043] また、本発明の半導体装置の製造方法は、図 3に示すように、フリップチップ型の半 導体装置に用いてもよい。この場合、フリップチップボンドに用いられるアンダーフィ ノレ材が未硬化の接着剤層に相当する。アンダーフィル材としては、液状 (ペースト状） のアンダーフィル材を用いても良ぐシート状アンダーフィル材を用いても良い。熱硬 化性のシート状アンダーフィル材としては、例えば、本願出願人らによる特願 2005— 129502に記載されたものが使用できる。 Such a method for manufacturing a multi-stack semiconductor device can be achieved by replacing the lower chip 25 with the wiring substrate 1 in the above-described embodiment. In addition, the method for manufacturing a semiconductor device of the present invention may be used for a flip chip type semiconductor device as shown in FIG. In this case, the underfine material used for flip chip bonding corresponds to the uncured adhesive layer. As the underfill material, a liquid (paste-like) underfill material or a sheet-like underfill material may be used. As the thermosetting sheet-like underfill material, for example, those described in Japanese Patent Application 2005-129502 by the applicants of the present application can be used.
[0044] シート状アンダーフィル材を使用した場合における製造方法は、次の通りである。ま ず、回路面にバンプが形成された半導体ウェハを準備する。半導体ウェハの回路面 に、上記シートのアンダーフィル層（接着剤層 33)がバンプを貫通するように貼付す る。次いで、半導体ウェハの裏面に通常のダイシングテープを貼着し、これを介してリ ングフレームに固定して、ダイシング装置を用いて半導体ウェハを切断分離し、チッ プを得る。次いで、上記シートの基材のみを剥離し、バンプ頂部を露出させる。これ により、回路面が未硬化の接着剤層 33で覆われ、かつバンプ 35頂部が接着剤層 33 から突出したチップが得られる。次いで、このバンプ 35が、配線基板 34の電極部に 相対するように位置合わせをし、チップ 32と配線基板 34との導通を確保するように、 チップ 32を配線基板 34に載置する。このようにしてチップと未硬化の接着剤層 33 ( アンダーフィル材）とが積層（フリップチップボンド）された配線基板 31が得られる。  [0044] A manufacturing method in the case of using a sheet-like underfill material is as follows. First, prepare a semiconductor wafer with bumps formed on the circuit surface. Affix the underfill layer (adhesive layer 33) of the above sheet to the circuit surface of the semiconductor wafer so as to penetrate the bumps. Next, a normal dicing tape is attached to the back surface of the semiconductor wafer, fixed to the ring frame through this, and the semiconductor wafer is cut and separated using a dicing apparatus to obtain a chip. Subsequently, only the base material of the said sheet | seat is peeled and a bump top part is exposed. As a result, a chip in which the circuit surface is covered with the uncured adhesive layer 33 and the tops of the bumps 35 protrude from the adhesive layer 33 is obtained. Next, the bumps 35 are aligned so as to face the electrode portions of the wiring board 34, and the chip 32 is placed on the wiring board 34 so as to ensure conduction between the chip 32 and the wiring board 34. In this way, the wiring substrate 31 in which the chip and the uncured adhesive layer 33 (underfill material) are laminated (flip chip bond) is obtained.
[0045] 本態様においては、このようにして得られたフリップチップボンドされた配線基板を、 前述した態様と同様の（3)静圧加圧工程、 (4)熱硬化工程及び（5)組立工程が行わ れて半導体装置が製造される。本態様においては（5)組み立て工程におけるワイヤ 一ボンディング工程は不要であるため、未硬化の接着剤層 33 (アンダーフィル材）を 硬化させた後にモールディング工程を経て、半導体装置が製造される。  [0045] In this embodiment, the flip-chip bonded wiring board obtained as described above is used in the same manner as in the above-described embodiment (3) static pressure pressing step, (4) thermosetting step, and (5) assembly. The process is performed to manufacture a semiconductor device. In this embodiment, since the wire-bonding step (5) in the assembly step is unnecessary, the semiconductor device is manufactured through the molding step after the uncured adhesive layer 33 (underfill material) is cured.
[0046] [実施例]  [0046] [Example]
以下、実施例に基づいて本発明をさらに具体的に説明するが、本発明はこれらの 実施例に限定されるものではない。  EXAMPLES Hereinafter, the present invention will be described more specifically based on examples, but the present invention is not limited to these examples.
[0047] [実施例 1] [0047] [Example 1]
(1)ダイシング工程  (1) Dicing process
ダミーのシリコンウェハ (200mm径、厚さ 150 01)に、ダイシング 'ダイボンディングシ ート（リンテック社製、 Adwill LE-5003)をテープマウンター（リンテック社製、 Adwill RA D2500 m/8)を用いて貼付し、同時にリングフレームに固定した。その後、 UV照射装 置（リンテック社製 Adwill RAD 2000 m/8)を用いて基材面から紫外線を照射した。次 に、ダイシング装置（ディスコ社製、 DFD651)を使用し 8mm X 8mmのサイズのチップに ダイシングした。ダイシングの際の切り込み量は、ダイシング 'ダイボンディングシート の基材フィルムに対して 20 m切り込むようにした。 Dimming on a dummy silicon wafer (200mm diameter, 150 01 thickness) A tape mounter (manufactured by Lintec, Adwill LE-5003) was attached using a tape mounter (manufactured by Lintec, Adwill RA D2500 m / 8) and simultaneously fixed to the ring frame. Thereafter, the substrate surface was irradiated with ultraviolet rays using a UV irradiation device (Adwill RAD 2000 m / 8 manufactured by Lintec). Next, using a dicing machine (DFD651, manufactured by DISCO Corporation), dicing was performed into chips of 8 mm X 8 mm size. The amount of cut during dicing was set to cut 20 m into the base film of the dicing die bonding sheet.
(2)ダイボンド工程  (2) Die bonding process
チップをダイボンドする配線基板として、銅箔張り積層板（三菱ガス化学社製、 CCL -HL830)の銅箔に回路パターンが形成され、パターン上にソルダーレジスト (太陽ィ ンキ社製、 PSR-4000 AUS5)を有している基板（ちの技研社製）を用いた。 （1)で得ら れたシリコンチップを粘接着剤層（未硬化の接着剤層）ごとピックアップし、該配線基 板上に粘接着剤層を介して載置した後、 100°C、 300gf、 1秒間の条件で圧着 (ダイボ ンド）した。  As a wiring board for die-bonding the chip, a circuit pattern is formed on the copper foil of a copper foil-clad laminate (Mitsubishi Gas Chemical Co., Ltd., CCL-HL830), and a solder resist (Taiyo Inki Co., PSR-4000 AUS5) is formed on the pattern. ) Was used (made by Chino Giken Co., Ltd.). The silicon chip obtained in (1) was picked up together with the adhesive layer (uncured adhesive layer) and placed on the wiring board via the adhesive layer, and then 100 ° C. , 300 gf for 1 second under pressure (die bond).
(3)静圧加圧工程  (3) Static pressure application process
続!/、て、 (2)で得られたチップがダイボンドされた配線基板を加熱加圧装置 (栗原 製作所製オートクレーブ）に投入し、常圧よりも 0.5MPa大きい静圧下で、 100°C、 30 分加熱し、粘接着剤層に出現するボイドの除去を行った。  Continue! /, And then put the chip obtained in (2) die-bonded into a heating and pressurizing device (autoclave manufactured by Kurihara Seisakusho) at 100 ° C under a static pressure 0.5MPa higher than normal pressure. After heating for 30 minutes, voids appearing in the adhesive layer were removed.
(4)熱硬化工程  (4) Thermosetting process
加熱加圧装置よりダイボンドされた配線基板を取り出した後、常圧のオーブンにて 1 20°C、 1時間、続いて 140°C、 1時間の条件で加熱し、粘接着剤層を硬化させた。 After taking out the die-bonded wiring board from the heating and pressurizing device, the adhesive layer is cured by heating in a normal pressure oven at 120 ° C for 1 hour, followed by 140 ° C for 1 hour. I let you.
(5)組立工程 (5) Assembly process
封止装置 (ァピックヤマダ株式会社製 MPC-06M Trial Press)により、（3)で得られた ダイボンドされた配線基板をモールド樹脂 (京セラケミカル株式会社製 KE-1100AS3) で封止厚 400 mになるように封止した。次いで、 175°C、 5時間で封止樹脂を硬化さ せた。さらに、封止した配線基板をダイシングテープ (リンテック社製 Adwill D-510T)に 貼付し、ダイシング装置 (ディスコ社製、 DFD651)により 12mm X 12mmサイズにダイシ ングしてダミーチップによるワイヤーなしの模擬的な半導体装置を得た。  Using a sealing device (MPC-06M Trial Press manufactured by Apic Yamada Co., Ltd.), the die-bonded wiring board obtained in (3) is sealed with a mold resin (KE-1100AS3 manufactured by Kyocera Chemical Co., Ltd.) so that the sealing thickness is 400 m. Sealed. Next, the sealing resin was cured at 175 ° C. for 5 hours. In addition, the sealed wiring board is affixed to dicing tape (Adwill D-510T manufactured by Lintec), and diced to 12mm x 12mm size with a dicing device (DFD651 manufactured by Disco). Obtained a semiconductor device.
[実施例 2]〜[実施例 6] 実施例 1において、（3)静圧加圧工程における処理条件を表 1の条件に変更して 行った以外は、実施例 1と同様にして模擬的な半導体装置を得た。なお、表 1におレ て、圧力の値は、常圧よりもどれだけ大きいかで示す。 [Example 2] to [Example 6] In Example 1, a simulated semiconductor device was obtained in the same manner as in Example 1 except that the processing conditions in the (3) static pressure application step were changed to the conditions shown in Table 1. In Table 1, the pressure value indicates how much larger than the normal pressure.
[表 1]  [table 1]
【表 1】  【table 1】
Figure imgf000014_0001
Figure imgf000014_0001
[0050] [実施例 7]  [0050] [Example 7]
(3)静圧加圧工程および (4)熱硬化工程を同時に開始し同時に終了した。すなわ ち、常圧よりも 0.5MPa大きい静圧下で、 120°C、 1時間、続いて 140°C、 1時間行い、 粘接着剤層を充分に硬化させた。それ以外は実施例 1と同様にして模擬的な半導体 装置を得た。  (3) The static pressure application step and (4) the thermosetting step were started and ended simultaneously. In other words, the adhesive layer was sufficiently cured by carrying out a static pressure 0.5 MPa higher than normal pressure at 120 ° C for 1 hour, followed by 140 ° C for 1 hour. Otherwise, a simulated semiconductor device was obtained in the same manner as in Example 1.
[0051] [実施例 8] [0051] [Example 8]
ダイシング 'ダイボンディングシートを Adwill LE-5006 (リンテック社製）に変更した以 外は、実施例 1と同様にして模擬的な半導体装置を得た。  Dicing A simulated semiconductor device was obtained in the same manner as in Example 1 except that the die bonding sheet was changed to Adwill LE-5006 (manufactured by Lintec).
[0052] [実施例 9] [0052] [Example 9]
(1)ダイシング工程  (1) Dicing process
ダミーのシリコンウェハ (200mm径、厚さ 150 /i m)に、 UV硬化型ダイシングテープ (Ad will D-628リンテック社製）をテープマウンター（リンテック社製、 Adwill RAD2500 m/8 )を用いて貼付し、同時にリングフレームに固定した。次に、ダイシング装置（ディスコ 社製、 DFD651)を使用し 8mm X 8mmのサイズのチップにダイシングした。ダイシング の際の切り込み量は、基材に対して 20 m切り込むようにした。その後、 UV照射装置 (リンテック社製 Adwill RAD 2000 m/8)を用いて基材面から紫外線を照射した。 Adhere UV curing dicing tape (Ad will D-628 Lintec) to a dummy silicon wafer (200mm diameter, thickness 150 / im) using tape mounter (Lintech, Adwill RAD2500 m / 8). At the same time, fixed to the ring frame. Next, dicing equipment (disco Using a DFD651), dicing into 8mm x 8mm size chips. The amount of cut when dicing was set to cut 20 m with respect to the base material. Thereafter, the substrate surface was irradiated with ultraviolet rays using a UV irradiation device (Adwill RAD 2000 m / 8 manufactured by Lintec Corporation).
(2)ダイボンド工程  (2) Die bonding process
チップをダイボンドする配線基板として、銅箔張り積層板（三菱ガス化学社製、 CCL -HL830)の銅箔に回路パターンが形成され、パターン上にソルダーレジスト (太陽ィ ンキ社製、 PSR-4000 AUS5)を有している基板（ちの技研社製）を用いた。以下の配 合よりなるペースト状の接着剤を該配線基板上に塗布し、（1)で得られたシリコンチッ プをピックアップして、該配線基板上のペースト状の接着剤の上に載置した後、 23°C 、 100gf、 1秒間の条件で圧着（ダイボンド）した。  As a wiring board for die-bonding the chip, a circuit pattern is formed on the copper foil of a copper foil-clad laminate (Mitsubishi Gas Chemical Co., Ltd., CCL-HL830), and a solder resist (Taiyo Inki Co., PSR-4000 AUS5) is formed on the pattern. ) Was used (made by Chino Giken Co., Ltd.). A paste adhesive consisting of the following combinations is applied onto the wiring board, and the silicon chip obtained in (1) is picked up and placed on the paste adhesive on the wiring board. After that, pressure bonding (die bonding) was performed under conditions of 23 ° C., 100 gf, and 1 second.
(ペースト状接着剤の配合） (Formation of paste adhesive)
液状ビスフエノール A型骨格エポキシ樹脂（ジャパンエポキシレジン (株）社製、ェピ コート 828) : 30重量部、グリシジノレアミン型エポキシ樹脂（ジャパンエポキシレジン（株 )社製、ェピコート 630) ： 15重量部、ノポラック型エポキシ樹脂（日本化薬 (株)製、 EO CN-102S) : 5重量部、硬化剤（旭電化製、アデ力ハードナー 3636AS)を有機溶媒 (メ チルェチルケトン）に分散した溶液（固形濃度が 15%) : 5重量部、硬化促進剤（四国 化成工業製、キュアゾール 2PHZ)を有機溶媒 (メチルェチルケトン）に分散した溶液（ 固形濃度が 15%) : 10重量部  Liquid bisphenol A type skeleton epoxy resin (Japan Epoxy Resin Co., Ltd., Epicoat 828): 30 parts by weight, glycidinoreamine type epoxy resin (Japan Epoxy Resin Co., Ltd., Epicoat 630): 15 Parts by weight, nopolac-type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., EO CN-102S): 5 parts by weight, a solution in which a curing agent (manufactured by Asahi Denka, Ade force Hardener 3636AS) is dispersed in an organic solvent (methylethyl ketone) ( (Solid concentration is 15%): 5 parts by weight, curing accelerator (Shikoku Kasei Kogyo Co., Ltd. Curesol 2PHZ) dispersed in organic solvent (methyl ethyl ketone) (solid concentration is 15%): 10 parts by weight
(3)静圧加圧工程および (4)熱硬化工程  (3) Static pressure application process and (4) Thermosetting process
続いて、（3)静圧加圧工程および (4)熱硬化工程を同時に開始し同時に終了した 。すなわち、チップがダイボンドされた配線基板を加熱加圧装置 (栗原製作所製ォー トクレーブ）に投入し、 0.5MPaの静圧下で、 120°C、 1時間、続いて 140°C、 1時間行い 、加圧条件下で粘接着剤層を硬化させた。  Subsequently, (3) the static pressure application step and (4) the thermosetting step were started and ended simultaneously. In other words, the circuit board on which the chip was die-bonded was placed in a heating and pressurizing device (autoclave manufactured by Kurihara Seisakusho) and subjected to a static pressure of 0.5 MPa at 120 ° C for 1 hour, followed by 140 ° C for 1 hour. The adhesive layer was cured under pressure.
(5)封止工程 (5) Sealing process
封止装置 (ァピックヤマダ株式会社製 MPC-06M Trial Press)により、（3)で得られた ダイボンドされた配線基板をモールド樹脂 (京セラケミカル株式会社製 KE-1100AS3) で封止厚 400 mになるように封止した。次いで、 175°C、 5時間で封止樹脂を硬化さ せた。次いで、封止した配線基板をダイシングテープ (リンテック社製 Adwill D-510T) に貼付し、ダイシング装置 (ディスコ社製、 DFD651)により 12mm X 12mmサイズにダイ シングして模擬的な半導体装置を得た。 Using a sealing device (MPC-06M Trial Press manufactured by Apic Yamada Co., Ltd.), the die-bonded wiring board obtained in (3) is sealed with a mold resin (KE-1100AS3 manufactured by Kyocera Chemical Co., Ltd.) so that the sealing thickness is 400 m. Sealed. Next, the sealing resin was cured at 175 ° C. for 5 hours. Next, the sealed wiring board is diced with tape (Adwill D-510T manufactured by Lintec). A dummy semiconductor device was obtained by dicing into a 12 mm × 12 mm size with a dicing apparatus (DFD651, manufactured by DISCO Corporation).
[0053] [比較例 1] [0053] [Comparative Example 1]
静圧加圧工程〜熱硬化工程にお!/、て、ダイボンドされた配線基板を加熱加圧装置 に投入したが加圧を行わず、大気圧下で、 120°C、 1時間、続いて 140°C、 1時間加熱 し、粘接着剤層を硬化した。それ以外は実施例 1と同様にして模擬的な半導体装置 を得た。すなわち、静圧加圧工程を行わなかった以外は実施例 1と同様にして模擬 的な半導体装置を得た。  In the hydrostatic pressure process to the thermosetting process! /, The die-bonded wiring board was put into the heating / pressurizing device, but no pressure was applied and 120 ° C for 1 hour at atmospheric pressure. The adhesive layer was cured by heating at 140 ° C for 1 hour. Otherwise, a simulated semiconductor device was obtained in the same manner as in Example 1. That is, a simulated semiconductor device was obtained in the same manner as in Example 1 except that the static pressure application step was not performed.
[0054] [比較例 2] [0054] [Comparative Example 2]
実施例 9の（2)ダイボンド工程において、チップの圧着条件を 23°C、 500gf、 1秒間と した以外は、実施例 9と同様の評価を行った。なお、ダイボンド工程後の接着剤の巻 き上がりが多すぎたため、その後の工程は行わなかった。  In the (2) die bonding step of Example 9, the same evaluation as in Example 9 was performed, except that the chip pressing condition was 23 ° C., 500 gf, 1 second. In addition, since there was too much roll-up of the adhesive after the die bonding process, the subsequent process was not performed.
[0055] [評価方法] [0055] [Evaluation method]
試験 1 ; ボイドの有無の確認  Test 1; Check for voids
実施例、比較例の半導体装置の製造方法において、シリコンウェハの代わりに透 明の円板ガラス（ェヌ 'エスジー 'プレシジョン社製、直径 8インチ、厚さ 100 ^ m)を用 いて同様の操作を行った。得られたガラスチップがダイボンドされた配線基板は、接 着剤層がガラスチップ側から透視可能であり、デジタルマイクロスコープによりボイド の有無を観察した。結果を表 2に示す。  In the method of manufacturing the semiconductor device of the example and comparative example, the same operation was performed using a transparent disc glass (manufactured by ENSG Precision Co., Ltd., diameter 8 inches, thickness 100 ^ m) instead of the silicon wafer. went. The obtained wiring board on which the glass chip was die-bonded had an adhesive layer that could be seen through from the glass chip side, and the presence or absence of voids was observed with a digital microscope. The results are shown in Table 2.
[0056] 試験 2 ; 接着剤のチップ表面への巻き上がりの確認 [0056] Test 2; Confirmation of winding of adhesive onto chip surface
実施例、比較例の半導体装置の製造方法において、（3)静圧加圧工程および (4) 熱硬化工程を終えた段階でダイボンドされた配線基板の断面およびチップ表面をデ ジタルマイクロスコープにより観察して、チップ表面への接着剤の巻き上がりの有無を 確認した。結果を表 2に示す。  In the manufacturing method of the semiconductor device of Example and Comparative Example, (3) Static pressure pressurization process and (4) Cross section of die-bonded wiring board and chip surface observed after completion of thermosetting process with digital microscope Then, it was confirmed whether or not the adhesive was rolled up on the chip surface. The results are shown in Table 2.
[0057] 試験 3 ; 半導体パッケージの信頼性評価 [0057] Test 3; Reliability evaluation of semiconductor packages
実施例、比較例の半導体装置の製造方法において、（5)封止工程を終えた半導 体装置（半導体パッケージ)を 85°C、 60%RH条件下に 168時間放置して吸湿させ た後、最高温度 260°C加熱時間 1分間の IRリフロー (リフロー炉:相模理工製 WL-15 -20DNX型)を 3回行った。この後、チップと配線基板との接合部の浮き'剥がれの有 無、パッケージクラック発生の有無を、走査型超音波探傷装置 (日立建機ファインテツ ク株式会社製 Hye-Focus)による断面観察で評価した。接合部に 0. 5mm以上の剥 離を観察した場合を「剥離が発生した」と判断した。半導体パッケージ 25個にっレ、て 上記試験を行い、「剥離が発生しなかった」個数を数えた。この評価結果を表 2に示 す。 In the semiconductor device manufacturing methods of the examples and comparative examples, (5) after the semiconductor device (semiconductor package) after the sealing process was left to stand for 168 hours at 85 ° C and 60% RH to absorb moisture IR reflow with a maximum temperature of 260 ° C and a heating time of 1 minute (Reflow furnace: WL-15 manufactured by Sagami Riko) -20DNX type) was performed 3 times. After this, the cross-section observation with a scanning ultrasonic flaw detector (Hye-Focus manufactured by Hitachi Construction Machinery Finetech Co., Ltd.) was conducted to check whether the joint between the chip and the wiring board was lifted or peeled off and whether there was a package crack. evaluated. When peeling of 0.5 mm or more was observed at the joint, it was judged that “peeling occurred”. The above test was conducted on 25 semiconductor packages, and the number of “no peeling occurred” was counted. The evaluation results are shown in Table 2.
[表 2] [Table 2]
【表 2】  [Table 2]
ボイド 接着剤の巻き り Void Adhesive winding
( 2) (3) (4) ( 2) ( 3 ) (4) ^ッケ ダイボン 諍脑庄 麵匕 ダイボン 諍； 圧 麵匕  (2) (3) (4) (2) (3) (4) ^ Dicken DAIBO
ド 後 工程後 TM ド 後 後 ΪΙ後  After process After process TM After process After process
H½例 1 あり なし なし なし なし なし 2 5/2 5 識例 2 あり なし なし なし なし なし 2 5/2 5 鶴例 3 あり なし なし なし なし なし 2 5/ 2 5 実施例 4 あり なし なし なし なし なし 2 5/2 5 実沲例 5 あり なし なし なし なし なし 2 5/2 5 iG あり なし なし なし なし なし 2 5/2 5 実細 7 あり なし なし なし 2 5/2 5 実細 8 あり なし なし なし なし なし 2 5/2 5 あり なし なし なし 2 5/ 2 5 翻 1 あり 一 あり なし —— なし 1 0/ 2 5 なし ― ― あり ― ― ―  H½ Example 1 Yes No No No No No 2 5/2 5 Case 2 Yes No No No No No 2 5/2 5 Example 3 Yes No No No No No No 2 5/2 5 Example 4 Yes No No No No No 2 5/2 5 Actual example 5 Yes No No No No No 2 5/2 5 iG Yes No No No No No 2 5/2 5 Actual 7 Yes No No No 2 5/2 5 Actual 8 Yes No No No No No 2 5/2 5 Yes No No No 2 5/2 5 Reference 1 Yes One Yes No —— No 1 0/2 5 No ― ― Yes ― ― ―

Claims

請求の範囲 The scope of the claims
[1] チップと未硬化の接着剤層とが積層された配線基板を加熱して、前記未硬化の接 着剤層を硬化させて半導体装置を製造する方法であって、  [1] A method of manufacturing a semiconductor device by heating a wiring board on which a chip and an uncured adhesive layer are laminated, and curing the uncured adhesive layer,
前記硬化前に、前記チップと未硬化の接着剤層とが積層された配線基板を常圧に 対し 0. 05MPa以上の静圧により加圧する静圧加圧工程を含むことを特徴とする半 導体装置の製造方法。  A semiconductor comprising a static pressure pressing step of pressing the wiring board on which the chip and the uncured adhesive layer are laminated with a static pressure of 0.05 MPa or more against normal pressure before the curing. Device manufacturing method.
[2] 前記静圧加圧工程による加圧状態のまま、前記チップと未硬化の接着剤層とが積 層された配線基板を加熱して前記未硬化の接着剤層を硬化する熱硬化工程をさら に含むことを特徴とする請求項 1に記載の半導体装置の製造方法。  [2] A thermosetting step of curing the uncured adhesive layer by heating the wiring substrate on which the chip and the uncured adhesive layer are stacked while being pressed in the static pressure pressing step. The method of manufacturing a semiconductor device according to claim 1, further comprising:
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KR20090053954A (en) 2009-05-28
US20080066856A1 (en) 2008-03-20
KR20110131313A (en) 2011-12-06
TW200818347A (en) 2008-04-16
MY153208A (en) 2015-01-29
EP2063465A4 (en) 2012-08-08
US8545663B2 (en) 2013-10-01
CN101517720A (en) 2009-08-26

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