WO2008012871A1

WO2008012871A1 - Nonvolatile semiconductor storage device

Info

Publication number: WO2008012871A1
Application number: PCT/JP2006/314649
Authority: WO
Inventors: Yoshihiro Sato; Hiroshi Iwasa
Original assignee: Fujitsu Limited
Priority date: 2006-07-25
Filing date: 2006-07-25
Publication date: 2008-01-31
Also published as: JPWO2008012871A1; JP5012802B2

Abstract

[PROBLEMS] To provide a nonvolatile semiconductor storage device having a writing circuit of simple circuitry by which writing can be performed surely in a short time. [MEANS FOR SOLVING PROBLEMS] The nonvolatile semiconductor storage device has a resistance storage element in which switching is made between high resistance state and low resistance state by applying a voltage. The nonvolatile semiconductor storage device comprises a voltage application circuit for supplying power to the resistance storage element and generating a first voltage at one end thereof, a monitor circuit having a predetermined threshold voltage and detecting the fact that the first voltage has reached the predetermined threshold voltage, and an interruption circuit for limiting power supply from the voltage application circuit to the resistance storage element based on detection of the monitor circuit.

Description

Specification

Nonvolatile semiconductor memory device

Technical field

TECHNICAL FIELD [0001] The present invention relates to a nonvolatile semiconductor memory device using a resistance memory element whose resistance state is changed by applying an electrical stimulus.

Background art

[0002] The nonvolatile semiconductor memory device is called a RRAM (Resistance Random Access Memory), and uses a resistance memory element whose resistance state is changed by applying an electrical stimulus from the outside as a memory cell. Then, the high resistance state and the low resistance state of the resistance memory element are associated with, for example, information “0” or “1”.

[0003] As a typical example of a resistance memory element, an oxide material containing a transition metal is known. In general, a resistance memory element having the above-described characteristics changes from a high resistance state to a low resistance state. Alternatively, when the low resistance state transitions to the high resistance state, the resistance value changes greatly, and the resistance value changes abruptly. Therefore, in order to prevent the phenomenon that an excessive current flows through the resistance memory element when writing data, the RRAM needs to limit the current (current compliance) at a predetermined timing.

[0004] Conventionally, as a method for realizing such a function of current compliance, there has been proposed a method of supplying power to the resistance memory element in a pulsed manner while limiting the current to V. However, In the method, in addition to the necessity of providing a current limiting circuit, it is necessary to perform a so-called verify operation that checks whether or not the force is correctly set. As a result, the circuit becomes complicated and the circuit scale becomes large, and the write time becomes long.

[0005] In addition, as a solution to the above-mentioned drawbacks related to the write time, when the resistance value of the resistance memory element is monitored, the monitored state is fed back and the power supply to the resistance memory element is cut off! There is also a suggestion of a method! (See Patent Document 1).

[0006] According to Patent Document 1, the voltage value at one end of the resistance memory element is monitored, and the monitored result is input to the sense amplifier circuit. On the other hand, a plurality of resistance elements (reference resistors) are used to A reference voltage of the sense amplifier circuit is created, and writing is stopped when the resistance value of the resistance memory element changes to the resistance value of the predetermined reference resistance.

[0007] Patent Document 1: Japanese Patent Application Laid-Open No. 2004-234707

Disclosure of the invention

[0008] (Problems to be solved by the invention)

However, in the method described in Patent Document 1, a reference voltage is created by combining reference resistances, and therefore a reference resistor must be newly provided in addition to the sense amplifier circuit. As usual, the problem remains that the circuit becomes large-scale.

The present invention has been made in view of the above-described problems, and can be surely written in a short time and has a writing circuit having a simple circuit configuration. An object is to provide a storage device.

[0011] (Means for solving the problem)

The above problems can be solved by a novel circuit configuration using the characteristic that the resistance state of the resistance memory element changes during writing (not in flash memory or the like). The present invention has been found and the present invention has been made.

That is, at the time of writing, a high voltage is applied to the resistance memory element to change its resistance state. Then, paying attention to the voltage (within the writing circuit) that changes according to the change in the resistance state, the voltage is received by a monitor circuit having a predetermined threshold, and the resistance change is instantaneously triggered by the change in the voltage. The solution to the problem is realized by limiting the power supply to the device.

[0013] According to one aspect of the present invention, there is provided a nonvolatile semiconductor memory device having a resistance memory element that switches between a high resistance state and a low resistance state by applying a voltage, and supplies power to the resistance memory element. And a voltage applying circuit for generating a first voltage at one end of the resistance memory element, and a predetermined threshold voltage, and detecting that the first voltage has reached the predetermined threshold voltage. There is provided a non-volatile semiconductor memory device having a monitor circuit and a cutoff circuit for restricting power supply from the voltage applying circuit to the resistance memory element based on the detection of the monitor circuit.

[0014] Further, according to another aspect of the present invention, a high resistance state and a low resistance state by application of a voltage A non-volatile semiconductor memory device having a resistance memory element that is switched between when the resistance memory element is in a high-resistance state, the power source is supplied to the resistance memory element, and a first end of the resistance memory element is A first voltage applying circuit for generating a voltage; and a power supply to the resistance memory element when the resistance memory element is in a low resistance state, and a second voltage lower than the first voltage at one end of the resistance memory element. A second voltage applying circuit for generating the first voltage, a first monitor circuit having a predetermined threshold voltage and detecting that the first voltage has reached the first threshold voltage; A second monitor circuit having a predetermined threshold voltage and detecting that the first voltage has reached the second threshold voltage; and based on the detection of the first monitor circuit. Shuts off the current supply from the first voltage application circuit to the resistance memory element. And a second cutoff circuit that cuts off the voltage application to the resistance memory element based on the detection of the second monitor circuit. A non-volatile semiconductor memory device is provided.

[0015] According to another aspect of the present invention, there is provided a non-volatile semiconductor memory device having a resistance memory element that switches between a high resistance state and a low resistance state by application of a voltage, and a power source is supplied to the resistance memory element. And a voltage application circuit for generating a first voltage at a predetermined location of a memory cell including the resistance memory element, and a predetermined threshold voltage, the first voltage being a predetermined threshold! /, Value There is provided a non-volatile semiconductor memory device that includes a monitor circuit that detects that the voltage has been reached, and that limits power supply from the voltage application circuit to the resistance memory element based on the detection of the monitor circuit .

[0016] (Effect of the invention)

According to the present invention, at the time of writing, a high voltage is applied to the resistance memory element to change its resistance state. Then, paying attention to the voltage that changes according to the change in the resistance state (in the write circuit), the current supply to the resistance memory element is instantaneously limited by using the predetermined change in the voltage as a trigger, Thus, reliable writing can be performed, and such writing processing can be realized with a simple circuit.

[0017] It is also possible to easily design a circuit using a general-purpose design tool and design technique in a semiconductor process.

Brief Description of Drawings [0018] FIG. 1 is a graph showing the current-voltage characteristics of a resistance memory element using a unipolar resistance memory material.

FIG. 2 is a diagram showing a basic configuration of a memory cell in a nonvolatile semiconductor memory device

FIG. 3 is a circuit diagram showing a memory cell array 20 in which memory cells 10 are arranged in a matrix.

FIG. 4 is a block diagram illustrating a schematic configuration of a peripheral circuit according to the first embodiment.

FIG. 5 is a circuit diagram illustrating an example of a set driver circuit according to the first embodiment.

FIG. 6 is a timing chart illustrating a write operation of the set driver circuit according to the first embodiment.

FIG. 7 is a circuit diagram illustrating an example of a reset driver circuit according to the first embodiment.

FIG. 8 is a timing chart showing a write operation of the reset driver circuit according to the first embodiment.

FIG. 9 is a graph showing the relationship between the ratio of the gate width of nMOS to the gate width of pMOS and the threshold voltage of the input section in the input section of the monitor circuit having a CMOS structure.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, details according to embodiments of the present invention will be described with reference to the drawings.

[0020] (Example 1)

Basic operation of resistive memory elements

First, the basic operation of a resistance memory element using a unipolar resistance memory material will be described with reference to the drawings. Fig. 1 is a graph showing the current-voltage characteristics of a resistance memory element using a unipolar resistance memory material. This graph shows the case of using TiO, which is a typical example of a unipolar resistive memory material.

[0021] Let the initial state of the resistance memory element be point a. When the applied voltage is gradually increased from point a, the current gradually increases along curve A. When the applied voltage further increases and exceeds approximately 1.5V (point b in the figure), the resistance memory element switches (sets) to the low resistance state as well as the high resistance state force. Accordingly, the absolute value of the current increases rapidly, and the current-voltage characteristic transitions from the high resistance state of curve A to the low resistance state shown by curves C and D. Note that the current value from point b to point c is constant at 2mA (straight line B), but this is due to current limitation. That is, the resistance memory element has already transitioned to the low resistance state at the time point b.

[0023] Therefore, if the current limit is removed, a large current of the value obtained when the curve D is extended to 1.5 V beyond the point d will flow to the resistance memory element. May be damaged.

Next, the current limitation is removed at the time point c. Then, as the voltage is gradually decreased from point c, the current changes along the curve C in the direction of the arrow, and its absolute value gradually decreases. Conversely, when the applied voltage is gradually increased again, the current changes along the curve D in the direction of the arrow, and its absolute value gradually increases.

[0025] When the applied positive voltage is further increased and exceeds about 0.7 V (d point), the resistance memory element switches (resets) from the low resistance state to the high resistance state. Along with this, along the curve E, the absolute value of the current sharply decreases, and the current-voltage characteristics transition from the d point to the e point.

[0026] After the transition to point e, the current changes along curve A as the state force voltage at point e decreases or increases. As long as the voltage does not exceed point b, this resistance memory element remains in a high resistance state.

[0027] As described above, when TiO is used as the resistance memory element, the current-voltage characteristics follow curve A in the high resistance state if the applied voltage is lower than the voltage at point b (about 1.5V). Changes linearly and maintains a high resistance state. Similarly, in the low resistance state, if the applied voltage is lower than the voltage at point d (approximately 0.7V), the current-voltage characteristics change along curve C, and the low resistance state is maintained.

[0028] That is, even if the resistance state of the resistance memory element is! /, It is stable if the applied voltage to the resistance memory element is lower than a predetermined voltage (here, for example, 0.7V), Even if the power is turned off, the current resistance state is maintained.

[0029] Note that, when a resistance memory element is formed using the above materials, characteristics as shown in FIG. 1 cannot be obtained in an initial state immediately after the element formation. In order to make a resistance memory material reversibly changeable between a high resistance state and a low resistance state, a process called forming is performed. In some cases it is necessary. In forming, a voltage higher than the set voltage is applied to the resistance memory material. Once the forming is performed, the resistance memory element does not return to the initial state.

[0030] Basic configuration of memory cell

Next, the basic configuration of the memory cell in the nonvolatile semiconductor memory device will be described with reference to FIG. FIG. 2A is a circuit diagram showing a memory cell in the nonvolatile semiconductor memory device, and FIG. 2B is a schematic sectional view showing a structure of the memory cell in the nonvolatile semiconductor memory device. FIG. 2 shows a configuration common to the conventional nonvolatile semiconductor memory device and the nonvolatile semiconductor memory device of this embodiment.

The memory cell 10 of the nonvolatile semiconductor memory device includes a resistance memory element 12 and a cell selection transistor 14 as shown in FIG. The resistance memory element 12 has one end connected to the bit line BL and the other end connected to the drain D of the cell selection transistor 14. The source S of the cell selection transistor 14 is connected to the source line SL, and the gate G is connected to the word line WL.

As shown in FIG. 2 (b), the resistance memory element 12 has a resistance memory material 12b sandwiched between a pair of electrodes (12a, 12c). Here, the resistance memory material 12b is, for example, a unipolar resistance memory material having a TiO force. In FIG. 2 (b), the bit line BL extends parallel to the paper surface, and the source line SL and the word line WL extend toward the back, that is, perpendicular to the paper surface. RU

FIG. 3 is an example of a circuit diagram showing a memory cell array 20 in which the memory cells 10 shown in FIG. 2 are arranged in a matrix. Thus, the plurality of memory cells 10 are arranged adjacent to each other in the column direction (vertical direction in the drawing) and the row direction (horizontal direction in the drawing).

[0034] A plurality of word lines WL1, * WL1, WL2, * WL2 ',... Are arranged in the row direction, and are connected to the memory cells 10 arranged in the row direction. In the same row direction, source lines SL1, SL2,... Are arranged and connected to the memory cells 10 arranged in the row direction. In this figure, the number of source lines equal to or greater than the number of word lines is provided in relation to the amount of power supply noise, etc., in which one source line is provided for every two word lines. It's okay. A plurality of bit lines BL1, BL2, BL3, BL4-... Are arranged in the column direction, and are connected to the memory cells 10 arranged in the column direction. Each bit line BL is provided with a bit line selection transistor 16 having a function as a variable resistance element.

[0036] Peripheral circuit for one write 'read'

Next, a peripheral circuit that performs processing such as writing to the memory cell described so far will be described. FIG. 4 is a block diagram illustrating a schematic configuration of the peripheral circuit according to the first embodiment.

As shown in FIG. 4, the peripheral circuit for the memory cell array 20 described above includes a set driver circuit 30 and a reset driver circuit 40 that write data to the memory cell 10, and data reading from the memory cell 10. The reading circuit 28 for performing the above and the control circuit 26 for controlling these circuits are also configured.

[0038] In addition to the memory cells (MSll to MSij) arranged in an array, the memory cell array 20 includes a word line selector 22 for selecting the word line WL and a bit line selector for selecting the bit line BL. 24 is also included. The memory cell portion in the memory cell array 20 corresponds to, for example, a circuit similar to the circuit shown in FIG. 3 described above. In FIG. 4, for convenience of illustration, this memory cell portion is included in the circuit. The wiring is partially omitted.

The memory cell 10 is selected by the word line selector 22 and the bit line selector 24. The word line selector 22 and the bit line selector 24 are also connected to the address line 25. Address setting to the address line 25 is performed by the control circuit 26.

[0040] <Set driver circuit>

The set driver circuit 30 includes a voltage application circuit 32 that applies a predetermined voltage (and current) to the memory cell 10 selected at the time of writing, a monitor circuit 34 that detects the voltage of the bit line, and a monitor circuit 34. In response to this notification, the power supply to the memory cell 10 is cut off.

[0041] The set driver circuit 30 has a precharge circuit 38 that sets the voltage of the bit line BL to a predetermined value before writing. The precharge circuit 38 avoids a malfunction in the writing process.

[0042] <Reset driver circuit> The reset driver circuit 40 includes a voltage application circuit 42 that applies a predetermined voltage (and current) to the memory cell 10 selected at the time of writing, and a monitor circuit 4 that detects the voltage of the bit line.

4 and a shut-off circuit 46, which receives the notification from the monitor circuit 44 and shuts off the power supply to the memory cell 10, is also configured.

In addition, the reset driver circuit 40 includes a precharge circuit 48 that sets the voltage of the bit line BL to a predetermined value before writing. The precharge circuit 48 avoids malfunctions in the write process.

[0044] Ku control circuit>

The control circuit 26 includes a CPU (Central Processing Unit) 26a, a memory 26b that stores a control program for the CPU 26a, a bus 26c that transmits signals between them, and the like.

[0045] The control circuit 26 has the above-described configuration, and controls the write operation in the set driver circuit 30 and the reset driver circuit 40 via (via) the control signals 27a and 27b. The read operation in the read circuit 28 is controlled by the control signal 27c. At that time, the control circuit 26 also controls the memory cell array 20 by the control signal 27d.

[0046] <Readout circuit>

The read circuit 28 includes a sense amplifier (not shown), and the voltage of the bit line BL is measured by the sense amplifier to recognize the storage state of the selected memory cell.

[0047] One example of circuit configuration of one set driver circuit

Next, individual blocks of the circuit shown in FIG. 4 (memory cell array 20 and its peripheral circuits) will be described with reference to the drawings. First, the set driver circuit 30 will be described. FIG. 5 is a circuit diagram illustrating an example of a set driver circuit according to the first embodiment.

[0048] Memory Memory Array>

As shown in the figure, the memory cell array 20 is arranged between the bit line BL and the reference voltage Vss. In this figure, for convenience of illustration, only one of the many memory cells existing in the memory cell array 20 is shown as a representative. Other memory cells are arranged in parallel with the memory cell 10 shown in the figure. In the memory cell 10, as shown in the figure, the resistance memory element 12 and the cell selection transistor 14 (TR11) are connected in series. Specifically, one end of the resistance memory element 12 is connected to the bit line BL, and the other end is connected to the drain D of TR11. The source S of TR11 is connected to the reference voltage Vss, and the gate G of TR11 is connected to the word line WL.

The resistance value of the resistance memory element 12 is several kΩ in the low resistance state, and several ten Ω to 1000 kQ in the high resistance state. Unlike a normal resistor, the resistance memory element 12 has a very small area dependency on the resistance value.

[0051] Since the cell selection transistors 14 connected in series to the resistance memory element 12 need to be provided in the same number as the resistance memory elements 12, it is desirable that the area be as small as possible.

As an example of the cell selection transistor 14 having a small area, a structure in which the ratio of the gate width to the gate length is 2.8 (gate width = 0.5 umZ gate length = 0.18 um) is conceivable. When such a structure is used, it is possible to form the cell selection transistor 14 having an on-resistance of about 2 kΩ. When such a cell selection transistor 14 is used, the resistance value in the low resistance state is about 4 kΩ (and the maximum current during the reset operation) so that the necessary voltage is applied to the cell selection transistor 14. It is desirable to use a resistance memory element 12 that has a current of about several hundred A.

[0053] <Set voltage application circuit>

As shown in FIG. 5, the set voltage application circuit 32 includes a current mirror circuit having TR32 and TR33. The current mirror circuit is a stable power supply connected to the power supply Vdd. In the current mirror circuit, the end opposite to the side connected to the power supply Vdd is connected to the drain D of the bit line BL and TR31 as shown in the figure.

Here, in order to increase the memory capacity density of the nonvolatile semiconductor device, the cell selection transistor 14 (TR11) in the memory cell 10 is an nMOS, and the transistors (TR32, TR33 constituting the current mirror circuit). ) Is preferably pMOS.

TR31 is provided between the set voltage application circuit 32 and a cutoff circuit 36 described later, and enables the operation of the set driver circuit 30 at the time of writing. The drain D of TR31 is connected to the source S of TR32, that is, the node N1, and the source 3 of Ding 1 ^ 31 is connected to the cutoff circuit 36 (specifically, the drain D of TR34). Also, TR31 gate G allows write Connected to the set write enable signal SetWE. When performing the writing process, set the SetWE signal in advance to a high level (for example, approximately 1.5 to 1.7 V).

[0056] <Cutoff circuit>

As shown in the figure, the cutoff circuit 36 is provided between the aforementioned TR31 and the reference voltage Vss. The cutoff circuit 36 includes, for example, a transistor TR34 disposed between TR31 and the reference voltage Vss, and its drain D is connected to the source S of TR31. The source S of TR34 is connected to the reference voltage Vss, and the output of the monitor circuit 34 is connected to the gate G of TR34. Note that the reference voltage Vss may be set to a ground (GND) level, for example. The transistor TR 34 has, for example, an nMOS structure.

[0057] <Monitor circuit>

The monitor circuit 34 includes, for example, two inverters IN11 and IN12 connected in series as shown in the drawing. The input of inverter IN11 is connected to bit line BL, and its output is connected to the input of inverter IN12. As described above, the output of the inverter IN12 is connected to the gate G of the transistor TR34 constituting the cutoff circuit 36.

[0058] Here, for the inverter INI 1 connected to the bit line BL! /, The threshold voltage (threshold voltage) is set to a value that can be recognized as the transition to the low resistance state. To do. The threshold value of this IN11 is, for example, 1. OV to l. 2V. The optimum value depends on the material of the resistance memory element 12 and the characteristics of the peripheral circuit of the resistance memory element 12. decide. There is no particular limitation on the subsequent inverter IN12.

In this specification, “threshold! /, Value voltage” and “threshold voltage” are used as synonymous terms.

The inverter IN11 has a CMOS structure input section (not shown) in which, for example, a pMOS transistor and an nMOS transistor are also formed. The threshold voltage of this input section becomes the threshold voltage of the monitor circuit 34.

Here, the relationship between the configuration of the CMOS structure and the threshold voltage will be described. FIG. 9 is a graph showing the relationship between the ratio of the nMOS gate width to the pMOS gate width and the threshold voltage of the input section in the input section of the monitor circuit having a CMOS structure. It is fu.

As shown in FIG. 9, the threshold voltage can be controlled by changing the ratio of the gate width of the nMOS and the gate width of the pMOS. Specifically, by setting the ratio of the gate width of the nMOS to the gate width of the pMOS greater than 1, that is, by making the gate width of the pMOS wider than the gate width of the nMOS, the threshold voltage is changed from 1.0 V to 1. It can be 2 V.

[0063] When the gate width of the nMOS is 0.36 μm and the gate width of the pMOS is 7.2 m under the predetermined wiring rule, the threshold voltage should be about 1. IV. Is possible.

[0064] In this figure, in order to adjust the force timing in which the monitor circuit 34 includes two inverters, an example in which four or more even number inverters may be connected in series. .

[0065] <Precharge circuit>

As shown in the figure, the precharge circuit 38 is provided between the power supply Vdd and the bit line BL. The precharge circuit 38 is disposed between, for example, the bit line BL and the power supply Vdd, has a transistor TR35 having a pMOS structure, and the drain D of TR35 is connected to the power supply Vdd. The gate G of TR35 is connected to the control signal PrSET from the control circuit 26, and the source S of TR35 is connected to the bit line BL.

[0066] Write operation of one set driver circuit

Next, the write operation of the set driver circuit 30 will be described. FIG. 6 is a timing chart illustrating the write operation of the set driver circuit according to the first embodiment.

[0067] Step 1: First, the bit line BL is precharged. In other words, the set precharge signal PrSET is set to Low level to turn on TR35 so that the bit line BL has substantially the same voltage value as the power supply Vdd. The voltage of the power supply Vdd is about 1.8V, for example.

As described above, the precharge circuit 38 determines one end of the resistance memory element 12 at a predetermined voltage before applying a voltage to the resistance memory element 12.

[0069] Step 2: Next, the SetWE signal is enabled in this state. That is, the SetWE signal is set to High level to turn on TR31. At this time, already after step 1 precharge Since TR34 is in the on state, when TR31 is turned on, the voltage value of node N1 drops significantly, and a large current easily flows through the path of L1.

As a result, the current mirror circuit is activated, and a large current easily flows through the L2 path. However, in this state, since TR11 which is the cell selection transistor 14 is in an OFF state, a large current does not flow through the path L2, and a high voltage is not applied to the resistance memory element 12. (In other words, the resistance memory element 12 is still in a high resistance state.) At this point, TR35 is turned on by the precharge in step 1, and the voltage value of the bit line BL is equal to the power supply Vdd. The values are approximately the same (approximately 1.6 V to 1.8 V).

Step 3: Next, precharge of the bit line BL is stopped. In other words, the set precharge signal PrSET is returned to the high level (for example, about 1.5V to 1.8V), and TR35 is turned off.

As described above, the precharge circuit 38 turns on the internal transistor TR35 to set one end of the resistance memory element 12 to a predetermined voltage, and then turns off the transistor 35 to stop the precharge.

Step 4: Next, the memory cell 10 to be written is selected. That is, the control circuit 26 designates an address for the address line 25 and enables the word line WL of the memory cell 10. As a result, the word line WL becomes a high level (for example, 1.5 to 1.7 V), and the cell selection transistor TR11 is turned on. At the same time as TR11 is turned on, a high voltage (for example, about 1.6 V) that can be set to the resistance memory element 12 is applied. The voltage applied to the resistance memory element is shown in the graph “VR” in FIG.

Step 5: Next, the resistance memory element 12 is set. That is, when a high voltage that can be set is applied for a predetermined time (several ns to 50 ns), the resistance memory element 12 enters the set state, and the resistance memory element 12 rapidly changes to the low resistance state in addition to the high resistance state force. To do.

In this way, the voltage application circuit 32 applies a voltage capable of switching the resistance state of the resistance memory element 12 to both ends of the resistance memory element 12, and then (switches the resistance state). The resistance state is switched after a predetermined time has elapsed (after a voltage capable of being applied) is applied.

Step 6: Next, the set state is detected by the monitor circuit. That is, resistance memory element When the child 12 transitions to the low resistance state, the voltage of the bit line BL rapidly decreases accordingly. When the voltage value of the bit line BL becomes lower than the threshold voltage of the inverter IN11 in the monitor circuit 34 (for example, about 1. OV to l.2V), the monitor circuit 34 is activated.

[0077] With respect to the threshold voltage of the inverter IN11, in order to increase the sensitivity of the monitor circuit 34, the resistance memory element 12 is in the middle of transition to the low resistance state, that is, after the resistance state starts to be switched. It is desirable to set so that the voltage value of the bit line BL reaches the threshold voltage value of the inverter IN11 before the switching is completed.

The monitor circuit 34 changes (inverts) the logic of an internal logic element when the voltage of the bit line BL reaches a predetermined threshold voltage value. In other words, when the voltage value is low level, it changes from low level to high level, and when the voltage value is high level, it changes from high level to low level.

Step 7: Next, power supply to the resistance memory element 12 is cut off. That is, the monitor circuit 34 detects the set of the resistance memory element 12, and changes the output signal StatSET power Low level (for example, about 0V to 0.5V) of the monitor circuit. This StatSET can notify the completion of setting to the outside. When the StatSET signal goes low, TR34 in the cutoff circuit 36 turns off and the current in the L1 path is cut off.

Then, the current mirror circuit in the set voltage application circuit 32 is activated, and the current flowing through the path L2 is interrupted. In the case of setting, the time from when the resistance state of the resistance memory element 12 is switched to when the current in the path L1 is cut off is several ns to several tens ns.

As described above, the cutoff circuit 36 limits the current of the current limiting circuit that limits the amount of current supplied to the resistance memory element. Here, the current limiting circuit is the current mirror circuit, and the blocking circuit 36 limits the amount of current supplied to the resistance memory element by blocking one current path in the current mirror circuit.

By the steps as described above, writing to set (set) the resistance memory element 12 to the low resistance state is surely performed.

[0083] The write operation when the resistance memory element 12 is initially in the high resistance state is described above. I am clear. In order to simplify the circuit, when the above-described writing is performed on the resistance memory element 12 in the low resistance state, the low resistance state does not change and the low resistance state is maintained as it is. ! / I want to talk ヽ.

Regarding this point, when the resistance memory element 12 is in the low resistance state by the current limiting function of the current mirror circuit, the voltage value applied to the resistance memory element 12 is a value at which the resistance state does not change (for example, 0.6 V The following). Therefore, when writing is performed in the steps as described above, the resistance state of the resistance memory element 12 remains unchanged. The set completion is immediately notified to the outside while maintaining the low resistance state.

One circuit configuration example of one reset driver circuit

Next, the reset driver circuit 40 will be described. FIG. 7 is a circuit diagram illustrating an example of a set driver circuit according to the first embodiment.

[0085] Memory Memory Array>

Since the memory cell array 30 has already been described in the section of the set driver circuit, its description is omitted here.

[0086] <Reset voltage application circuit>

As shown in FIG. 7, the reset voltage application circuit 42 is configured by a current mirror circuit having TR42 and TR43. The current mirror circuit is a stable power supply connected to the power supply Vdd. In the current mirror circuit, the end opposite to the side connected to the power supply Vdd is connected to the drain D of the bit line BL and TR41 as shown in the figure.

[0087] Here, in order to increase the memory capacity density of the nonvolatile semiconductor device, the cell selection transistor 14 (TR11) in the memory cell 10 is an nMOS and the transistors (TR42, TR43) constituting the current mirror circuit. ) Is preferably pMOS.

TR41 is provided between the reset voltage application circuit 42 and a cutoff circuit 46 described later, and enables the operation of the reset driver circuit 40 at the time of writing. The drain D of TR41 is connected to the source S of TR42, ie, the node N2, and the source 3 of Ding 1 ^ 41 is connected to the cutoff circuit 46 (specifically, the drain D of TR44). The gate G of TR41 is connected to a reset write enable signal ResetWE that permits writing. Write process In this case, this ResetWE signal is set to a high level (for example, about 1.5 to 1.7 V) in advance.

[0089] <Circuit circuit>

As shown in the figure, the cutoff circuit 46 is provided between the aforementioned TR41 and the reference voltage Vss. The cutoff circuit 46 includes, for example, a transistor TR44 disposed between TR41 and the reference voltage Vss, and its drain D is connected to the source S of TR41. The source S of TR44 is connected to the reference voltage Vss, and the output of the monitor circuit 44 is connected to the gate G of TR44. The transistor TR44 has, for example, an nMOS structure.

[0090] <Monitor circuit>

The monitor circuit 44 has, for example, one inverter IN21 and a flip-flop circuit FF as shown in the figure. The input of inverter IN21 is connected to bit line BL, and its output is connected to one input of flip-flop circuit FF.

Here, the inverter IN21 is set to a value at which the threshold voltage can be recognized as having transitioned to the high resistance state. The threshold voltage of IN21 is, for example, 1.0 V to 1.2 V, but the optimum value is determined according to the material constituting the resistance memory element 12 and the characteristics of the peripheral circuit of the resistance memory element 12. To do.

The inverter IN21 has, for example, a pMOS structure transistor and an nMOS structure transistor, and a CMOS structure input section (not shown). The threshold voltage voltage monitor circuit 44 threshold of the input section is provided. Become a voltage. Note that. Since the relationship between the CMOS structure form of the inverter IN21 and the threshold voltage is the same as that of the monitor circuit in the set driver circuit, description thereof is omitted here.

The flip-flop circuit FF is composed of, for example, two NAND circuits (NA1, NA2). The output of this flip-flop circuit FF is connected to the gate G of TR44 in the cutoff circuit 46. The output of the inverter IN21 is connected to one input of the flip-flop circuit FF, and the X-StartRESET signal is connected to the other input. X—Star tRESET signal sets the output (StatRESET signal) of flip-flop circuit FF to High level.

[0094] The flip-flop circuit FF has completed the write operation by the reset driver circuit 40. After that, when the voltage of the bit line BL drops, TR44 of the cutoff circuit 46 is turned on again due to the voltage change, and the reset driver circuit 40 is prevented from restarting.

Here, a basic operation of the flip-flop circuit FF will be described. First, set the X-StartRES ET signal to low level and then back to high level, and then set the StatRESET signal to high level. Next, when the write operation increases the voltage of the bit line BL and the voltage of the bit line BL exceeds the threshold voltage value of the input of the inverter IN21, the StatRESET signal changes from the high level to the low level.

[0096] After that, for example, even if the voltage of the bit line BL falls and falls below the threshold voltage value of the input of the inverter IN21, the voltage level of the StatRESET signal is at the ow level, so the NAND circuit The output of NA2 does not change, and the internal logic of flip-flop circuit FF does not change. In other words, the output logic of the flip-flop circuit FF is not changed, and the voltage of the StatRESET signal (input signal to the gate G of TR44) is held at the low level.

[0097] To perform a write operation again, change the X-StartRESET signal from High to Low and return the StatRESET signal to High. When the StatRESET signal becomes high level, the X—StartRESET signal is returned to high level (from low level). As described above, the X-StartRESET signal has a function for setting the flip-flop circuit FF to the initial state (initial standby) and enabling the operation again.

As described above, the monitor circuit 44 functions as a stable operation circuit that prevents the logic from changing again after the voltage of the bit line BL reaches a predetermined threshold voltage and the internal logic changes. It has a function. Further, the monitor circuit 44 has a function of enabling the unlocking of the logic from the outside as required by the X-StartRESET signal.

[0099] In this figure, three or more odd-numbered inverters are connected in series in order to adjust the 1S timing in which one inverter is included in the monitor circuit 34. Also good.

[0100] <Precharge circuit>

As shown in the figure, the precharge circuit 48 is provided between the bit line BL and the reference voltage Vss. It is done. For example, the precharge circuit 48 is disposed between the bit line BL and the reference voltage Vss, and includes a transistor TR45 having an nMOS structure, and the drain D of TR45 is connected to the bit line BL. The TR45 gate G is connected to the control signal PrRES ET from the control circuit 26, and the TR45 source S is connected to the reference voltage Vss.

[0101] One reset driver circuit write operation

Next, the write operation of the reset driver circuit 40 will be described. FIG. 8 is a timing chart illustrating the write operation of the reset driver circuit according to the first embodiment.

[0102] Step 1: First, precharge the bit line BL. That is, the reset precharge signal PrRESET is set to a high level (for example, about 1.5 to 1.8 V) to turn on TR45 so that the bit line BL has substantially the same voltage value as the reference voltage Vss. As described above, the precharge circuit 48 determines one end of the resistance memory element 12 at a predetermined voltage before the voltage is applied to the resistance memory element 12, and prevents malfunction of the circuit.

[0103] At this time, the X-StartRESET signal is changed from the High level to the Low level, and the StatRESET signal is changed from the Low level to the High level.

[0104] Note that either the PrRESET signal or the X-StartRESET signal will be faster than the other signals because of wiring delays, transistor characteristic variations, etc.! To do.

[0105] Step 2: Next, the memory cell 10 to be written is selected. That is, the control circuit 26 designates an address for the address line 25 and enables the word line WL of the memory cell 10. As a result, the word line WL becomes a high level (for example, 1.5 to 1.7 V), and the cell selection transistor TR11 is turned on.

[0106] Step 3: Next, the ResetWE signal is enabled. That is, the ResetWE signal for enabling the reset driver circuit 40 is set to a high level (for example, about 1.5 to 1.7 V) to turn on TR41. At this time, the transistor TR45 of the precharge circuit 48, the TR44 of the cutoff circuit 46, and the TR11 of the memory cell 10 are already in the ON state by the processing of Step 1 and Step 2, so that TR41 is turned on. The current mirror circuit is activated and a large current begins to flow through the L4 path.

[0107] However, in this state, the transistor TR45 of the precharge circuit 48 is on. Current flows through the precharge circuit 48 side, and almost no current flows through the LO path on the memory cell 10 side. Therefore, at this time, the voltage of the bit line BL is hardly changed, and the voltage value of the bit line BL is maintained substantially the same value (about OV to 0.5 V) as the reference voltage Vss. As a result, no high voltage is applied to the resistance memory element 12, and the resistance memory element 12 maintains a low resistance state.

[0108] Step 4: Next, precharge of the bit line BL is stopped. In other words, the PrRESET signal is returned to the low level, TR45 is turned off, and the precharge is stopped. In addition, the precharge is stopped and the X-StartRESET signal is changed from low level to high level. At the same time as TR11 is turned on, a high voltage (approximately 0.9 V) that can be set to the resistance memory element 12 is applied. The voltage applied to the resistance memory element is shown in the graph “VR J” in FIG.

Step 5: Next, the resistance memory element 12 is reset. When the resettable high voltage is applied for a predetermined time, the resistance memory element 12 is reset, and the resistance memory element 12 rapidly changes from the low resistance state to the high resistance state. The time required for the resistance memory element 12 to reset (the predetermined time) varies depending on conditions, and is usually several hundred ns to several tens of ms, but here, for example, 800 ns as shown in FIG.

In this way, the voltage application circuit 42 applies a voltage capable of switching the resistance state of the resistance memory element 12 to both ends of the resistance memory element 12, and (the resistance state can be switched). After a predetermined time (after the voltage is applied), the resistance state is switched.

[0111] Step 6: Next, the reset state is detected by the monitor circuit. That is, when the resistance memory element 12 transitions to the high resistance state, the voltage of the bit line BL rises accordingly. When the voltage value of the bit line BL becomes higher than the threshold voltage of the inverter IN21 in the monitor circuit 44 (for example, about 1. OV to l.2V), the monitor circuit 44 is activated. At this time, the StatRESET signal can be used to notify the outside that the reset has been completed.

[0112] In this way, with respect to the threshold voltage of the inverter IN21, in order to increase the sensitivity of the monitor circuit 44, the resistance state starts to switch during the transition of the resistance memory element 12 to the low resistance state. And before the switching is over, the bit line BL It is desirable to set so that the voltage value of reaches the threshold voltage of inverter IN21.

In the monitor circuit 44, when the voltage of the bit line BL changes from low level to high level and reaches a predetermined threshold voltage value, the logic of the internal logic element changes (inverts).

Step 7: Next, power supply to the resistance memory element 12 is cut off. That is, the monitor circuit 44 detects the reset of the resistance memory element 12, and the output signal StatRESET of the monitor circuit changes from the high level to the low level (for example, about OV to 0.5V). When the StatRESE T signal changes to Low level, TR44 in the cutoff circuit 46 is turned off, and the current in the L3 path is cut off.

[0115] Then, the current mirror circuit in the voltage application circuit 42 is activated, and the current flowing through the path L4 is interrupted. In the case of reset, the time from when the resistance state of the resistance memory element 12 is switched to when the current in the path L4 is cut off is several ns to several tens ns.

As described above, the cutoff circuit 46 limits the current of the current limiting circuit that limits the amount of current supplied to the resistance memory element. The current limiting circuit is, for example, the current mirror circuit as shown in FIG. 7, and the cutoff circuit 46 cuts off one of the current paths in the current mirror circuit to thereby supply the current amount to the resistance memory element. Limit.

[0117] After that, when the current in the L3 path is cut off, the voltage level of the bit line BL, which has been rising, decreases and falls below the threshold voltage value of the inverter IN21. Because of the low level, the output of the NAND circuit NA2 does not change, and the logic inside the flip-flop circuit FF does not change. That is, the logic of the output of the flip-flop circuit FF does not change and is held at the voltage power ow level of the StatRESET signal (input signal to the gate G of TR44).

[0118] By the steps as described above, writing to reset (reset) the resistance memory element 12 is performed reliably.

[0119] The write operation when the resistance memory element 12 is initially in the low resistance state has been described above. In order to simplify the circuit, when writing as described above to the resistance memory element 12 in the high resistance state, the high resistance state does not change, and the high resistance state remains unchanged. Please hold it!

[0120] Regarding this point, for example, when the resistance memory element 12 is in a high resistance state from the beginning, the voltage of the bit line BL is monitored immediately after applying a high voltage to the resistance memory element 12 in Step 4. It becomes higher than the threshold voltage value of circuit 21. Therefore, it can be realized by adjusting the power supply to the resistance memory element 12 to be instantaneously cut off in a time shorter than the time when the resistance state of the resistance memory element 12 changes (for example, several ns). It is. Also, immediately notify the outside of the reset completion.

[0121] As described above, according to the present embodiment, the write circuit to the resistance memory element is combined with an element mainly composed of a field effect transistor (MOS FET: Metal Oxide Semiconductor Field Effect Transistor). Therefore, it is possible to easily manufacture a non-volatile memory device by using the conventional process for forming CMOS.

[0122] Further, it is not necessary to provide a diffused resistor or a polysilicon resistor that requires a predetermined size according to the resistance value as the reference resistor. Therefore, a large scale circuit can be avoided, which is suitable for use as a large-capacity memory.

[0123] Furthermore, since the current supply source is instantaneously cut off before a large current flows through the resistance memory element 12, there is an advantage that a simple circuit is sufficient!

Explanation of symbols

[0124] 10 · · · Memory cells

12 · · · Resistance memory element

12a, 12c pairs of electrodes

12b ... Resistance memory material

14 ... cell selection transistor

16 bit line selection transistor

20 ... Memory cell array

2 ₂ ... Word line selector

24 bit line selector

25 ... Address line .... Control circuit

a --- CPU

b ... Memory

c ... Nos

a, 27b, 27c, 27d ... Control signal ... Readout circuit

... Set driver circuit

, 42 ... Voltage application circuit

44 Monitor circuit

, 46 ... Shut-off circuit

48 ... Precharge circuit ... Reset driver circuit

Claims

The scope of the claims

[1] In a nonvolatile semiconductor memory device having a resistance memory element that switches between a high resistance state and a low resistance state by application of a voltage,

A voltage application circuit that supplies power to the resistance memory element and generates a first voltage at one end of the resistance memory element;

A monitor circuit having a predetermined threshold voltage and detecting that the first voltage has reached a predetermined threshold voltage;

And a cutoff circuit that restricts power supply from the voltage application circuit to the resistance memory element based on the detection of the monitor circuit.

A non-volatile semiconductor memory device.

[2] The cut-off circuit cuts off the current supply from the voltage application circuit to the resistance memory element based on the detection of the monitor circuit.

The nonvolatile semiconductor memory device according to claim 1, wherein:

[3] The cutoff circuit cuts off voltage application from the voltage application circuit to the resistance memory element based on the detection of the monitor circuit.

The nonvolatile semiconductor memory device according to claim 1, wherein:

[4] The monitor circuit has an input unit having a CMOS structure, and the threshold voltage is the threshold voltage of the input unit! /, The value voltage.

The nonvolatile semiconductor memory device according to claim 1, wherein:

[5] The input section has a pMOS structure and an nMOS structure, and the gate width force of the pMOS is wider than the MOS gate width.

The nonvolatile semiconductor memory device according to claim 2, wherein:

[6] The monitor circuit changes its internal logic when the first voltage reaches a predetermined threshold voltage.

The nonvolatile semiconductor memory device according to claim 1, wherein:

[7] having a precharge circuit that determines one end of the resistance memory element at a predetermined voltage before applying a voltage to the resistance memory element

The nonvolatile semiconductor memory device according to claim 1, wherein:

[8] Before applying the first voltage to the resistance memory element, the precharge circuit turns on an internal transistor to set one end of the resistance memory element to a predetermined voltage. Turn off the transistor

The nonvolatile semiconductor memory device according to claim 7, wherein:

[9] The voltage application circuit includes a current mirror circuit, and supplies power to the resistance memory element by the current mirror circuit.

The nonvolatile semiconductor memory device according to claim 1, wherein:

[10] The interrupting circuit interrupts one current path of the current mirror circuit.

The nonvolatile semiconductor memory device according to claim 7, wherein:

[11] A memory element array in which a plurality of the resistance storage elements are arranged between the resistance storage element and a reference voltage Vss. The cell selection transistor includes a cell selection transistor that selects the resistance storage element. The transistor that constitutes the current mirror circuit is a pMOS.

9. The nonvolatile semiconductor memory device according to claim 8, wherein

[12] A voltage capable of switching the resistance state is applied to both ends of the resistance memory element by the voltage application circuit,

After the voltage capable of switching the resistance state is applied, the power supply from the voltage application circuit to the resistance memory element is limited at the first switching of the resistance state of the resistance memory element

The nonvolatile semiconductor memory device according to claim 1, wherein:

[13] A voltage capable of switching the resistance state is applied to both ends of the resistance memory element by the voltage application circuit,

The resistance state is switched after a predetermined time has elapsed since a voltage capable of switching the resistance state is applied.

The nonvolatile semiconductor memory device according to claim 1, wherein:

[14] After the predetermined time has elapsed, the first voltage reaches the threshold value after the resistance state starts to switch and before the switching ends. The nonvolatile semiconductor memory device according to claim 13.

[15] In a nonvolatile semiconductor memory device having a resistance memory element that switches between a high resistance state and a low resistance state by application of a voltage,

A first voltage application circuit that supplies power to the resistance memory element when the resistance memory element is in a high resistance state, and generates a first voltage at one end of the resistance memory element;

When the resistance memory element is in a low resistance state, a second voltage is applied to supply power to the resistance memory element and generate a second voltage lower than the first voltage at one end of the resistance memory element. Circuit,

A first monitor circuit having a predetermined threshold voltage and detecting that the first voltage has reached the first threshold voltage;

A second monitor circuit having a predetermined threshold voltage and detecting that the first voltage has reached a second threshold voltage;

A first cutoff circuit that shuts off a current supply from the first voltage application circuit to the resistance memory element based on the detection of the first monitor circuit;

And a second cutoff circuit that cuts off voltage application from the second voltage application circuit to the resistance memory element based on the detection of the second monitor circuit.

A non-volatile semiconductor memory device.

[16] In the second monitor circuit, after the second voltage reaches the predetermined threshold voltage and the internal logic changes, the second voltage drops below the predetermined threshold. The logic after the change is maintained.

16. The nonvolatile semiconductor memory device according to claim 15, wherein

[17] The second monitor circuit further has a function of releasing the held state from the outside after being held in a state where the logic does not change.

17. The nonvolatile semiconductor memory device according to claim 16, wherein:

[18] The circuit for stable operation has a flip-flop circuit that combines two NAND circuits,

After the second voltage reaches the predetermined threshold voltage and the internal logic changes by the flip-flop circuit, the second voltage falls below the predetermined threshold. Maintain the post-change logic

17. The nonvolatile semiconductor memory device according to claim 16, wherein:

In a nonvolatile semiconductor memory device having a resistance memory element that switches between a high resistance state and a low resistance state by application of a voltage,

A voltage applying circuit that supplies power to the resistance memory element and generates a first voltage at a predetermined location of a memory cell including the resistance memory element;

Based on the detection of the monitor circuit, the power supply from the voltage application circuit to the resistance memory element is limited.

A non-volatile semiconductor memory device.