KR101004679B1 - Phase change memory device and verification method of programming current for it - Google Patents

Abstract

The present invention relates to a technology for programming memory cells of a phase change memory device, and an object thereof is to provide a phase change memory device capable of accurately programming data by adjusting a programming current. In the present invention, the test data is programmed in the phase change memory cell, and the test data is compared with the data programmed in the phase change memory cell to supply a larger programming current when the data does not match, or increase the supply time of the programming current. So that the data can be programmed correctly. In other words, the circuit is configured to adjust the current application condition to which data can be programmed accurately, and the optimal current application condition can be set using a fuse.

Phase change memory device. Phase change material, GST, programming current, set current, reset current

Description

PHASE CHANGE MEMORY DEVICE AND VERIFICATION METHOD OF PROGRAMMING CURRENT FOR IT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly to a technique for programming a memory cell of a phase change memory device.

Dynamic Radom Access Memory (DRAM), which is used in computer main memory, can be randomly accessed and highly integrated at low cost, but has a disadvantage of being volatile memory. In addition, the static radom access memory (SRAM) used as a cache memory or the like is capable of random access and is faster than a DRAM, but is disadvantageous in terms of cost because it is a volatile memory and a memory cell larger than the DRAM. On the other hand, NAND flash memory, which is a non-volatile memory, is highly integrated at low cost and advantageous in terms of power consumption, but has a disadvantage of slow operation speed because random access is not possible.

Various memories are being developed to overcome the disadvantages of the conventional memory device. In particular, phase change memory (PCRAM) devices are characterized as non-volatile memory and have random access. High integration is possible at low cost. A phase change memory device (PCRAM) stores information using a phase change material, and a nonvolatile memory device using a phase change of a phase change material according to a temperature condition, that is, a change in resistance value according to a phase change. Non-Volatile Memory Device).

The phase change material uses a material that can be converted into an amorphous state or a crystal state depending on temperature conditions. Typical phase change materials include chalcogenide alloys, including Ge ₂ Sb ₂ Te ₅ (GST) using germanium (German), antimony (Sb), and tellurium (Te). Since is representative, phase change materials are generally referred to as 'GST'.

The phase change memory device PCRAM uses a Joule heating generated by application of a current or voltage under a specific condition to the phase change material GST, and determines the crystal state of the phase change material GST. It causes a reversible phase change between amorphous states. The crystal state is described as a circuit set state, and in the set state, the phase change material GST has electrical characteristics such as a metal having a low resistance value. In addition, the amorphous state is described as a reset state in a circuit, and in the reset state, the phase change material GST has a higher resistance value than the set state. . That is, the phase change memory device stores information through a change in resistance value between a crystal state and an amorphous state, and detects a voltage change due to a change in current or current flowing through a phase change material (GST). Stored information is determined. Generally, the set state is defined as '0' and the reset state has a logic level of '1'. The phase change material (GST) maintains its state even when the power is cut off.

Meanwhile, the amorphous state and the crystal state of the phase change material GST may be switched with each other by a programming current, and the set current sets the phase change material GST of the memory cell. A programming current for making a set state, and a reset current is defined as a programming current for making a phase change material GST of a memory cell into a reset state.

The phase change material GST is heated to a temperature higher than the melting temperature for a predetermined time by supplying a reset current, and then rapidly cooled to be converted into an amorphous state. In addition, the phase change material GST is heated to a temperature higher than the crystallization temperature and lower than the melting temperature for a predetermined time by supply of a set current, and then gradually cooled to a crystal state. On the other hand, since the resistance value can be differentiated according to the amorphous volume or the crystal volume of the phase change material GST, a multi-level memory cell may be used. will be. In general, the reset current flows a high current for a short time compared to the set current, and the set current flows a low current for a long time compared to the reset current. . That is, the state of the phase change material GST is changed by Joule heating of a specific condition generated by the supply of programming current.

1 is a configuration diagram of a phase change memory cell.

Referring to FIG. 1, a phase change memory cell is connected between a phase change element GST connected between a bit line BL and a first node N0, and between a first node N0 and a ground voltage terminal VSS. And a cell transistor MN1 under the control of the word line WL.

An operation of the phase change memory cell configured as described above is as follows.

First, an operation for programming data in the phase change element GST is performed as follows.

When the word line WL is activated at a high level and the cell transistor MN1 is turned on, a current path is provided between the phase change element GST connected to the bit line BL and the ground voltage terminal VSS. Will be created. Therefore, by supplying a programming current corresponding to data to the phase change element GST through the bit line BL, the phase change element GST is changed into a crystal state or an amorphous state. In general, when the data to be programmed has a logic level of '1', the reset current is supplied to convert the phase change element GST to a reset state, and the data is at a logic level of '0'. When the current is supplied to the set current (Set Current) to convert the phase change element (GST) to the set state (Set State). The reset state, which is an amorphous state, has a larger resistance value than the set state, which is a crystal state.

In addition, an operation for detecting data programmed into the phase change element GST is performed as follows.

When the word line WL is activated at a high level and the cell transistor MN1 is turned on, a current path is provided between the phase change element GST connected to the bit line BL and the ground voltage terminal VSS. Will be created. Therefore, when a constant voltage or a constant current is applied to the phase change element GST through the bit line BL, the amount of current flowing according to the resistance value of the phase change element GST is different, or the phase change element GST is applied. Since the magnitude of the voltage drop is different, the data stored in the phase change element GST is determined using the voltage drop. That is, the state of the phase change element GST is determined.

2 is another configuration diagram of a phase change memory cell.

Referring to FIG. 1, a phase change memory cell includes a cell diode D1 and a bit line BL connected to a cathode connected to a word line WL and an anode connected to a first node N0. The phase change element GST connected between the 1st node N0 is provided.

An operation of the phase change memory cell configured as described above is as follows.

First, an operation for programming data in the phase change element GST is performed as follows.

When the word line WL is activated at a low level-ground voltage and starts to apply a constant voltage through the bit line BL, the cell diode D1 is in a forward biased state, so that the anode of the cell diode D1 is The cell diode D1 is turned on when the voltage difference between the anode and the cathode becomes greater than the threshold voltage. At this time, a current path is generated between the phase change element GST connected to the bit line BL and the word line WL. Therefore, by supplying a programming current corresponding to data to the phase change element GST through the bit line BL, the phase change element GST is changed into a crystal state or an amorphous state. In general, when the data to be programmed has a logic level of '1', the reset current is supplied to convert the phase change element GST to a reset state, and the data is at a logic level of '0'. When the current is supplied to the set current (Set Current) to convert the phase change element (GST) to the set state (Set State). The reset state, which is an amorphous state, has a larger resistance value than the set state, which is a crystal state.

In addition, an operation for detecting data programmed into the phase change element GST is performed as follows.

When the word line WL is activated at a low level-ground voltage and starts to apply a constant voltage through the bit line BL, the cell diode D1 is in a forward biased state, so that the anode of the cell diode D1 is The cell diode D1 is turned on when the voltage difference between the anode and the cathode becomes greater than the threshold voltage. At this time, a current path is generated between the phase change element GST connected to the bit line BL and the word line WL. Therefore, when a constant voltage or a constant current is applied to the phase change element GST through the bit line BL, the amount of current flowing varies according to the resistance value of the phase change element GST, or the phase change element GST Since the magnitude of the voltage drop is different, the data stored in the phase change element GST may be determined using the voltage drop magnitude. That is, the state of the phase change element GST is determined.

As shown in FIG. 2, the structure of a phase change memory cell using a cell diode D1 instead of a cell transistor is excellent in supplying a programming current and occupies a small area, which is advantageous for high integration. . Therefore, recently, phase change memory cells have been constructed using cell diodes rather than cell transistors.

As described above, in order to store data in a phase change memory cell, a programming current having a specific condition must be supplied. That is, according to the data to be programmed, the set current to set the phase change element GST to the set state or the reset current to make the reset state to be set according to the data to be programmed. If the programming current is insufficient due to PVT (Process Voltage Temperature) change or the programming time is shorter than the scheduled time, the data cannot be programmed correctly. Therefore, additional circuitry is required to verify and correct this.

The present invention has been proposed to solve the above-mentioned conventional problems, and an object thereof is to provide a phase change memory device capable of accurately programming data by adjusting a programming current.

According to an aspect of the present invention for achieving the above technical problem, a data reading unit for reading data programmed in a phase change memory cell; A comparison unit for comparing the output data output from the data reading unit with the applied test data; Outputs first and second write control signals corresponding to the test data, and activates a bias signal when two data are different as a result of the comparison of the comparator-an activation period of the first write control signal or the second write control signal Activated during the write control; And a data write unit configured to supply a programming current to the phase change memory cell in response to the first and second write control signals, and to supply an additional programming current to the phase change memory cell in response to the bias signal. A change memory device is provided.

In addition, according to another aspect of the invention, the data reading unit for reading data programmed in the phase change memory cell; A comparison unit for comparing the output data output from the data reading unit with the applied test data; Outputs first and second write control signals corresponding to the test data, and activates a bias signal when two data are different as a result of comparison of the comparator-an activation period of the first write control signal or the second write control signal After a certain time is activated-the write control unit for outputting; And supplying a programming current to the phase change memory cell in response to the first and second write control signals, and adding a time for supplying a programming current to the phase change memory cell in response to the bias signal. A phase change memory device having a write unit is provided.

Further, according to another aspect of the invention, a first programming step of programming test data in the phase change memory cell; A comparison step of comparing the test data with data programmed into the phase change memory cell through the first programming step; And a second programming for providing the additional programming current to the programming current supplied in the first programming step and programming the test data to the phase change memory cell through a larger current when the two data are different as a result of the comparison. A programming current verification method of a phase change memory device including the steps is provided.

Further, according to another aspect of the invention, a first programming step of programming test data in the phase change memory cell; A comparison step of comparing the test data with data programmed into the phase change memory cell through the first programming step; And a second programming step of programming the test data to the phase change memory cell by providing a programming current for a longer period of time than the first programming step when the two data data of the comparison step are different from each other. A method of verifying the programming current of a device is provided.

In the present invention, the test data is programmed in the phase change memory cell, and the test data is compared with the data programmed in the phase change memory cell to supply a larger programming current when the data does not match, or increase the supply time of the programming current. So that the data can be programmed correctly. In other words, the circuit is configured to adjust the current application condition to which data can be programmed accurately, and the optimal current application condition can be set using a fuse.

The phase change memory device to which the present invention is applied can identify the programming current application condition according to the characteristic difference of each phase change memory cell which can be changed according to the process, and thus can accurately program the data to improve the yield of the phase change memory device. Can be.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. . For reference, symbols and symbols used to refer to elements, signal names, and the like in the drawings and the detailed description may be indicated by detailed units as necessary, and thus the same symbols and symbols do not refer to the same element in the entire circuit. Note that it may not.

In general, the logic signal of the circuit is divided into a high level (HIGH LEVEL, H) or a low level (LOW LEVEL, L) corresponding to the voltage level, and may be expressed as '1' and '0', respectively. In addition, it is defined and described that it may additionally have a high impedance (Hi-Z) state and the like. In addition, PMOS (P-channel Metal Oxide Semiconductor) and N-channel Metal Oxide Semiconductor (NMOS), which are terms used in the present embodiment, are known to be a type of MOSFET (Metal Oxide Semiconductor Field-Effect Transistor).

3 is a configuration diagram of a phase change memory device according to an embodiment of the present invention.

Referring to FIG. 3, the phase change memory device includes a data reader 320 for reading data programmed in the phase change memory cell 310, output data DATA1_RD output from the data reader 320, and an applied test. The comparator 330 for comparing the data DATA1_WR and the first and second write control signals SET and RESET corresponding to the test data DATA1_WR are output. If different, the bias control signal C_EN is activated-activated during the activation period of the first write control signal SET or the second write control signal RESET. The programming current I _WRITE is supplied to the phase change memory cell 310 in response to the write control signals SET and RESET, but the additional programming current is supplied to the phase change memory cell 310 in response to the bias signal C_EN. The data writing unit 350 is provided.

The main operations of the phase change memory device configured as described above are as follows.

First, when the word line enable signal WL_EN and the column select signal YI are activated at the high level, the data read unit 320 pulls down the transistors MN1 of the data read unit 320 and the word line driver 360. A constant current is supplied through the current path formed between the circuits and senses the voltage change of the phase change element GST to determine the data programmed in the phase change element GST.

Next, the comparator 330 compares the output data DATA1_RD output from the data reader 320 with the applied test data DATA1_WR and outputs the result.

Next, the write controller 340 outputs the first and second write control signals SET and RESET corresponding to the test data DATA1_WR, and the bias signal when the two data are different as a result of the comparison by the comparator 330. The C_EN is activated and output, and the bias signal C_EN is activated during the activation period of the first write control signal SET or the second write control signal RESET. The write control unit 340 may further include a fuse circuit for activating the bias signal C_EN during the activation period of the first write control signal SET or the second write control signal RESET. That is, whether the bias signal C_EN is activated and an activation period may be set through the fuse.

Finally, the data write unit 350 supplies the programming current I _WRITE to the phase change memory cell 310 in response to the first and second write control signals SET and RESET, but not to the bias signal C_EN. In response, an additional programming current is supplied to the phase change memory cell 310. Therefore, a larger programming current I _WRITE is supplied to the phase change element GST during the period in which the bias signal C_EN is activated.

4 is a circuit diagram according to an embodiment of the comparison unit of FIG. 3.

Referring to FIG. 4, the comparator includes an output signal of a first inverter INV1 inputting test data DATA1_WR, a second inverter INV2 inputting output data DATA1_RD, and an output signal of the first inverter INV1. First negative logical means NAND1 for inputting output data DATA1_RD, Output signal of second inverter INV1 and Second negative logical means NAND2 for inputting test data DATA1_WR, Test signal (TEST) and third negative logical means (NAND3) for inputting the output signals of the first and second negative logical means (NAND1, NAND2).

The main operation of the comparator configured as described above is performed as follows.

First, when the test signal TEST is at the low level, the output signal CELL_VEN of the comparator is activated at a high level and output. That is, the output signal CELL_VEN is output at a high level regardless of the comparison result of the test data DATA1_WR and the output data DATA1_RD.

Next, when the test data DATA1_WR and the output data DATA1_RD have the same logic level when the test signal TEST is at the high level, the output signal CELL_VEN is deactivated to a low level and is output. The test data DATA1_WR ) And the output data DATA1_RD have different logic levels, the output signal CELL_VEN is activated at a high level and output. In other words, when the test signal TEST is at the high level, two input signals are compared and the result is output.

5 is a circuit diagram according to an embodiment of the data write unit of FIG. 3.

Referring to FIG. 5, the data write unit may output the set current Set I1_SET or the reset current I1_RESET to the output terminal N0 in response to the first write control signal SET and the second write control signal RESET. ) Is configured as a current driver 510 for driving) and an auxiliary current driver 520 for driving additional current I2 to output terminal N0 in response to bias signal C_EN.

The main operation of the data writing unit configured as described above is performed as follows.

The current driver 510 drives the set current I1_SET or the reset current I1_RESET to the output terminal N0 in response to the first write control signal SET and the second write control signal RESET. The programming current I1_SET generated through the current mirror is supplied to the output terminal N0 during the activation period of the first write control signal SET, that is, the set current. In addition, during the activation period of the second write control signal RESET, the programming current I1_RESET generated through the current mirror, that is, the reset current is supplied to the output terminal N0. The activation level of the first write control signal SET and the second write control signal RESET is determined according to the logic level of the data to be programmed.

In addition, the auxiliary current driver 520 drives the additional current I2 to the output terminal N0 in response to the bias signal C_EN, and the bias signal C_EN is the first write control signal SET or the second write control. It is activated during the activation period of the signal RESET and controls to supply an additional current I2 to the output terminal N0. Therefore, when the bias signal C_EN is activated, the programming current I _WRITE driven to the output terminal N0 is driven from the auxiliary current driver 520 to the current I1 driven by the current driver 510. Is added and driven.

The programming current of the phase change memory device as described above is programmed in the phase change memory cell 310 through the first programming step and the first programming step of programming the test data DATA1_WR in the phase change memory cell 310. In the comparison step of comparing the data and the test data DATA1_WR, and the comparison result of the comparison step, when the two data are different, an additional programming current I2 is provided to the programming current I1 supplied in the first programming step so that a larger current ( It may be verified through a second programming step of programming test data DATA1_WR to the phase change memory cell 310 through I1 + I2).

Here, the first programming step may include generating first and second write control signals SET and RESET corresponding to the test data DATA1_WR, and in response to the first and second write control signals SET and RESET. And supplying a set current I1_SET or a reset current I1_RESET to the change memory cell 310. The second programming step may include activation of the first and second write control signals SET and RESET corresponding to the test data DATA1_WR, and the first write control signal SET or the second write control signal RESET. Generating a bias signal C_EN that is activated during the interval, and in response to the first and second write control signals SET and RESET, the set current Set I, I1_SET or reset current Supplying Reset Current, I1_RESET, but supplying an additional current I2 to the phase change memory cell 310 in response to the bias signal C_EN.

Hereinafter, with reference to Figures 3 to 5 in another aspect of the present invention.

Referring to FIG. 3, the phase change memory device includes a data reader 320 for reading data programmed in the phase change memory cell 310, output data DATA1_RD output from the data reader 320, and an applied test. The comparator 330 for comparing the data DATA1_WR and the first and second write control signals SET and RESET corresponding to the test data DATA1_WR are output. If different, the bias signal C_EN is activated-After a period of activation of the first write control signal SET or the second write control signal RESET is activated for a certain time-the write control unit 340, the first to output The programming current I _WRITE is supplied to the phase change memory cell 310 in response to the second write control signals SET and RESET, but the programming current is supplied to the phase change memory cell 310 in response to the bias signal C_EN. adding the time of supplying a certain amount of time _(WRITE I) And a data writing unit 350.

The main operations of the phase change memory device configured as described above are as follows.

First, when the word line enable signal WL_EN and the column select signal YI are activated at the high level, the data read unit 320 pulls down the transistors MN1 of the data read unit 320 and the word line driver 360. A constant current is supplied through the current path formed between the circuits and senses the voltage change of the phase change element GST to determine the data programmed in the phase change element GST.

Next, the comparator 330 compares the output data DATA1_RD output from the data reader 320 with the applied test data DATA1_WR and outputs the result.

Next, the write controller 340 outputs the first and second write control signals SET and RESET corresponding to the test data DATA1_WR, and the bias signal when the two data are different as a result of the comparison by the comparator 330. The C_EN is activated and output, and the bias signal C_EN is activated for a predetermined time after the activation period of the first write control signal SET or the second write control signal RESET. The write controller 340 may further include a fuse circuit for activating the bias signal C_EN for a predetermined time after the activation period of the first write control signal SET or the second write control signal RESET. There will be. That is, whether the bias signal C_EN is activated and an activation period may be set through the fuse.

Finally, the data write unit 350 supplies the programming current I _WRITE to the phase change memory cell 310 in response to the first and second write control signals SET and RESET, but not to the bias signal C_EN. In response, the time for supplying the programming current I _WRITE to the phase change memory cell 310 is added for a predetermined time. Therefore, the programming current I _WRITE is additionally supplied to the phase change element GST during the period in which the bias signal C_EN is activated after the activation of the first write control signal SET or the second write control signal RESET.

Referring to FIG. 4, the comparator includes an output signal of a first inverter INV1 inputting test data DATA1_WR, a second inverter INV2 inputting output data DATA1_RD, and an output signal of the first inverter INV1. First negative logical means NAND1 for inputting output data DATA1_RD, Output signal of second inverter INV1 and Second negative logical means NAND2 for inputting test data DATA1_WR, Test signal (TEST) and third negative logical means (NAND3) for inputting the output signals of the first and second negative logical means (NAND1, NAND2).

The main operation of the comparator configured as described above is performed as follows.

First, when the test signal TEST is at the low level, the output signal CELL_VEN of the comparator is activated at a high level and output. That is, the output signal CELL_VEN is output at a high level regardless of the comparison result of the test data DATA1_WR and the output data DATA1_RD.

Next, when the test data DATA1_WR and the output data DATA1_RD have the same logic level when the test signal TEST is at the high level, the output signal CELL_VEN is inactivated and output at a low level, and the test data DATA1_WR When the output data DATA1_RD and the logic data have different logic levels, the output signal CELL_VEN is activated at a high level and output. In other words, when the test signal TEST is at the high level, two input signals are compared and the result is output.

Referring to FIG. 5, the data write unit may output the set current Set I1_SET or the reset current I1_RESET to the output terminal N0 in response to the first write control signal SET and the second write control signal RESET. Auxiliary current for adding a driving time of the set current or the reset current driven to the output terminal N0 in response to the bias signal C_EN and the bias signal C_EN for a predetermined time The driving unit 520 is configured.

The main operation of the data writing unit configured as described above is performed as follows.

The current driver 510 drives the set current I1_SET or the reset current I1_RESET to the output terminal N0 in response to the first write control signal SET and the second write control signal RESET. The programming current I1_SET generated through the current mirror is supplied to the output terminal N0 during the activation period of the first write control signal SET, that is, the set current. In addition, during the activation period of the second write control signal RESET, the programming current I1_RESET generated through the current mirror, that is, the reset current is supplied to the output terminal N0. The activation level of the first write control signal SET and the second write control signal RESET is determined according to the logic level of the data to be programmed.

In addition, the auxiliary current driver 520 drives the additional current I2 to the output terminal N0 in response to the bias signal C_EN, and the bias signal C_EN is the first write control signal SET or the second write control. After the activation period of the signal RESET is activated for a predetermined time to control to supply an additional current (I2) to the output terminal (N0). Therefore, when the bias signal C_EN is activated, the driving time of the programming current I _WRITE driven to the output terminal N0 is the auxiliary current driver 520 at the supply time of the currents I1_SET and I1_RESET driven by the current driver 510. In addition, the supply time of the current I2 driven in FIG. 9 is added to increase the driving time of the set current or the reset current. Since the mirrored output current I2 is determined according to the size of the PMOS transistor MP4 of the auxiliary current driver 520, the size of the PMOS transistor MP4 may be adjusted according to the amount of current to be supplied for an additional time. will be.

The programming current of the phase change memory device as described above is programmed in the phase change memory cell 310 through the first programming step and the first programming step of programming the test data DATA1_WR in the phase change memory cell 310. In the comparison step of comparing the data and the test data DATA1_WR, and the comparison result of the comparison step, when the two data are different, the programming current I _WRITE is provided to the phase change memory cell 310 for a longer time than the first programming step. It may be verified through a second programming step of programming the test data DATA1_WR.

Here, the first programming step may include generating first and second write control signals SET and RESET corresponding to the test data DATA1_WR, and in response to the first and second write control signals SET and RESET. And supplying a set current I1_SET or a reset current I1_RESET to the change memory cell 310. The second programming step may include an activation period of the first and second write control signals SET and RESET corresponding to the test data DATA1_WR and the first write control signal SET or the second write control signal RESET. Afterwards, the bias signal C_EN is activated for a predetermined time, and the set current (I1_SET) or reset is performed in the phase change memory cell 310 in response to the first and second write control signals SET and RESET. Supplying a current (Reset Current, I1_RESET), but adding a time for supplying a set current (Set Current) or a reset current (Reset Current) to the phase change memory cell 310 in response to the bias signal (C_EN) for a predetermined time It includes.

In the above, the specific description was made according to the embodiment of the present invention. Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

For example, the configuration of an active high or an active low to indicate an activation state of a signal and a circuit may vary according to embodiments. In addition, the configuration of the transistor may be changed as necessary to implement the same function. That is, the configurations of the PMOS transistor and the NMOS transistor may be replaced with each other, and may be implemented using various transistors as necessary. In addition, the configuration of the logic gate may be changed as necessary to implement the same function. That is, the negative logical means, the negative logical sum means, etc. may be configured through various combinations such as NAND GATE, NOR GATE, and INVERTER. Such a change in the circuit is too many cases, and the change can be easily inferred by a person skilled in the art, so the enumeration thereof will be omitted.

1 is a configuration diagram of a phase change memory cell.

2 is another configuration diagram of a phase change memory cell.

3 is a configuration diagram of a phase change memory device according to an embodiment of the present invention.

4 is a circuit diagram according to an embodiment of the comparison unit of FIG. 3.

5 is a circuit diagram according to an embodiment of the data write unit of FIG. 3.

* Explanation of symbols for the main parts of the drawings

310: phase change memory cell

360: word line driver

510: current driver

520: auxiliary current driver

In the figure, PMOS transistors and NMOS transistors are denoted by MPi and MNi (i = 0, 1, 2, ...), respectively.

Claims (14)

A data reading unit for reading data programmed into a phase change memory cell; A comparison unit for comparing the output data output from the data reading unit with the applied test data; Outputs first and second write control signals corresponding to the test data, and activates a bias signal when two data are different as a result of the comparison of the comparator-an activation period of the first write control signal or the second write control signal Activated during the write control; And A data write unit configured to supply a programming current to the phase change memory cell in response to the first and second write control signals, and to supply an additional programming current to the phase change memory cell in response to the bias signal Phase change memory device having a. The method of claim 1, The write control unit, And a fuse circuit for activating the bias signal during an activation period of the first write control signal or the second write control signal. The method of claim 1, And the write controller sets whether to activate the bias signal and an activation interval in response to a comparison result of the comparator. The method of claim 1, The data writing unit, A current driver for driving a set current or a reset current to an output terminal in response to the first write control signal and the second write control signal; And And an auxiliary current driver for driving an additional current to the output terminal in response to the bias signal. A data reading unit for reading data programmed into a phase change memory cell; A comparison unit for comparing the output data output from the data reading unit with the applied test data; Outputs first and second write control signals corresponding to the test data, and activates a bias signal when two data are different as a result of the comparison of the comparison unit; After a certain time is activated-the write control unit for outputting; And Write data for supplying a programming current to the phase change memory cell in response to the first and second write control signals, and adding a time for supplying a programming current to the phase change memory cell in response to the bias signal. part Phase change memory device having a. The method of claim 5, The write control unit, And a fuse circuit for activating the bias signal for a predetermined time after an activation period of the first write control signal or the second write control signal. The method of claim 5, And the write controller sets whether to activate the bias signal and an activation interval in response to a comparison result of the comparator. The method of claim 5, The data writing unit, A current driver for driving a set current or a reset current to an output terminal in response to the first write control signal and the second write control signal; And And an auxiliary current driver configured to add a driving time of the set current or the reset current driven to the output terminal in response to the bias signal for a predetermined time. A first programming step of programming test data into a phase change memory cell; A comparison step of comparing the test data with data programmed into the phase change memory cell through the first programming step; And A second programming step of programming the test data to the phase change memory cell through a larger current by providing an additional programming current to the programming current supplied in the first programming step when the two data are different as a result of the comparison. Method of operating a phase change memory device comprising a. 10. The method of claim 9, The first programming step, Generating first and second write control signals corresponding to the test data; And And supplying a set current or a reset current to the phase change memory cell in response to the first and second write control signals. 10. The method of claim 9, The second programming step, Generating a first and second write control signal corresponding to the test data and a bias signal activated during an activation period of the first write control signal or the second write control signal; And Supplying a set current or a reset current to the phase change memory cell in response to the first and second write control signals, and supplying an additional current to the phase change memory cell in response to the bias signal. A method of operating a phase change memory device. A first programming step of programming test data into a phase change memory cell; A comparison step of comparing the test data with data programmed into the phase change memory cell through the first programming step; And A second programming step of programming the test data to the phase change memory cell by providing a programming current for a longer time than the first programming step when the two data are different as a result of the comparison step. Method of operating a phase change memory device comprising a. The method of claim 12, The first programming step, Generating first and second write control signals corresponding to the test data; And And supplying a set current or a reset current to the phase change memory cell in response to the first and second write control signals. The method of claim 12, The second programming step, Generating a first and second write control signal corresponding to the test data and a bias signal activated for a predetermined time after an activation period of the first write control signal or the second write control signal; And Supply a set current or a reset current to the phase change memory cell in response to the first and second write control signals, and provide a time for supplying the set current or reset current to the phase change memory cell in response to the bias signal. The method of operating a phase change memory device comprising the step of adding a predetermined time.

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