JP5012802B2 - Nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device using a resistance memory element whose resistance state is changed by applying an electrical stimulus.

  The nonvolatile semiconductor memory device is called RRAM (Resistance Random Access Memory), and uses a resistance memory element whose resistance state is changed by applying an electrical stimulus from the outside as a memory cell. The high resistance state and the low resistance state of the resistance memory element are associated with, for example, information “0” and “1”.

  As a typical example of a resistance memory element, an oxide material containing a transition metal is known. However, a resistance memory element having the above-described characteristics generally has a low resistance state or a low resistance state. When the state changes to the high resistance state, the resistance value changes greatly, and the resistance value changes abruptly. Therefore, in order to prevent the phenomenon that an excessive current flows through the resistance memory element when writing data, the RRAM needs to limit the current (current compliance) at a predetermined timing.

  Conventionally, as a method for realizing such a function of current compliance, a method of supplying power to the resistance memory element in a pulsed manner while limiting the current has been proposed. In such a method, a current limiting circuit is provided. In addition, it is necessary to perform a so-called verify operation for checking whether or not the set operation has been performed correctly. As a result, the circuit becomes complicated and the circuit scale becomes large, and the write time becomes long.

  In order to eliminate the above-mentioned drawbacks related to the writing time, a method of monitoring the change in the resistance value of the resistance memory element and feeding back the monitored state to cut off the power supply to the resistance memory element has also been proposed. (See Patent Document 1).

  According to Patent Document 1, the voltage value at one end of the resistance memory element is monitored, and the monitored result is input to the sense amplifier circuit. On the other hand, a reference voltage of the sense amplifier circuit is created by a plurality of resistance elements (reference resistances), and writing is stopped when the resistance value of the resistance memory element changes to a resistance value of a predetermined reference resistance.

JP 2004-234707 A

(Problems to be solved by the invention)

  However, in the method described in Patent Document 1, since the reference voltage is created by combining the reference resistors, it is necessary to newly provide a reference resistor in addition to the sense amplifier circuit. The problem remains.

  The present invention has been made in view of the above problems, and provides a nonvolatile semiconductor memory device that can perform reliable writing in a short time and has a writing circuit having a simple circuit configuration. For the purpose.

(Means for solving the problem)
The present inventors have found that the above problem can be solved by a novel circuit configuration utilizing the characteristic that the resistance state of the resistance memory element changes during writing (not in flash memory or the like) It came to make this invention.

  That is, at the time of writing, a high voltage is applied to the resistance memory element to change its resistance state. Then, paying attention to the voltage (within the writing circuit) that changes according to the change in the resistance state, the voltage is received by a monitor circuit having a predetermined threshold value, and the resistance change is instantaneously triggered by the change in the voltage as a trigger The solution to the problem is realized by limiting the power supply to the element.

  According to one aspect of the present invention, a nonvolatile semiconductor memory device having a resistance memory element that switches between a high resistance state and a low resistance state by application of a voltage, the power source being supplied to the resistance memory element, and the resistance memory A voltage applying circuit for generating a first voltage at one end of the element; a monitor circuit having a predetermined threshold voltage; and detecting that the first voltage has reached a predetermined threshold voltage; A non-volatile semiconductor memory device is provided that includes a cutoff circuit that limits power supply from the voltage application circuit to the resistance memory element based on the detection of the monitor circuit.

  According to another aspect of the present invention, there is provided a non-volatile semiconductor memory device having a resistance memory element that switches between a high resistance state and a low resistance state by application of a voltage, and the resistance memory element is in a high resistance state. A first voltage applying circuit for supplying power to the resistance memory element and generating a first voltage at one end of the resistance memory element; and when the resistance memory element is in a low resistance state, the resistance memory element A second voltage applying circuit for supplying a power to the first resistance memory element and generating a second voltage lower than the first voltage at one end of the resistance memory element; and a predetermined threshold voltage, and the first voltage A first monitor circuit for detecting that the first threshold voltage has been reached, and a predetermined threshold voltage, wherein the first voltage has reached the second threshold voltage. A second monitor circuit to detect, and the first monitor circuit A first cutoff circuit that cuts off current supply from the first voltage application circuit to the resistance memory element, and a second voltage application based on the detection of the second monitor circuit. There is provided a nonvolatile semiconductor memory device having a second cutoff circuit that cuts off voltage application from the circuit to the resistance memory element.

  According to another aspect of the present invention, there is provided a nonvolatile semiconductor memory device having a resistance memory element that switches between a high resistance state and a low resistance state by application of a voltage, and supplies power to the resistance memory element. A voltage application circuit for generating a first voltage at a predetermined location of a memory cell including the resistance memory element; a predetermined threshold voltage; and the first voltage has reached a predetermined threshold voltage There is provided a non-volatile semiconductor memory device that limits power supply from the voltage application circuit to the resistance memory element based on the detection of the monitor circuit.

(Effect of the invention)
According to the present invention, at the time of writing, a high voltage is applied to the resistance memory element to change its resistance state. Then, paying attention to the voltage (within the writing circuit) that changes in accordance with the change in the resistance state, the current supply to the resistance memory element is instantaneously limited by using the predetermined change in the voltage as a trigger. Reliable writing can be performed, and such writing processing can be realized with a simple circuit.

  It is also possible to easily design a circuit using a general-purpose design tool and design method in a semiconductor process.

These are graphs showing the current-voltage characteristics of a resistance memory element using a unipolar resistance memory material. FIG. 3 is a diagram showing a basic configuration of a memory cell in a nonvolatile semiconductor memory device. FIG. 3 is a circuit diagram showing a memory cell array 20 in which memory cells 10 are arranged in a matrix. FIG. 3 is a block diagram illustrating a schematic configuration of a peripheral circuit according to the first embodiment. FIG. 3 is a circuit diagram illustrating an example of a set driver circuit according to the first embodiment. FIG. 3 is a timing chart illustrating a write operation of the set driver circuit according to the first embodiment. FIG. 3 is a circuit diagram illustrating an example of a reset driver circuit according to the first embodiment. FIG. 3 is a timing chart illustrating a write operation of the reset driver circuit according to the first embodiment. These are graphs showing the relationship between the ratio of the gate width of the nMOS and the gate width of the pMOS and the threshold voltage of the input section in the input section of the monitor circuit having the CMOS structure.

  Below, the detail which concerns on embodiment of this invention is demonstrated, referring drawings.

(Example 1)
-Basic operation of resistance memory element-
First, the basic operation of a resistance memory element using a unipolar resistance memory material will be described with reference to the drawings. FIG. 1 is a graph showing current-voltage characteristics of a resistance memory element using a unipolar resistance memory material. This graph is a case where TiO _x which is a typical example of a unipolar resistance memory material is used.

  Let the initial state of the resistance memory element be point a. As the applied voltage is gradually increased from the point a, the current gradually increases along the curve A. When the applied voltage further increases and exceeds about 1.5 V (point b in the figure), the resistance memory element is switched (set) from the high resistance state to the low resistance state.

  As a result, the absolute value of the current increases rapidly, and the current-voltage characteristic transitions from the high resistance state of curve A to the low resistance state shown by curves C and D. It should be noted that the current value is approximately 2 mA and is constant (straight line B) from the point b to the point c because the current is limited. That is, the resistance memory element has already transitioned to the low resistance state at the point b.

  Therefore, if the current limit is removed, a large current having a value obtained when the curve D is extended to 1.5 V beyond the point d will flow to the resistance memory element, and the resistance memory element may be damaged. There is sex.

  Next, the current limitation is removed at the time point c. When the voltage is gradually decreased from the point c, the current changes along the curve C in the direction of the arrow, and the absolute value thereof gradually decreases. Conversely, when the applied voltage is gradually increased again, the current changes along the curve D in the direction of the arrow, and its absolute value gradually increases.

  When the applied positive voltage is further increased and exceeds about 0.7 V (point d), the resistance memory element is switched (reset) from the low resistance state to the high resistance state. Along with this, the absolute value of the current sharply decreases along the curve E, and the current-voltage characteristic transitions from the point d to the point e.

  After the transition to the point e, the current changes along the curve A when the voltage is decreased or increased from the state at the point e. As long as the voltage does not exceed the point b, this resistance memory element maintains the high resistance state as it is.

As described above, when TiO _x is used as the resistance memory element, the current-voltage characteristic is linear along the curve A if the applied voltage is lower than the voltage at the point b (about 1.5 V) in the high resistance state. Change and the high resistance state is maintained. Similarly, in the low resistance state, if the applied voltage is lower than the voltage at the point d (about 0.7 V), the current-voltage characteristic changes along the curve C, and the low resistance state is maintained.

  In other words, regardless of the resistance state of the resistance memory element, the resistance memory element is stable if the voltage applied to the resistance memory element is lower than a predetermined voltage (e.g., 0.7 V in this case). The resistance state at the time is maintained.

  Note that when a resistance memory element is formed using the above-described material, characteristics as shown in FIG. 1 cannot be obtained in an initial state immediately after the element is formed. In order to make the resistance memory material reversibly changeable between a high resistance state and a low resistance state, a process called forming may be required. In forming, a voltage higher than the set voltage is applied to the resistance memory material. Once forming is performed, the resistance memory element does not return to the initial state.

-Basic configuration of memory cell-
Next, the basic configuration of the memory cell in the nonvolatile semiconductor memory device will be described with reference to FIG. 2A is a circuit diagram showing a memory cell in the nonvolatile semiconductor memory device, and FIG. 2B is a schematic cross-sectional view showing a structure of the memory cell in the nonvolatile semiconductor memory device. FIG. 2 shows a configuration common to the conventional nonvolatile semiconductor memory device and the nonvolatile semiconductor memory device of this embodiment.

  As shown in FIG. 2A, the memory cell 10 of the nonvolatile semiconductor memory device includes a resistance memory element 12 and a cell selection transistor 14. The resistance memory element 12 has one end connected to the bit line BL and the other end connected to the drain D of the cell selection transistor 14. The source S of the cell selection transistor 14 is connected to the source line SL, and the gate G is connected to the word line WL.

As shown in FIG. 2B, the resistance memory element 12 has a resistance memory material 12b sandwiched between a pair of electrodes (12a, 12c). Here, the resistance memory material 12b is a unipolar resistance memory material made of, for example, TiO _x . In FIG. 2B, the bit line BL extends parallel to the paper surface, and the source line SL and the word line WL extend from the front to the back of the paper surface, that is, perpendicular to the paper surface.

  FIG. 3 is an example of a circuit diagram showing a memory cell array 20 in which the memory cells 10 shown in FIG. 2 are arranged in a matrix. Thus, the plurality of memory cells 10 are arranged adjacent to each other in the column direction (vertical direction in the drawing) and the row direction (horizontal direction in the drawing).

  A plurality of word lines WL1, * WL1, WL2, * WL2,... Are arranged in the row direction, and are connected to the memory cells 10 arranged in the row direction. Similarly, source lines SL1, SL2,... Are arranged in the row direction and are connected to the memory cells 10 arranged in the row direction. In this figure, an example is shown in which one source line is provided for every two word lines. However, the number of source lines equal to or more than the number of word lines is provided in relation to the amount of power noise generated. May be.

  A plurality of bit lines BL1, BL2, BL3, BL4... Are arranged in the column direction, and are connected to the memory cells 10 arranged in the column direction. Each bit line BL is provided with a bit line selection transistor 16 having a function as a variable resistance element.

-Peripheral circuits for writing and reading-
Next, a peripheral circuit that performs processing such as writing on the memory cells described so far will be described. FIG. 4 is a block diagram illustrating a schematic configuration of the peripheral circuit according to the first embodiment.

  As shown in FIG. 4, the peripheral circuit for the memory cell array 20 described above includes a set driver circuit 30 and a reset driver circuit 40 that write data to the memory cell 10, and a read circuit that reads data from the memory cell 10. 28 and a control circuit 26 for controlling these circuits.

  The memory cell array 20 includes a word line selector 22 for selecting a word line WL and a bit line selector 24 for selecting a bit line BL in addition to the memory cells (MS11 to MSij) arranged in an array. . The memory cell portion in the memory cell array 20 corresponds to, for example, a circuit similar to the circuit shown in FIG. 3 described above, but in FIG. 4, for convenience of illustration, wiring in the circuit is set for this memory cell portion. Parts are omitted.

  Selection of the memory cell 10 is performed by the word line selector 22 and the bit line selector 24. The word line selector 22 and the bit line selector 24 are also connected to the address line 25. Address setting to the address line 25 is performed by the control circuit 26.

<Set driver circuit>
The set driver circuit 30 includes a voltage application circuit 32 that applies a predetermined voltage (and current) to the memory cell 10 selected at the time of writing, a monitor circuit 34 that detects the voltage of the bit line, and a In response to the notification, the power supply to the memory cell 10 is constituted by a cutoff circuit 36 and the like.

  The set driver circuit 30 includes a precharge circuit 38 that sets the voltage of the bit line BL to a predetermined value before writing. The precharge circuit 38 avoids a malfunction in the writing process.

<Reset driver circuit>
The reset driver circuit 40 includes a voltage application circuit 42 that applies a predetermined voltage (and current) to the memory cell 10 selected at the time of writing, a monitor circuit 44 that detects the voltage of the bit line, and a In response to the notification, the power supply to the memory cell 10 is cut off.

  The reset driver circuit 40 includes a precharge circuit 48 that sets the voltage of the bit line BL to a predetermined value before writing. The precharge circuit 48 avoids a malfunction in the writing process.

<Control circuit>
The control circuit 26 includes a CPU (Central Processing Unit) 26a, a memory 26b that stores a control program for the CPU 26a, a bus 26c that transmits signals between them, and the like.

  The control circuit 26 has the above-described configuration, and controls the write operation in the set driver circuit 30 and the reset driver circuit 40 via (via) the control signals 27a and 27b, and also by the control signal 27c. The read operation in the read circuit 28 is controlled. At that time, the control circuit 26 also controls the memory cell array 20 by the control signal 27d.

<Read circuit>
The read circuit 28 includes a sense amplifier (not shown), and the voltage of the bit line BL is measured by the sense amplifier to recognize the storage state of the selected memory cell.

-Circuit configuration example of set driver circuit-
Next, individual blocks of the circuit (memory cell array 20 and its peripheral circuits) shown in FIG. 4 will be described with reference to the drawings. First, the set driver circuit 30 will be described. FIG. 5 is a circuit diagram illustrating an example of a set driver circuit according to the first embodiment.

<Memory cell array>
As shown in the figure, the memory cell array 20 is arranged between the bit line BL and the reference voltage Vss. In the drawing, for convenience of illustration, only one of the many memory cells existing in the memory cell array 20 is shown as a representative. The other memory cells are arranged in parallel with the memory cell 10 shown in the drawing.

  In the memory cell 10, as shown in the drawing, the resistance memory element 12 and the cell selection transistor 14 (TR11) are connected in series. Specifically, one end of the resistance memory element 12 is connected to the bit line BL, and the other end is connected to the drain D of TR11. The source S of TR11 is connected to the reference voltage Vss, and the gate G of TR11 is connected to the word line WL.

  The resistance value of the resistance memory element 12 is several kΩ in the low resistance state and several tens k to 1000 kΩ in the high resistance state. Unlike a normal resistor, the resistance memory element 12 has a very small area dependency on the resistance value.

  Since it is necessary to provide the same number of cell selection transistors 14 connected in series to the resistance memory element 12 as the resistance memory element 12, it is desirable that the area be as small as possible.

  As an example of the cell selection transistor 14 having a small area, a structure in which the ratio of the gate width to the gate length is 2.8 (gate width = 0.5 μm / gate length = 0.18 μm) can be considered. When such a structure is used, the cell selection transistor 14 having an on-resistance of about 2 kΩ can be formed. When such a cell selection transistor 14 is used, the resistance value in the low resistance state is about 4 kΩ (and the maximum current during the reset operation is several hundred μA so that a necessary voltage is applied to the cell selection transistor 14. It is desirable to use a resistance memory element 12 having a degree of

<Set voltage application circuit>
As shown in FIG. 5, the set voltage application circuit 32 includes a current mirror circuit having TR32 and TR33. The current mirror circuit is a stable power supply connected to the power supply Vdd. In the current mirror circuit, the end opposite to the side connected to the power supply Vdd is connected to the drains D of the bit lines BL and TR31 as shown in the figure.

  Here, in order to increase the memory capacity density of the nonvolatile semiconductor device, the cell selection transistor 14 (TR11) in the memory cell 10 is an nMOS and the transistors (TR32, TR33) constituting the current mirror circuit are pMOS. Is preferred.

  The TR 31 is provided between the set voltage application circuit 32 and a cutoff circuit 36 described later, and enables the operation of the set driver circuit 30 at the time of writing. The drain D of TR31 is connected to the source S of TR32, that is, the node N1, and the source S of TR31 is connected to the cutoff circuit 36 (specifically, the drain D of TR34). The gate G of TR31 is connected to a set write enable signal SetWE that permits writing. When performing the writing process, the SetWE signal is set to a high level (for example, about 1.5 to 1.7 V) in advance.

<Cutoff circuit>
As shown in the figure, the cutoff circuit 36 is provided between the aforementioned TR31 and the reference voltage Vss. The cutoff circuit 36 includes, for example, a transistor TR34 disposed between TR31 and the reference voltage Vss, and its drain D is connected to the source S of TR31. The source S of TR34 is connected to the reference voltage Vss, and the output of the monitor circuit 34 is connected to the gate G of TR34. The reference voltage Vss may be a ground (GND) level, for example. The transistor TR34 has, for example, an nMOS structure.

<Monitor circuit>
The monitor circuit 34 includes, for example, two inverters IN11 and IN12 connected in series as shown in the drawing. The input of the inverter IN11 is connected to the bit line BL, and the output is connected to the input of the inverter IN12. As described above, the output of the inverter IN12 is connected to the gate G of the transistor TR34 constituting the cutoff circuit 36.

  Here, for the inverter IN11 connected to the bit line BL, the threshold voltage (threshold voltage) is set to a value that allows the transition to the low resistance state. The threshold value of IN11 is, for example, 1.0 V to 1.2 V, but the optimum value is determined according to the material constituting the resistance memory element 12 and the characteristics of the peripheral circuit of the resistance memory element 12. To do. There is no particular limitation on the subsequent inverter IN12.

  In this specification, “threshold voltage” and “threshold voltage” are used as synonymous terms.

  The inverter IN11 has, for example, a CMOS structure input section (not shown) composed of a pMOS transistor and an nMOS transistor. Then, the threshold voltage of this input unit becomes the threshold voltage of the monitor circuit 34.

  Here, the relationship between the form of the CMOS structure and the threshold voltage will be described. FIG. 9 is a graph showing the relationship between the ratio of the gate width of the nMOS and the gate width of the pMOS and the threshold voltage of the input section in the input section of the monitor circuit having the CMOS structure.

  As shown in FIG. 9, the threshold voltage can be controlled by changing the ratio of the gate width of the nMOS and the gate width of the pMOS. Specifically, by setting the ratio of the gate width of the nMOS to the gate width of the pMOS larger than 1, that is, by making the gate width of the pMOS wider than the gate width of the nMOS, the threshold voltage is set to 1.0 V to It can be 1.2V.

  If the gate width of the nMOS is 0.36 μm and the gate width of the pMOS is 7.2 μm under a predetermined wiring rule, the threshold voltage can be about 1.1V.

  In this figure, the example in which the number of inverters constituting the monitor circuit 34 is two is shown, but four or more even number of inverters may be connected in series in order to adjust the timing.

<Precharge circuit>
As shown in the figure, the precharge circuit 38 is provided between the power supply Vdd and the bit line BL. For example, the precharge circuit 38 is disposed between the bit line BL and the power supply Vdd, has a transistor TR35 having a pMOS structure, and the drain D of TR35 is connected to the power supply Vdd. The gate G of TR35 is connected to the control signal PrSET from the control circuit 26, and the source S of TR35 is connected to the bit line BL.

-Set driver circuit write operation-
Next, the write operation of the set driver circuit 30 will be described. FIG. 6 is a timing chart illustrating the write operation of the set driver circuit according to the first embodiment.

  Step 1: First, the bit line BL is precharged. That is, the set precharge signal PrSET is set to Low level to turn on TR35 so that the bit line BL has substantially the same voltage value as the power supply Vdd. The voltage of the power supply Vdd is about 1.8V, for example.

  As described above, the precharge circuit 38 determines one end of the resistance memory element 12 at a predetermined voltage before applying a voltage to the resistance memory element 12.

  Step 2: Next, the SetWE signal is validated in this state. That is, the SetWE signal is set to High level to turn on TR31. At this time, since TR34 is already in the ON state after the precharge in Step 1, when TR31 is turned on, the voltage value of the node N1 is greatly reduced, and a large current easily flows through the path of L1. .

  As a result, the current mirror circuit operates and a large current easily flows through the path L2. However, in this state, since the cell selection transistor TR11 is in an OFF state, no large current flows through the path L2, and no high voltage is applied to the resistance memory element 12. (That is, the resistance memory element 12 is still in a high resistance state.) At this time, the TR 35 is turned on by the precharge in step 1, and the voltage value of the bit line BL is equal to the power supply Vdd. The values are substantially the same (approximately 1.6 V to 1.8 V).

  Step 3: Next, the precharge of the bit line BL is stopped. That is, the set precharge signal PrSET is returned to the high level (for example, about 1.5 V to 1.8 V), and the TR 35 is turned off.

  As described above, the precharge circuit 38 turns on the internal transistor TR35 to set one end of the resistance memory element 12 to a predetermined voltage, and then turns off the transistor 35 to stop the precharge.

  Step 4: Next, the memory cell 10 to be written is selected. That is, the control circuit 26 designates an address with respect to the address line 25 and enables the word line WL of the memory cell 10. As a result, the word line WL becomes a high level (for example, 1.5 to 1.7 V), and the cell selection transistor TR11 is turned on. As soon as TR11 is turned on, a high voltage (for example, about 1.6 V) that can be set is applied to the resistance memory element 12. The voltage applied to the resistance memory element is shown in the graph “VR” in FIG.

  Step 5: Next, the resistance memory element 12 is set. That is, when a settable high voltage is applied for a predetermined time (several ns to 50 ns), the resistance memory element 12 enters the set state, and the resistance memory element 12 rapidly changes from the high resistance state to the low resistance state.

  In this way, the voltage application circuit 32 applies a voltage capable of switching the resistance state of the resistance memory element 12 to both ends of the resistance memory element 12, and then (the voltage capable of switching the resistance state). The resistance state is switched after a predetermined time has elapsed (after the voltage is applied).

  Step 6: Next, the set state is detected by the monitor circuit. That is, when the resistance memory element 12 transitions to the low resistance state, the voltage of the bit line BL rapidly decreases accordingly. When the voltage value of the bit line BL becomes lower than the threshold voltage (for example, about 1.0 V to 1.2 V) of the inverter IN11 in the monitor circuit 34, the monitor circuit 34 operates.

  Regarding the threshold voltage of the inverter IN11, in order to increase the sensitivity of the monitor circuit 34, during the transition of the resistance memory element 12 to the low resistance state, that is, after the resistance state starts switching, It is desirable to set so that the voltage value of the bit line BL reaches the threshold voltage value of the inverter IN11.

  The monitor circuit 34 changes (inverts) the logic of an internal logic element when the voltage of the bit line BL reaches a predetermined threshold voltage value. That is, when the voltage value is low level, it changes from low level to high level, and when the voltage value is high level, it changes from high level to low level.

  Step 7: Next, power supply to the resistance memory element 12 is cut off. That is, the monitor circuit 34 detects the set of the resistance memory element 12, and the output signal StatSET of the monitor circuit changes to a low level (for example, about 0V to 0.5V). The completion of setting can be notified to the outside by this StatSET. When the StatSET signal becomes low level, TR 34 in the cutoff circuit 36 is turned off, and the current in the path L1 is cut off.

  Then, the current mirror circuit in the set voltage application circuit 32 is activated, and the current flowing through the path L2 is interrupted. In the case of the set, the time from when the resistance state of the resistance memory element 12 is switched to when the current in the path L1 is cut off is several ns to several tens ns.

  Thus, the cutoff circuit 36 limits the current of the current limiting circuit that limits the amount of current supplied to the resistance memory element. Here, the current limiting circuit is the current mirror circuit, and the cutoff circuit 36 limits the amount of current supplied to the resistance memory element by blocking one of the current paths in the current mirror circuit.

  By the steps as described above, writing to set (set) the resistance memory element 12 in a low resistance state is performed reliably.

The write operation when the resistance memory element 12 is initially in the high resistance state has been described above. In order to simplify the circuit, when the above-described writing is performed on the resistance memory element 12 in the low resistance state, the low resistance state does not change and the low resistance state is maintained as it is. desirable.
Regarding this point, when the resistance memory element 12 is in the low resistance state by the current limiting function of the current mirror circuit, the voltage value applied to the resistance memory element 12 is a value at which the resistance state does not change (for example, 0.6 V). The following). Therefore, when writing is performed in the steps as described above, the resistance state of the resistance memory element 12 remains unchanged in the low resistance state. The completion of the setting is immediately notified to the outside while the low resistance state is maintained.

-Circuit configuration example of reset driver circuit-
Next, the reset driver circuit 40 will be described. FIG. 7 is a circuit diagram illustrating an example of a set driver circuit according to the first embodiment.

<Memory cell array>
Since the memory cell array 30 has already been described in the section of the set driver circuit, description thereof is omitted here.

<Reset voltage application circuit>
As shown in FIG. 7, the reset voltage application circuit 42 is configured by a current mirror circuit having TR42 and TR43. The current mirror circuit is a stable power supply connected to the power supply Vdd. In the current mirror circuit, the end opposite to the side connected to the power supply Vdd is connected to the drains D of the bit lines BL and TR41 as shown in the figure.

  Here, in order to increase the memory capacity density of the nonvolatile semiconductor device, the cell selection transistor 14 (TR11) in the memory cell 10 is an nMOS, and the transistors (TR42, TR43) constituting the current mirror circuit are pMOS. Is preferred.

  The TR 41 is provided between the reset voltage application circuit 42 and a cutoff circuit 46 described later, and enables the operation of the reset driver circuit 40 at the time of writing. The drain D of TR41 is connected to the source S of TR42, that is, the node N2, and the source S of TR41 is connected to the cutoff circuit 46 (specifically, the drain D of TR44). The gate G of TR41 is connected to a reset write enable signal ResetWE that permits writing. When performing the writing process, the ResetWE signal is set to a high level (for example, about 1.5 to 1.7 V) in advance.

<Cutoff circuit>
As shown in the figure, the cutoff circuit 46 is provided between the aforementioned TR 41 and the reference voltage Vss. The cutoff circuit 46 includes, for example, a transistor TR44 disposed between TR41 and the reference voltage Vss, and its drain D is connected to the source S of TR41. The source S of TR44 is connected to the reference voltage Vss, and the output of the monitor circuit 44 is connected to the gate G of TR44. The transistor TR44 has, for example, an nMOS structure.

<Monitor circuit>
The monitor circuit 44 has, for example, one inverter IN21 and a flip-flop circuit FF as shown in the figure. The input of the inverter IN21 is connected to the bit line BL, and the output thereof is connected to one input of the flip-flop circuit FF.

  Here, for the inverter IN21, the threshold voltage is set to a value that can be recognized as having transitioned to the high resistance state. The threshold voltage of IN21 is, for example, 1.0 V to 1.2 V, and the optimum value is determined according to the material constituting the resistance memory element 12 and the characteristics of the peripheral circuit of the resistance memory element 12. .

  The inverter IN21 has, for example, a CMOS structure input section (not shown) composed of a pMOS structure transistor and an nMOS structure transistor, and the threshold voltage of this input section becomes the threshold voltage of the monitor circuit 44. . Note that. Since the relationship between the CMOS structure in the inverter IN21 and the threshold voltage is the same as that of the monitor circuit in the set driver circuit, the description thereof is omitted here.

  The flip-flop circuit FF is composed of, for example, two NAND circuits (NA1, NA2). The output of the flip-flop circuit FF is connected to the gate G of the TR 44 in the cutoff circuit 46. The output of the inverter IN21 is connected to one input of the flip-flop circuit FF, and the X-StartRESET signal is connected to the other input. The X-StartRESET signal sets the output of the flip-flop circuit FF (StatRESET signal) to a high level.

  In the flip-flop circuit FF, when the voltage of the bit line BL drops after the write operation by the reset driver circuit 40 is completed, the TR44 of the cutoff circuit 46 is turned on again by the voltage change, and the reset driver circuit 40 is restarted. Prevents startup.

  Here, the basic operation of the flip-flop circuit FF will be described. First, the X-StartRESET signal is once set to the Low level and then returned to the High level, and then the StatRESET signal is set to the High level. Next, when the voltage of the bit line BL rises by the write operation and the voltage of the bit line BL exceeds the threshold voltage value of the input of the inverter IN21, the StatRESET signal changes from the High level to the Low level.

  After that, for example, even if the voltage of the bit line BL drops and falls below the threshold voltage value of the input of the inverter IN21, the output level of the NAND circuit NA2 changes because the voltage level of the StatRESET signal is low level. The logic inside the flip-flop circuit FF does not change. That is, the logic of the output of the flip-flop circuit FF does not change, and the voltage of the StatRESET signal (input signal to the gate G of TR44) is held at the low level.

  When the write operation is performed again, the X-Start RESET signal may be changed from the High level to the Low level, and the Stat RESET signal may be returned to the High level. When the StatRESET signal becomes High level, the X-StartRESET signal is returned to High level (from Low level). As described above, the X-StartRESET signal has a function for setting the flip-flop circuit FF to the initial state (initial standby) and enabling the operation again.

  As described above, the monitor circuit 44 functions as a stable operation circuit that prevents the logic from changing again after the voltage of the bit line BL reaches a predetermined threshold voltage and the internal logic changes. . Further, the monitor circuit 44 has a function of enabling the logic to be released from the outside according to the X-StartRESET signal as necessary.

  In addition, although the example which showed the inverter which comprises the input part of the monitor circuit 34 was shown in this figure, in order to adjust a timing, it is good also as a structure by which three or more odd number inverters are connected in series. .

<Precharge circuit>
As shown in the figure, the precharge circuit 48 is provided between the bit line BL and the reference voltage Vss. For example, the precharge circuit 48 is disposed between the bit line BL and the reference voltage Vss, has a transistor TR45 having an nMOS structure, and the drain D of TR45 is connected to the bit line BL. The gate G of TR45 is connected to the control signal PrRESET from the control circuit 26, and the source S of TR45 is connected to the reference voltage Vss.

-Write operation of reset driver circuit-
Next, the write operation of the reset driver circuit 40 will be described. FIG. 8 is a timing chart illustrating the write operation of the reset driver circuit according to the first embodiment.

  Step 1: First, the bit line BL is precharged. That is, the reset precharge signal PrRESET is set to a high level (for example, about 1.5 to 1.8 V) to turn on the TR 45 so that the bit line BL has substantially the same voltage value as the reference voltage Vss. As described above, the precharge circuit 48 determines one end of the resistance memory element 12 at a predetermined voltage before the voltage is applied to the resistance memory element 12, and prevents malfunction of the circuit.

  At this time, the X-StartRESET signal is changed from High level to Low level, and the StatRESET signal is changed from Low level to High level.

  Note that the circuit operates correctly even if one of the PrRESET signal and the X-StartRESET signal operates at an earlier timing than the other signals due to wiring delay, transistor characteristic variation, and the like.

  Step 2: Next, the memory cell 10 to be written is selected. That is, the control circuit 26 designates an address with respect to the address line 25 and enables the word line WL of the memory cell 10. As a result, the word line WL becomes a high level (for example, 1.5 to 1.7 V), and the cell selection transistor TR11 is turned on.

  Step 3: Next, the ResetWE signal is enabled. That is, the ResetWE signal for enabling the reset driver circuit 40 is set to a high level (for example, about 1.5 to 1.7 V), and the TR 41 is turned on. At this time, the transistor TR45 of the precharge circuit 48, the TR44 of the cutoff circuit 46, and the TR11 of the memory cell 10 have already been turned on by the processing of Step 1 and Step 2, so that the TR41 is turned on, so that the current The mirror circuit is activated and a large current begins to flow through the path L4.

  However, in this state, since the transistor TR45 of the precharge circuit 48 is on, a current flows to the precharge circuit 48 side, and almost no current flows to the path L0 on the memory cell 10 side. For this reason, the voltage of the bit line BL is hardly changed at this time, and the voltage value of the bit line BL is maintained at substantially the same value (about 0 V to 0.5 V) as the reference voltage Vss. As a result, a high voltage is not applied to the resistance memory element 12, and the resistance memory element 12 maintains a low resistance state.

  Step 4: Next, precharge of the bit line BL is stopped. That is, the PrRESET signal is returned to the low level, the TR45 is turned off, and the precharge is stopped. Further, the precharge is stopped and the X-StartRESET signal is changed from the low level to the high level. As soon as TR11 is turned on, a high voltage (approximately 0.9 V) that can be set is applied to the resistance memory element 12. The voltage applied to the resistance memory element is shown in the graph “VR” in FIG.

  Step 5: Next, the resistance memory element 12 is reset. When the resettable high voltage is applied for a predetermined time, the resistance memory element 12 is reset, and the resistance memory element 12 is rapidly changed from the low resistance state to the high resistance state. The time required for resetting the resistance memory element 12 (the predetermined time) varies depending on conditions, and is usually several hundred ns to several tens of ms, but here, for example, 800 ns as shown in FIG.

  In this way, the voltage application circuit 42 applies a voltage capable of switching the resistance state of the resistance memory element 12 to both ends of the resistance memory element 12, and applies a voltage capable of switching the resistance state. The resistance state is switched after a predetermined time has elapsed.

  Step 6: Next, the reset state is detected by the monitor circuit. That is, when the resistance memory element 12 transitions to the high resistance state, the voltage of the bit line BL rapidly increases accordingly. When the voltage value of the bit line BL becomes higher than a threshold voltage (for example, about 1.0 V to 1.2 V) of the inverter IN21 in the monitor circuit 44, the monitor circuit 44 is activated. At this time, the completion of the reset can be notified to the outside by a StatRESET signal.

  As described above, the threshold voltage of the inverter IN21 is switched during the transition of the resistance memory element 12 to the low resistance state, that is, after the resistance state starts to be switched, in order to increase the sensitivity of the monitor circuit 44. It is desirable to set so that the voltage value of the bit line BL reaches the threshold voltage of the inverter IN21 before finishing.

  The monitor circuit 44 changes (inverts) the logic of an internal logic element when the voltage of the bit line BL changes from a low level to a high level and reaches a predetermined threshold voltage value.

  Step 7: Next, power supply to the resistance memory element 12 is cut off. That is, the monitor circuit 44 detects the reset of the resistance memory element 12 and changes the output signal StatRESET of the monitor circuit from a high level to a low level (for example, about 0 V to 0.5 V). When the StatRESET signal changes to the Low level, TR44 in the cutoff circuit 46 is turned off, and the current in the path L3 is cut off.

  Then, the current mirror circuit in the voltage application circuit 42 is activated, and the current flowing through the path L4 is interrupted. In the case of reset, the time from when the resistance state of the resistance memory element 12 is switched to when the current in the path L4 is cut off is several ns to several tens ns.

  As described above, the cutoff circuit 46 limits the current of the current limiting circuit that limits the amount of current supplied to the resistance memory element. The current limiting circuit is, for example, the current mirror circuit as shown in FIG. 7, and the blocking circuit 46 limits the amount of current supplied to the resistance memory element by blocking one current path in the current mirror circuit. To do.

  After that, the current of the path L3 is cut off, so that the voltage level of the bit line BL that has risen falls and falls below the threshold voltage value of the inverter IN21. However, the voltage level of the StatRESET signal becomes low Therefore, the output of the NAND circuit NA2 does not change, and the logic inside the flip-flop circuit FF does not change. That is, the logic of the output of the flip-flop circuit FF does not change, and the voltage of the StatRESET signal (input signal to the gate G of TR44) is held at the low level.

  By the steps as described above, writing to reset (reset) the resistance memory element 12 is reliably performed.

  The write operation when the resistance memory element 12 is initially in the low resistance state has been described above. In order to simplify the circuit, when the above-described writing is performed on the resistance memory element 12 in the high resistance state, the high resistance state does not change and the high resistance state is maintained as it is. desirable.

  Regarding this point, for example, when the resistance memory element 12 is in a high resistance state from the beginning, immediately after the high voltage is applied to the resistance memory element 12 in step 4, the voltage of the bit line BL becomes the threshold of the monitor circuit 21. It becomes higher than the hold voltage value. From this, it can be realized by adjusting the power supply to the resistance memory element 12 to be instantaneously cut off in a shorter time (for example, several ns) than the time when the resistance state of the resistance memory element 12 changes. . Also, the reset completion is immediately notified to the outside.

  As described above, according to the present embodiment, the write circuit to the resistance memory element is configured by a circuit in which elements composed mainly of field effect transistors (MOS FETs) are combined. Therefore, it is possible to easily manufacture a nonvolatile memory device by diverting a conventional CMOS formation process.

  Further, it is not necessary to provide a diffused resistor or a polysilicon resistor that requires a predetermined size corresponding to the resistance value as the reference resistor. Therefore, it is possible to avoid an increase in the scale of the circuit, which is suitable for use as a large capacity memory.

  Furthermore, since the current supply source is instantaneously cut off before a large current flows through the resistance memory element 12, there is an advantage that a simple circuit is sufficient.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Memory cell 12 ... Resistance memory element 12a, 12c ... A pair of electrode 12b ... Resistance memory material 14 ... Cell selection transistor 16 ... Bit line selection transistor 20 ... Memory cell array 22 ... Word line selector 24 ... Bit line selector 25 ... Address line 26: Control circuit 26a ... CPU
26b ... Memory 26c ... Buses 27a, 27b, 27c, 27d ... Control signal 28 ... Read circuit 30 ... Set driver circuit 32, 42 ... Voltage application circuit 34, 44 ... Monitor circuit 36, 46 ... Cut-off circuit 38, 48 ... Precharge Circuit 40 ... Reset driver circuit

Claims (4)

In a nonvolatile semiconductor memory device having a resistance memory element that switches between a high resistance state and a low resistance state by application of a voltage,
A first voltage application circuit for supplying a power to the resistance memory element and generating a first voltage at one end of the resistance memory element when the resistance memory element is in a high resistance state;
A second voltage application circuit for supplying power to the resistance memory element and generating a second voltage lower than the first voltage at one end of the resistance memory element when the resistance memory element is in a low resistance state; ,
A first monitor circuit having a predetermined threshold voltage and detecting that the first voltage has reached the first threshold voltage;
It has a predetermined threshold voltage, and the second monitor circuit detects that the second voltage reaches a second threshold voltage,
A first cutoff circuit that shuts off a current supply from the first voltage application circuit to the resistance memory element based on the detection of the first monitor circuit;
A non-volatile semiconductor memory device comprising: a second cutoff circuit that cuts off voltage application from the second voltage application circuit to the resistance memory element based on the detection of the second monitor circuit .   The second monitor circuit, when the second voltage falls below the predetermined threshold after the second voltage reaches the predetermined threshold voltage and the internal logic changes, The nonvolatile semiconductor memory device according to claim 1, wherein the logic after the change is maintained.   3. The nonvolatile semiconductor memory according to claim 2, wherein the second monitor circuit further has a function of releasing the held state from the outside after the logic is held in a state in which the logic does not change. apparatus. The second monitor circuit has a flip-flop circuit that combines two NAND circuits,
When the second voltage falls below the predetermined threshold after the second voltage reaches the predetermined threshold voltage and the internal logic changes by the flip-flop circuit, the change The non-volatile semiconductor memory device according to claim 2, wherein the subsequent logic is maintained.

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