JP2015230736A - Resistance change type nonvolatile storage and its writing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a resistance change type nonvolatile storage configured to perform verification writing operation that combines improvement of precision of recording and retrieval of data with speed improvement in writing of data and its writing method.SOLUTION: A resistance change type nonvolatile storage performs verification writing operation configured to apply a voltage pulse to newly change a resistive state to a resistance change type element that fails to satisfy a criterion for checking that the resistive state has changed regardless of application of a voltage pulse for changing the resistive state. When the frequency of verification writing operation performed for a prescribed number of resistance change type elements to be a writing object exceeds a predetermined frequency, the storage waits for a prescribed time without applying an additional voltage pulse.

Description

  The present invention relates to a variable resistance nonvolatile memory device and a writing method thereof. More specifically, the present invention relates to a variable resistance nonvolatile memory device that performs a verify write operation and a write method thereof.

  Patent Document 1 discloses a technique related to a NAND flash memory. In the nonvolatile memory device described in Patent Document 1, the threshold value at the time of erasure is included in the first threshold value distribution, and the threshold value at the time of data writing is included in the second threshold value distribution. A memory cell array is formed by arranging a plurality of nonvolatile memory cells in a matrix. When erasing data, an erasing voltage is applied to the nonvolatile memory cell to be erased, and the threshold value at the time of erasing is moved so as to be included in the first threshold value distribution. It is confirmed by the erase verify operation using the erase verify level as an index that the threshold value of the nonvolatile memory cell from which data is to be erased has moved into the first threshold distribution. When writing data, a write voltage is applied to the nonvolatile memory cell to be written, and the threshold value at the time of writing is moved so as to be included in the second threshold distribution. The fact that the threshold value of the nonvolatile memory cell to which data is to be written has moved into the second threshold distribution is confirmed by the write verify operation using the write verify level as an index. The erase verify level and the write verify level are adaptively changed based on at least one of the status of the erase operation and the status of the write operation.

  Patent Document 2 and Patent Document 3 disclose variable resistance nonvolatile memory elements using tantalum oxide (TaO) as a variable resistance layer.

JP 2012-27962 A International Publication No. 2008/149484 International Publication No. 2009/050833

  The present disclosure suppresses an increase in the number of repetitions of a verify write operation in a variable resistance nonvolatile memory device that performs a verify write operation.

  In order to achieve the above object, one aspect of a writing method according to the present disclosure is a writing method of a variable resistance nonvolatile memory device including a memory cell array including a plurality of memory cells including a variable resistance element. In the write operation, when the first voltage pulse is applied, the resistance variable element changes from the first resistance state used for storing the first information to the first resistance state used for storing the second information. To change to a second resistance state having a low resistance value, and to change the resistance state from the second resistance state to the first resistance state when a second voltage pulse is applied. An additional voltage pulse for changing the resistance state is applied to the resistance variable element that does not satisfy the determination condition for confirming that the resistance state has changed despite the application of the voltage pulse. When the number of the verify write operations performed on the predetermined number of resistance variable elements to be written exceeds the predetermined number, the additional voltage pulse is not applied and the predetermined voltage pulse is not applied. Wait for time.

  The present disclosure can also be realized as a variable resistance nonvolatile memory device including a pulse applying device that executes the above writing method.

  According to the variable resistance nonvolatile memory device and the writing method thereof of the present disclosure, an increase in the number of repetitions of the verify write operation can be suppressed.

FIG. 1 is a block diagram illustrating an example of a schematic configuration of the variable resistance nonvolatile memory device according to the first embodiment. FIG. 2 is a schematic diagram illustrating an example of a schematic configuration of a memory cell included in the variable resistance nonvolatile memory device according to the first embodiment. FIG. 3 is a flowchart illustrating an example of a writing method of the variable resistance nonvolatile memory device according to the first embodiment. FIG. 4 is a flowchart illustrating an example of a writing method of the variable resistance nonvolatile memory device according to the second embodiment. FIG. 5 is a flowchart illustrating an example of a writing method of the variable resistance nonvolatile memory device according to the third embodiment. FIG. 6 is a flowchart illustrating an example of a writing method of the variable resistance nonvolatile memory device according to the fourth embodiment. FIG. 7 is a flowchart illustrating an example of a writing method of the variable resistance nonvolatile memory device according to the fifth embodiment. FIG. 8 is a block diagram illustrating a schematic configuration of a variable resistance nonvolatile memory device according to a study example. FIG. 9 is a circuit diagram illustrating an example of a schematic configuration of a sense amplifier included in the variable resistance nonvolatile memory device according to the study example. FIG. 10 is a schematic diagram illustrating the determination level of the sense amplifier in the writing method of the variable resistance nonvolatile memory device according to the study example. FIG. 11A is a schematic flowchart for explaining a verify write operation at the time of increasing the resistance of the variable resistance nonvolatile memory device according to the study example. FIG. 11B is a schematic flowchart for explaining a verify write operation when the resistance of the variable resistance nonvolatile memory device according to the study example is lowered. FIG. 12 is a table showing set voltages for each operation in the write method of the variable resistance nonvolatile memory device according to the study example. FIG. 13A is a timing chart illustrating a low resistance operation of the variable resistance nonvolatile memory device according to the study example. FIG. 13B is a timing chart illustrating a high resistance operation of the variable resistance nonvolatile memory device according to the study example. FIG. 13C is a timing chart illustrating a read operation of the variable resistance nonvolatile memory device according to the study example. FIG. 14 is a flowchart illustrating a writing method of the variable resistance nonvolatile memory device according to the study example. FIG. 15 shows a frequency distribution of resistance values in the resistance variable nonvolatile memory device (1 kbit) according to the study example when high resistance and low resistance are repeated 50,000 times without performing a verify operation. FIG. FIG. 16 is a diagram showing a frequency distribution of resistance values when the resistance change type nonvolatile memory device (1 kbit) according to the examination example repeats the high resistance and the low resistance 50,000 times while performing the verify operation. It is. FIG. 17 is a diagram illustrating the transition of the average number of times per one bit of the verify write operation when the resistance increase and the resistance decrease are repeated in the resistance change nonvolatile memory device according to the study example. FIG. 18 is a flowchart illustrating a write method of the variable resistance nonvolatile memory device according to the first embodiment. FIG. 19 is a flowchart illustrating a write method of the variable resistance nonvolatile memory device according to the second embodiment. FIG. 20 is a diagram showing the transition of the average number of times per bit of the low resistance verify write operation when the resistance increase and the resistance decrease are repeated in the resistance change nonvolatile memory device according to the second embodiment. It is. FIG. 21 is a diagram showing the transition of the average number of times per bit of the high resistance verify write operation when the resistance increase and the resistance decrease are repeated in the resistance variable nonvolatile memory device according to the second embodiment. It is. FIG. 22 is a diagram illustrating a transition of the variation ratio of the resistance value after the high resistance writing in the variable resistance element (7 bits) of the variable resistance nonvolatile memory device according to the example.

  In the variable resistance nonvolatile memory device, in order to achieve both improvement in data recording and reading accuracy and improvement in data writing speed, intensive studies were conducted. As a result, the following knowledge was obtained.

  In recent years, the minimum processing dimension of a nonvolatile memory device has become increasingly smaller, and as the miniaturization progresses, the reliability of the memory cell can be reduced.

  In order to improve the reliability, after the information writing operation to the element is performed, the information held by the element is confirmed, and when the desired information is not written, the writing operation is executed again. That is, it is conceivable to introduce a verify write operation.

  In the NAND flash memory, the deterioration proceeds in such a manner that the resistance state is uniformly shifted to the high resistance side or the low resistance side. For this reason, it is possible to cope with deterioration by a method as disclosed in Patent Document 1. That is, it is possible to cope with the deterioration by changing the erase (corresponding to one of high resistance and low resistance writing) verify level and the write (also the other) verify level uniformly in the same direction by Δvrfy.

  However, in the resistance change type nonvolatile memory element, the resistance value in the high resistance state decreases and the resistance value in the low resistance state increases. For this reason, only by changing the verify level uniformly as in Patent Document 1, either the high resistance writing or the low resistance writing can be improved, but the other cannot be improved.

  In the variable resistance nonvolatile memory element, a phenomenon in which a resistance value detected after writing varies. For example, even in an element written in a high resistance state using a voltage pulse having the same voltage and the same pulse width, the resistance value detected thereafter varies greatly depending on the element.

  FIG. 15 shows an example of the frequency distribution of the resistance values of the elements written in the high resistance state (HR) and the low resistance state (LR). It can be seen that the resistance value varies greatly both in the high resistance state (HR) and in the low resistance state (LR). FIG. 15 shows data related to a bipolar variable resistance nonvolatile memory element, but even a unipolar variable resistance nonvolatile memory element has a forament structure and uses a defect for resistance change. In the case of a resistance variable element, variation in resistance value occurs similarly (see, for example, Lee, SB et al., Applied Physics Letters, vol. 95, p. 122112 (2009)).

  The variation increases with device degradation. That is, in the variable resistance nonvolatile memory element, by repeating the write operation to the high resistance state and the low resistance state, the performance of the memory cell deteriorates, the resistance value in the high resistance state decreases, The resistance value increases. As the number of write operations increases, the deterioration of the element becomes more prominent, and the number of verify failures, that is, the number of times that a voltage pulse is applied again in the verify write operation increases, resulting in a problem that the writing speed decreases.

  FIG. 17 is a diagram illustrating an example of the relationship between the number of write cycles and the number of verify failures when the determination condition is constant. As shown in the figure, the average number of verify failures per bit increases rapidly as the number of write cycles increases.

  The inventor of the present application has found a phenomenon that when the number of verify failures increases, the verify operation is interrupted, waits for a predetermined time, and then when the verify write operation is performed again, the number of verify failures decreases significantly.

  This phenomenon is attributed to the recovery of the characteristics of a deteriorated device over time. Even when the number of verify failures increases, by not performing the write operation for a predetermined time until the write operation is performed again, the device characteristics are restored, and the number of verify failures when the write operation is performed again decreases. Therefore, the writing speed can be improved.

  In addition, as the number of verify failures is reduced, the number of write operations including rewriting is also reduced, so that deterioration caused by repeated writing can be suppressed. On the other hand, the accuracy of data recording and reading can be improved as compared with a configuration in which no verify operation is executed.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

  Each of the embodiments described below shows a specific example of the present invention. Numerical values, shapes, materials, components, arrangement positions and connection forms of components, steps, order of steps, and the like shown in the following embodiments are merely examples, and do not limit the present invention. In addition, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept of the present invention are described as arbitrary constituent elements constituting the embodiments. In the drawings, the same reference numerals are sometimes omitted. In addition, the drawings schematically show each component for easy understanding, and there are cases where the shape, dimensional ratio, and the like are not accurately displayed. Moreover, in a manufacturing method, the order of each process etc. can be changed as needed, and another well-known process can be added.

(First embodiment)
A write method for a variable resistance nonvolatile memory device according to the first embodiment is a write method for a variable resistance nonvolatile memory device including a memory cell array including a plurality of memory cells including a variable resistance device, the variable resistance device In the write operation, when a first voltage pulse is applied, the first resistance state used for storing the first information is changed from the first resistance state used for storing the second information to a second resistance value lower than that of the first resistance state. When the second voltage pulse is applied when changing to the two-resistance state, the second resistance state changes from the second resistance state to the first resistance state, and the voltage pulse for changing the resistance state is applied. Regardless of the condition for confirming that the resistance state has changed, the verify write operation that applies an additional voltage pulse to change the resistance state does not satisfy the judgment condition. The performed, the number of verify-write operation performed for a predetermined number of the resistance variable element to be written exceeds a predetermined number, waits for a predetermined without applying an additional voltage pulse time.

  The variable resistance nonvolatile memory device according to the first embodiment includes a memory cell array having a plurality of memory cells including a variable resistance element, and the variable resistance element receives a first voltage pulse in a write operation. The first resistance state used for storing the first information is changed to the second resistance state used for storing the second information and having a resistance value lower than that of the first resistance state, and the second voltage pulse is applied. And a determination condition for confirming that the resistance state has changed despite the application of a voltage pulse for changing the resistance state, which has a characteristic of changing from the second resistance state to the first resistance state. A verify write operation is performed by applying an additional voltage pulse for changing the resistance state to a resistance variable element that is not satisfied, and this is performed for a predetermined number of resistance variable elements to be written. If the number of verify-write operation exceeds a predetermined number, it waits for a predetermined time without applying an additional voltage pulses comprises a pulse applying device.

  With this configuration, it is possible to suppress an increase in the number of repetitions of the verify write operation.

  More specifically, for example, in the variable resistance nonvolatile memory device, it is possible to realize improvement in data writing speed and suppression of deterioration together with improvement in data recording and reading accuracy.

  First, terms will be defined.

  “Performing the verify write operation” does not necessarily mean that the write operation on the variable resistance element is not completed until the determination condition for confirming that the resistance state has changed is satisfied. In a case where the determination condition for confirming that the resistance state has changed is not satisfied, for example, if any condition is satisfied, the verify write operation may be stopped and the write operation to the resistance variable element may be terminated. .

  The “predetermined number of resistance variable elements to be written” may be one resistance variable element or a plurality of resistance variable elements.

  The “number of verify write operations” may be the number of times of application of additional voltage pulses continuously performed on the variable resistance element. Specifically, for example, the first voltage pulse is applied to change the resistance variable element in the first resistance state to the second resistance state, and then the resistance state of the resistance variable element is confirmed. Suppose that it was in the 1st resistance state. In this case, if the first additional voltage pulse is applied and then the resistance state of the resistance variable element is confirmed, it is assumed that the first resistance state is still present. Therefore, it is assumed that the second additional voltage pulse is applied. At this time, the number of verify write operations in the state where the second additional voltage pulse is applied is two.

  In other words, the “number of verify write operations” means the number of additional voltage pulses applied after a voltage pulse (initial pulse) is applied to the resistance variable element in order to change the resistance state prior to the verify write operation. It is good. In other words, the number of verify write operations may be reset by applying an initial pulse. The number of verify write operations may be reset by “waiting for a predetermined time”. Note that whether or not to perform the reset is arbitrary, and may not be reset.

  Note that there is no particular limitation on whether or not to wait for a predetermined time again in the next verify write operation after waiting for a predetermined time. In addition, there is no particular limitation on whether or not to wait for a predetermined time in the normal write operation after the verify write operation is completed and the verify write operation performed first after that.

  A voltage pulse (initial pulse) applied to the resistance variable element to change the resistance state prior to the verify write operation, and an additional voltage pulse applied to the resistance variable element to change the resistance state in the verify write operation These voltage pulses may be the same or different. For example, when a certain resistance variable element is changed from a low resistance state to a high resistance state, a resistance increasing pulse that is first applied to the element and the resistance state of the element is changed in a verify write operation on the element. The additional voltage pulse applied to may be the same, or the voltage and pulse width may be different.

  In addition, the voltage pulses applied to the resistance variable element in order to change the resistance state in each verify write operation may be the same or different from each other. For example, when a certain resistance variable element is changed from a low resistance state to a high resistance state, an additional voltage applied to change the resistance state of the element in the first verify write operation for the element. The pulse and the additional voltage pulse applied to change the resistance state of the element in the second verify write operation may be the same, or the voltage and the pulse width may be different from each other. Good.

  The “predetermined time” can be set according to the recovery characteristic of the variable resistance element. In general, the “predetermined time” can be set to a time longer than the time required for a normal write operation. More specifically, for example, the “predetermined time” may be 150 ns or more and 10 minutes or less. Alternatively, for example, the “predetermined time” may be 1 μs or more and 10 minutes or less. Alternatively, for example, the “predetermined time” may be 10 seconds or more and 10 minutes or less. Alternatively, for example, the “predetermined time” may be 15 seconds or more and 10 minutes or less.

[Device configuration]
FIG. 1 is a block diagram illustrating an example of a schematic configuration of the variable resistance nonvolatile memory device according to the first embodiment.

  In the example illustrated in FIG. 1, the variable resistance nonvolatile memory device 140 according to the first embodiment includes a memory cell array 120 and a pulse applying device 130. The memory cell array 120 includes a plurality of memory cells 110 including the resistance change element 100.

  When the first voltage pulse is applied, the resistance variable element 100 has a lower resistance value than the first resistance state used for storing the second information from the first resistance state used for storing the first information. It changes to the 2nd resistance state, and when the 2nd voltage pulse is applied, it has the characteristic which changes from the 2nd resistance state to the 1st resistance state. The polarity of the first voltage pulse and the polarity of the second voltage pulse may be different or the same.

  FIG. 2 is a schematic diagram illustrating an example of a schematic configuration of a memory cell included in the variable resistance nonvolatile memory device according to the first embodiment. In the example illustrated in FIG. 2, the memory cell 110 according to the first embodiment includes a resistance variable element 100 and an NMOS transistor 104. The resistance variable element 100 is formed by laminating a first electrode 100a, a resistance variable layer 100b, and a second electrode 100c.

  The resistance change layer 100b is interposed between the first electrode 100a and the second electrode 100c, and the resistance value reversibly changes based on an electrical signal applied between the first electrode 100a and the second electrode 100c. It is a layer to do. The resistance change layer 100b is a layer that reversibly transitions between a high resistance state and a low resistance state according to the polarity of the voltage applied between the first electrode 100a and the second electrode 100c, for example. In the example shown in FIG. 2, the resistance change layer 100b includes at least two layers of a first resistance change layer 100b-1 connected to the first electrode 100a and a second resistance change layer 100b-2 connected to the second electrode. Configured. The resistance change layer 100b may be composed of a single layer or may be composed of three or more layers.

  The first resistance change layer 100b-1 is composed of an oxygen-deficient first metal oxide, and the second resistance change layer 100b-2 is a second metal oxide having a lower degree of oxygen deficiency than the first metal oxide. It consists of In the second resistance change layer 100b-2 of the resistance change element 100, a minute local region in which the degree of oxygen deficiency reversibly changes according to the application of an electric pulse is formed. The local region is considered to include a filament composed of oxygen defect sites.

For example, the first metal oxide can be a first tantalum oxide (TaO _x , 0 <x <2.5). The second metal oxide can be a second tantalum oxide (TaO _y , x <y).

  “Oxygen deficiency” refers to an oxide having a stoichiometric composition (the stoichiometric composition having the highest resistance value in the case where there are a plurality of stoichiometric compositions) in a metal oxide. Is the ratio of oxygen deficiency to the amount of oxygen constituting. A metal oxide having a stoichiometric composition is more stable and has a higher resistance value than a metal oxide having another composition.

For example, when the metal is tantalum (Ta), the oxide having the stoichiometric composition according to the above definition is Ta ₂ O ₅ , and can be expressed as TaO _2.5 . The oxygen deficiency of TaO _2.5 is 0%, and the oxygen deficiency of TaO _1.5 is oxygen deficiency = (2.5−1.5) /2.5=40%. In addition, the oxygen excess metal oxide has a negative oxygen deficiency. In the present specification, unless otherwise specified, the oxygen deficiency is described as including a positive value, 0, and a negative value.

  An oxide with a low degree of oxygen deficiency has a high resistance value because it is closer to a stoichiometric oxide, and an oxide with a high degree of oxygen deficiency has a low resistance value because it is closer to the metal constituting the oxide.

“Oxygen content” is the ratio of oxygen atoms to the total number of atoms. For example, the oxygen content of Ta ₂ O ₅ is the ratio of oxygen atoms to the total number of atoms (O / (Ta + O)), which is 71.4 atm%. Therefore, the oxygen-deficient tantalum oxide has an oxygen content greater than 0 and less than 71.4 atm%. For example, when the metal constituting the first metal oxide and the metal constituting the second metal oxide are of the same type, the oxygen content has a corresponding relationship with the degree of oxygen deficiency. That is, when the oxygen content of the second metal oxide is larger than the oxygen content of the first metal oxide, the oxygen deficiency of the second metal oxide is smaller than the oxygen deficiency of the first metal oxide.

  A metal other than tantalum may be used as the metal constituting the resistance change layer. As a metal constituting the variable resistance layer, a transition metal or aluminum (Al) can be used. As the transition metal, tantalum (Ta), titanium (Ti), hafnium (Hf), zirconium (Zr), niobium (Nb), tungsten (W), nickel (Ni), or the like can be used. Since transition metals can take a plurality of oxidation states, different resistance states can be realized by oxidation-reduction reactions.

For example, when hafnium oxide is used, when the composition of the first metal oxide is HfO _x , x is 0.9 or more and 1.6 or less, and the composition of the second metal oxide is HfO _y . In this case, when y is larger than the value x, the resistance value of the resistance change layer can be stably changed at high speed. In this case, the film thickness of the second metal oxide may be 3 to 4 nm.

Further, when zirconium oxide is used, when the composition of the first metal oxide is ZrO _x , x is 0.9 or more and 1.4 or less, and the composition of the second metal oxide is ZrO _y . In this case, when y is larger than the value x, the resistance value of the resistance change layer can be stably changed at high speed. In this case, the film thickness of the second metal oxide may be 1 to 5 nm.

  Different metals may be used for the first metal constituting the first metal oxide and the second metal constituting the second metal oxide. In this case, the second metal oxide may have a lower degree of oxygen deficiency than the first metal oxide, that is, the resistance may be higher. By adopting such a configuration, the voltage applied between the first electrode and the second electrode at the time of resistance change is more distributed to the second metal oxide, and the second metal oxide It is possible to make the oxidation-reduction reaction generated in the process easier.

  Further, different materials are used for the first metal constituting the first metal oxide serving as the first resistance change layer and the second metal constituting the second metal oxide serving as the second resistance change layer. In this case, the standard electrode potential of the second metal may be lower than the standard electrode potential of the first metal. The standard electrode potential represents a characteristic that the higher the value is, the more difficult it is to oxidize. Thereby, an oxidation-reduction reaction easily occurs in the second metal oxide having a relatively low standard electrode potential. The resistance change phenomenon is caused by a change in the filament (conducting path) caused by an oxidation-reduction reaction in a minute local region formed in the second metal oxide having a high resistance. ) Will change.

For example, stable resistance change operation can be obtained by using oxygen-deficient tantalum oxide (TaO _x ) as the first metal oxide and titanium oxide (TiO ₂ ) as the second metal oxide. Titanium (standard electrode potential = −1.63 eV) is a material having a lower standard electrode potential than tantalum (standard electrode potential = −0.6 eV). As described above, by using a metal oxide having a standard electrode potential lower than that of the first metal oxide as the second metal oxide, a redox reaction is more likely to occur in the second metal oxide. As another combination, aluminum oxide (Al ₂ O ₃ ) can be used for the second metal oxide to be the high resistance layer. For example, oxygen-deficient tantalum oxide (TaO _x ) may be used for the first metal oxide, and aluminum oxide (Al ₂ O ₃ ) may be used for the second metal oxide.

  The resistance change phenomenon in the variable resistance layer of the laminated structure is that a redox reaction occurs in a small local region formed in the second metal oxide having a high resistance, and a filament (conductive path) in the local region is formed. By changing, the resistance value is considered to change.

  That is, when a positive voltage is applied to the second electrode connected to the second metal oxide with reference to the first electrode, oxygen ions in the resistance change layer are attracted to the second metal oxide side. As a result, an oxidation reaction occurs in a small local region formed in the second metal oxide, and the degree of oxygen deficiency is reduced. As a result, it is considered that the filaments in the local region are not easily connected and the resistance value is increased.

  Conversely, when a negative voltage is applied to the second electrode connected to the second metal oxide with reference to the first electrode, oxygen ions in the second metal oxide are pushed to the first metal oxide side. . As a result, a reduction reaction occurs in a minute local region formed in the second metal oxide, and the degree of oxygen deficiency increases. As a result, it is considered that the filaments in the local region are easily connected and the resistance value decreases.

  The second electrode connected to the second metal oxide having a lower oxygen deficiency includes, for example, a metal constituting the second metal oxide, such as platinum (Pt), iridium (Ir), palladium (Pd), and the like. The standard electrode potential is higher than that of the material forming one electrode. The first electrode connected to the first metal oxide having a higher degree of oxygen deficiency is, for example, tungsten (W), nickel (Ni), tantalum (Ta), titanium (Ti), aluminum (Al), The standard electrode potential may be made of a material having a lower standard electrode potential than the metal constituting the first metal oxide, such as tantalum nitride (TaN) or titanium nitride (TiN). The standard electrode potential represents a characteristic that the higher the value is, the more difficult it is to oxidize.

  That is, the standard electrode potential V2 of the second electrode, the standard electrode potential Vr2 of the metal constituting the second metal oxide, the standard electrode potential Vr1 of the metal constituting the first metal oxide, and the standard electrode potential V1 of the first electrode May satisfy the relationship of Vr2 <V2 and V1 <V2. Furthermore, V2> Vr2 and Vr1 ≧ V1 may be satisfied.

  With the above configuration, a redox reaction occurs selectively in the second metal oxide in the vicinity of the interface between the second electrode and the second metal oxide, and a stable resistance change phenomenon is obtained.

  The first electrode terminal 105 is drawn from the first electrode 100a, and the second electrode terminal 102 is drawn from the second electrode 100c. The NMOS transistor 104 that is a selection transistor (that is, an example of a switch element) includes a gate terminal 103. The first electrode terminal 105 of the variable resistance element 100 and the source or drain (N + diffusion) region of the NMOS transistor 104 are connected in series, and the other drain or source (N + diffusion) region not connected to the variable resistance element 100. Is drawn out as the first electrode terminal 101, and the substrate terminal is connected to the ground potential. Here, the high resistance second resistance change layer 100 b-2 is disposed on the second electrode terminal 102 side opposite to the NMOS transistor 104.

  In the memory cell shown in FIG. 2, a voltage (low resistance voltage pulse) equal to or higher than a predetermined voltage (for example, the first threshold voltage) is applied to the first electrode terminal 101 with the second electrode terminal 102 as a reference. In this case, reduction occurs near the interface between the second electrode 100c and the second resistance change layer 100b-2, and the resistance change element 100 transitions to a low resistance state. On the other hand, when a voltage (high resistance voltage pulse) equal to or higher than another predetermined voltage (for example, a second threshold voltage) is applied to the second electrode terminal 102 with respect to the first electrode terminal 101, the second electrode 100c Oxidation occurs near the interface with the second resistance change layer 100b-2, and the resistance change element 100 transitions to a high resistance state. Here, the application direction of the low resistance voltage pulse is defined as a negative voltage direction, and the application direction of the high resistance voltage pulse is defined as a positive voltage direction. That is, the resistance variable element 100 of this embodiment can be a bipolar resistance variable element. Note that the resistance variable element 100 may be a unipolar resistance variable element.

  The memory cell array 120 has a so-called 1T1R type memory cell in which a MOS transistor and a resistance variable element are connected in series at a position near the intersection of a bit line and a word line arranged orthogonal to each other. An array arrangement may be employed. In the 1T1R type, one end of the two-terminal variable resistance element can be connected to a bit line or a source line. The other end can be connected to the drain or source of the transistor. The gate of the transistor can be connected to a word line. The other end of the transistor can be connected to a source line or a bit line to which one end of the resistance variable element is not connected. The source line can be arranged in parallel with the bit line or the word line.

  The memory cell array 120 has a so-called 1D1R type cross-point memory cell in which a diode and a resistance variable element are connected in series at the intersection of a bit line and a word line arranged orthogonal to each other in a matrix. A configuration in which an array is arranged may be used.

  The pulse applying device 130 performs a verify write operation. The verify write operation is a state in which the resistance state is applied to the resistance variable element 100 that does not satisfy the determination condition for confirming that the resistance state has changed despite the application of the voltage pulse for changing the resistance state. This is an operation of applying an additional voltage pulse for changing. The application of the voltage pulse for changing the resistance state may be repeated until the determination condition is satisfied, for example, or may be stopped when some condition is satisfied.

  When the number of verify write operations performed on a predetermined number of variable resistance elements 100 to be written exceeds a predetermined number, the pulse applying device 130 waits for a predetermined time after the verify write operation.

[Write Method (Operation Method of Resistance Change Nonvolatile Memory Device)]
FIG. 3 is a flowchart illustrating an example of a writing method of the variable resistance nonvolatile memory device according to the first embodiment. The operation shown in FIG. 3 can be executed under the control of the pulse applying device 130.

  When data writing to the variable resistance nonvolatile memory device 140 is started (start), first, a voltage pulse is applied to the variable resistance element 100 to be written (step S101).

  Next, it is determined whether or not the resistance change element 100 to which the voltage pulse is applied satisfies the determination condition (step S102). Specifically, for example, the resistance value of the resistance variable element to which the voltage pulse is applied is read by the pulse applying device 130, and the magnitude relationship with a predetermined threshold is determined using a sense amplifier. If the determination result is YES, data writing to the variable resistance nonvolatile memory device 140 ends (END).

  If the decision result in the step S102 is NO, it is judged whether or not the number of verify write operations exceeds a predetermined number (step S103).

  The number of verify write operations may be, for example, the number of voltage pulses applied to the same resistance variable element after the start of data write, or may be the number of times determined as NO in step S103. The number of verify write operations may be, for example, the sum of voltage pulses applied after the start of data write to a plurality of resistance change elements to be written, or NO in the determination in step S103. The total number of times may be used, or an average value of the number of times of NO in the determination in step S103 per resistance change element.

  The number of verify write operations may be stored in, for example, a data latch included in the variable resistance nonvolatile memory device 140.

  If the decision result in the step S103 is NO, the process returns to the step S101 and the voltage pulse is applied again to the resistance variable element 100 to be written. At this time, 1 is added to the number of verify write operations.

  If the decision result in the step S103 is YES, it waits for a predetermined time without applying a pulse in a step S104.

  In addition, after waiting for predetermined time in step S104, it returns to step S101 and a voltage pulse may be applied again. Further, after waiting for a predetermined time in step S104, the process may return to step S102 to determine whether or not the determination condition is satisfied.

  By waiting for a predetermined time, the degradation of the resistance variable element is recovered, and transitions to a higher resistance in the case of high resistance writing and to a lower resistance in the case of low resistance writing. Accordingly, for example, when writing again in step S101 and in the subsequent writing operation, the probability of verify fail is reduced, and the writing speed is improved.

  The standby for a predetermined time may be performed for each resistance variable element or may be performed for each of the plurality of resistance variable elements (in units of writing blocks).

(Second Embodiment)
In the second embodiment, when writing is performed to change one resistance change element from a high resistance state to a low resistance state, a predetermined standby time is provided according to the number of verify write operations.

  The resistance change nonvolatile memory device write method according to the second embodiment is the resistance change nonvolatile memory device write method according to the first embodiment. The verify write operation is performed after the first voltage pulse is applied. The resistance value of the resistance variable element is read, and the first voltage is again applied as an additional voltage pulse to the resistance variable element determined that the read resistance value is higher than the first threshold resistance value. A pulse is applied. In the verify write operation, if the number of verify write operations performed so far on one resistance variable element to be written exceeds the first threshold number, an additional operation is performed. It waits for a predetermined time without applying a typical voltage pulse.

  The variable resistance nonvolatile memory device according to the second embodiment is the variable resistance nonvolatile memory device according to the first embodiment, in which the pulse applying device executes the above writing method.

  The additional voltage pulse may not be the same as the first voltage pulse, and may be another additional voltage pulse.

[Device configuration]
The configuration of the variable resistance nonvolatile memory device according to the second embodiment is the same as that of the variable resistance nonvolatile memory device according to the first embodiment, except for the operation of the pulse applying device (the operation method of the variable resistance nonvolatile memory device). It can be. Therefore, the same code | symbol and name are attached | subjected about the component which is common in 1st Embodiment and 2nd Embodiment, and detailed description is abbreviate | omitted.

[Write Method (Operation Method of Resistance Change Nonvolatile Memory Device)]
FIG. 4 is a flowchart illustrating an example of a writing method of the variable resistance nonvolatile memory device according to the second embodiment. The operation shown in FIG. 4 can be executed under the control of the pulse applying device 130.

  When data writing to the variable resistance nonvolatile memory device 140 is started (start), first, a first voltage pulse is applied to the variable resistance element 100 to be written (step S201). Next, it is determined whether or not the determination condition is satisfied for the resistance variable element 100 to which the voltage pulse is applied, that is, whether or not the resistance value of the resistance variable element 100 is larger than the first threshold resistance value. A determination is made (step S202). Specifically, for example, the resistance value of the resistance variable element 100 to which the voltage pulse is applied is read by the pulse applying device 130, and whether or not the resistance value is higher than the first threshold resistance value is determined by the sense amplifier. To be determined. If the determination result is NO, data writing to the variable resistance nonvolatile memory device 140 ends (end).

  If the decision result in the step S202 is YES, it is judged whether or not the number of verify write operations exceeds the first threshold number (step S203). The first threshold number may be 1 or a predetermined natural number of 2 or more.

  The number of verify write operations may be, for example, the number of voltage pulses applied to the same resistance variable element after the start of data write, or may be the number of times determined as YES in step S202. The number of verify write operations may be stored in, for example, a data latch included in the variable resistance nonvolatile memory device 140.

  If the decision result in the step S203 is NO, the process returns to the step S201.

  If the decision result in the step S203 is YES, the process waits for a predetermined time without applying a pulse in a step S204.

  In addition, after waiting for predetermined time in step S204, it returns to step S201 and the 1st voltage pulse may be applied again. In addition, after waiting for a predetermined time in step S204, the process may return to step S202 to determine whether or not the determination condition is satisfied.

  Note that the first voltage pulse applied in step S201 may be a single pulse or a plurality of pulses.

  In such an operation method, when the number of verify write operations exceeds the first threshold number of times, the resistance variable element is deteriorated by waiting for a predetermined time, and the resistance value of the resistance variable element becomes lower. Accordingly, for example, when writing again in step S201 and in the subsequent writing operation, the probability of verify fail is reduced, and the writing speed is improved.

  In the above description, the number of verify write operations may or may not be reset to 0 after step S204. Since the deterioration of the resistance variable element is recovered by waiting for a predetermined time, the number of verifications is reset to 0, and it is not necessary to provide a waiting time for subsequent writing. If the number of verify write operations exceeds the first threshold number, it means that the resistance variable element is being deteriorated. In some cases, it is effective to always provide a standby time in subsequent writing without resetting the number of verify writing operations.

  Also in the second embodiment, the same modifications as in the first embodiment are possible.

(Third embodiment)
In the third embodiment, when writing is performed to change one resistance variable element from a low resistance state to a high resistance state, a predetermined standby time is provided according to the number of verify write operations.

  The resistance change nonvolatile memory device write method according to the third embodiment is the resistance change nonvolatile memory device write method according to the first embodiment, and the verify write operation is performed after the second voltage pulse is applied. The resistance value of the variable resistance element is read, and the second voltage is again applied as an additional voltage pulse to the variable resistance element determined that the read resistance value is lower than the second threshold resistance value. A pulse is applied. In the verify write operation, if the number of verify write operations performed so far on one resistance variable element to be written exceeds the second threshold number, an additional operation is performed. It waits for a predetermined time without applying a typical voltage pulse.

  The variable resistance nonvolatile memory device according to the third embodiment is the variable resistance nonvolatile memory device according to the first embodiment, and the pulse applying device executes the above writing method.

  The additional voltage pulse may not be the same as the second voltage pulse, and may be another additional voltage pulse.

[Device configuration]
The configuration of the variable resistance nonvolatile memory device of the third embodiment is the same as that of the variable resistance nonvolatile memory device of the first embodiment, except for the operation of the pulse applying device (the operation method of the variable resistance nonvolatile memory device). It can be. Therefore, the same code | symbol and name are attached | subjected about the component which is common in 1st Embodiment and 3rd Embodiment, and detailed description is abbreviate | omitted.

[Write Method (Operation Method of Resistance Change Nonvolatile Memory Device)]
FIG. 5 is a flowchart illustrating an example of a writing method of the variable resistance nonvolatile memory device according to the third embodiment. The operation shown in FIG. 5 can be executed under the control of the pulse applying device 130.

  When data writing to the variable resistance nonvolatile memory device 140 is started (start), first, a second voltage pulse is applied to the variable resistance element 100 to be written (step S301). Next, it is determined whether or not the determination condition is satisfied for the resistance variable element 100 to which the voltage pulse is applied, that is, whether or not the resistance value of the resistance variable element 100 is smaller than the second threshold resistance value. A determination is made (step S302). Specifically, for example, the resistance value of the resistance variable element 100 to which the voltage pulse is applied is read out by the pulse applying device 130, and the sense amplifier determines whether the resistance value is lower than the second threshold resistance value. To be determined. If the determination result is NO, data writing to the variable resistance nonvolatile memory device 140 ends (end).

  If the decision result in the step S302 is YES, it is judged whether or not the number of verify write operations exceeds the second threshold number (step S303). The second threshold number may be 1 or a predetermined natural number of 2 or more.

  The number of verify write operations may be, for example, the number of voltage pulses applied to the same resistance variable element after the start of data write, or may be the number of times determined as YES in step S302. The number of verify write operations may be stored in, for example, a data latch included in the variable resistance nonvolatile memory device 140.

  If the determination result of step S303 is NO, the process returns to step S301.

  If the decision result in the step S303 is YES, in a step S304, it is on standby without applying a pulse for a predetermined time.

  In addition, after waiting for predetermined time in step S304, it returns to step S301 and may apply a 1st voltage pulse again. Further, after waiting for a predetermined time in step S304, the process may return to step S302 to determine whether or not the determination condition is satisfied.

  Note that the second voltage pulse applied in step S301 may be a single pulse or a plurality of pulses.

  In such an operation method, when the number of verify write operations exceeds the second threshold number of times, by waiting for a predetermined time, the deterioration of the resistance variable element is recovered, and the resistance value of the resistance variable element becomes higher. Accordingly, for example, when writing again in step S301 and in the subsequent writing operation, the probability of verify fail is reduced, and the writing speed is improved.

  In the above description, the number of verify write operations may or may not be reset to 0 after step S304. Since the deterioration of the resistance variable element is recovered by waiting for a predetermined time, the number of verifications is reset to 0, and it is not necessary to provide a waiting time for subsequent writing. If the number of verify write operations exceeds the second threshold number, it means that the resistance variable element is being deteriorated. In some cases, it is effective to always provide a standby time in subsequent writing without resetting the number of verify writing operations.

  Also in the third embodiment, the same modifications as in the first embodiment are possible.

  The third embodiment and the second embodiment may be combined. In this case, the first threshold number and the second threshold number may or may not be equal.

(Fourth embodiment)
In the fourth embodiment, when writing is performed to change a plurality of resistance change elements from a high resistance state to a low resistance state, a predetermined standby time is provided according to the average number of verify write operations.

  The write method of the variable resistance nonvolatile memory device according to the fourth embodiment is the write method of the variable resistance nonvolatile memory device according to the first embodiment. The verify write operation is performed after the first voltage pulse is applied. The resistance value of the resistance variable element is read, and the first voltage is again applied as an additional voltage pulse to the resistance variable element determined that the read resistance value is higher than the first threshold resistance value. A pulse is applied, and in the verify write operation, the average number of verify write operations performed so far on all or a part of the plurality of resistance change elements to be written is the first threshold value. When the number of times is exceeded, an additional voltage pulse is not applied and the apparatus waits for a predetermined time.

  The variable resistance nonvolatile memory device according to the fourth embodiment is the variable resistance nonvolatile memory device according to the first embodiment, in which the pulse applying device executes the above writing method.

  The additional voltage pulse may not be the same as the first voltage pulse, and may be another additional voltage pulse.

[Device configuration]
The configuration of the variable resistance nonvolatile memory device according to the fourth embodiment is the same as that of the variable resistance nonvolatile memory device according to the first embodiment, except for the operation of the pulse applying device (the operation method of the variable resistance nonvolatile memory device). It can be. Therefore, the same code | symbol and name are attached | subjected about the component which is common in 1st Embodiment and 4th Embodiment, and detailed description is abbreviate | omitted.

[Write Method (Operation Method of Resistance Change Nonvolatile Memory Device)]
FIG. 6 is a flowchart illustrating an example of a writing method of the variable resistance nonvolatile memory device according to the fourth embodiment. The operation shown in FIG. 6 can be executed under the control of the pulse applying device 130.

  When data writing to the variable resistance nonvolatile memory device 140 is started (start), first, a first voltage pulse is applied to the variable resistance element 100 to be written (step S401). Next, it is determined whether or not the determination condition is satisfied for the resistance variable element 100 to which the voltage pulse is applied, that is, whether or not the resistance value of the resistance variable element 100 is larger than the first threshold resistance value. A determination is made (step S402). Specifically, for example, the resistance value of the resistance variable element 100 to which the voltage pulse is applied is read by the pulse applying device 130, and whether or not the resistance value is higher than the first threshold resistance value is determined by the sense amplifier. To be determined. If the determination result is NO, it is determined whether or not writing to all the elements to be reduced in resistance (LR) is completed (step 405). If the determination result is NO, the process proceeds to step 401 for the next LR conversion target element. If the determination result is YES, data writing to the variable resistance nonvolatile memory device 140 ends (END).

  If the decision result in the step S402 is YES, it is judged whether or not the average number of verify write operations exceeds the first threshold number (step S403). The first threshold number of times can be set to 0.1, for example.

  The average number of verify write operations may be, for example, the sum of the voltage pulses applied after the start of data write divided by the number of resistance change elements that have been written, or YES in step S402. The total number of times obtained may be divided by the number of resistance variable elements that have been written. For example, the total number of voltage pulses applied after the start of data writing, the total number of times YES is determined in step S402, the number of resistance change elements that have been written, and the like are stored in the resistance change nonvolatile memory. You may memorize | store in the data latch with which the apparatus 140 is provided.

  If the determination result of step S403 is NO, the process returns to step S401.

  If the decision result in the step S403 is YES, in a step S404, a standby is performed without applying a pulse for a predetermined time, and it is decided whether or not writing to all the elements to be reduced in resistance (LR) is completed. Is performed (step 405). Since the processing after step 405 is as described above, a description thereof will be omitted.

  In addition, after waiting for predetermined time in step S404, it returns to step S401 and the 1st voltage pulse may be applied again. Further, after waiting for a predetermined time in step S404, the process may return to step S402 to determine whether or not the determination condition is satisfied.

  Note that the first voltage pulse applied in step S401 may be a single pulse or a plurality of pulses.

  In such an operation method, when the number of verify write operations exceeds the first threshold number of times, the resistance variable element is deteriorated by waiting for a predetermined time, and the resistance value of the resistance variable element becomes lower. Accordingly, for example, when writing again in step S401 and in the subsequent writing operation, the probability of verify fail is reduced, and the writing speed is improved.

  In the above description, the number of verifications may or may not be reset to 0 after step S404. Since the deterioration of the resistance variable element is recovered by waiting for a predetermined time, the number of verifications is reset to 0, and it is not necessary to provide a waiting time for subsequent writing. When the average number of verify write operations exceeds the first threshold number, it means that the resistance variable element is being deteriorated. In some cases, it is effective to always provide a standby time in subsequent writing without resetting the number of verify writing operations.

  Also in the fourth embodiment, the same modifications as in the first embodiment are possible.

  The fourth embodiment may be combined with one or both of the second embodiment and the third embodiment.

(Fifth embodiment)
In the fifth embodiment, when writing is performed to change a plurality of resistance change elements from a low resistance state to a high resistance state, a predetermined standby time is provided according to the average number of verify write operations.

  The resistance change nonvolatile memory device write method according to the fifth embodiment is the resistance change nonvolatile memory device write method according to the first embodiment, and the verify write operation is performed after the second voltage pulse is applied. The resistance value of the variable resistance element is read, and the second voltage is again applied as an additional voltage pulse to the variable resistance element determined that the read resistance value is lower than the second threshold resistance value. A pulse is applied, and in the verify write operation, the average number of verify write operations performed so far on all or a part of the plurality of resistance change elements to be written is the second threshold value. When the number of times is exceeded, an additional voltage pulse is not applied and the apparatus waits for a predetermined time.

  The variable resistance nonvolatile memory device according to the fifth embodiment is the variable resistance nonvolatile memory device according to the first embodiment, and the pulse applying device executes the above writing method.

  The additional voltage pulse may not be the same as the second voltage pulse, and may be another additional voltage pulse.

[Device configuration]
The configuration of the variable resistance nonvolatile memory device according to the fifth embodiment is the same as that of the variable resistance nonvolatile memory device according to the first embodiment, except for the operation of the pulse applying device (the operation method of the variable resistance nonvolatile memory device). It can be. Therefore, the same code | symbol and name are attached | subjected about the component which is common in 1st Embodiment and 5th Embodiment, and detailed description is abbreviate | omitted.

[Write Method (Operation Method of Resistance Change Nonvolatile Memory Device)]
FIG. 7 is a flowchart illustrating an example of a writing method of the variable resistance nonvolatile memory device according to the fifth embodiment. The operation shown in FIG. 7 can be executed under the control of the pulse applying device 130.

  When data writing to the variable resistance nonvolatile memory device 140 is started (start), first, a second voltage pulse is applied to the variable resistance element 100 to be written (step S501). Next, it is determined whether or not the determination condition is satisfied for the resistance variable element 100 to which the voltage pulse is applied, that is, whether or not the resistance value of the resistance variable element 100 is smaller than the second threshold resistance value. A determination is made (step S502). Specifically, for example, the resistance value of the resistance variable element 100 to which the voltage pulse is applied is read out by the pulse applying device 130, and the sense amplifier determines whether the resistance value is lower than the second threshold resistance value. To be determined. If the determination result is NO, it is determined whether or not writing to all the elements to be increased in resistance (HR) has been completed (step 505). If the determination result is NO, the process proceeds to step 501 for the next element to be HR processed. If the determination result is YES, data writing to the variable resistance nonvolatile memory device 140 ends (END).

  If the decision result in the step S502 is YES, it is judged whether or not the average number of verify write operations exceeds the second threshold number (step S503). The second threshold number of times can be set to 0.1, for example.

  The average number of verify write operations may be, for example, the number of voltage pulses applied after the start of data write divided by the number of resistance change elements that have been written, or YES in step S502. The total number of times obtained may be divided by the number of resistance variable elements that have been written. For example, the total number of voltage pulses applied after the start of data writing, the total number of times YES is determined in step S502, and the number of resistance change elements that have been written, are stored in the resistance change nonvolatile memory. You may memorize | store in the data latch with which the apparatus 140 is provided.

  If the decision result in the step S503 is NO, the process returns to the step S501.

  If the decision result in the step S503 is YES, in a step S504, a stand-by is performed without applying a pulse for a predetermined time, and it is decided whether or not writing to all the elements to be increased in resistance (HR) is completed. Is performed (step 505). Since the processing after step 505 is as described above, the description thereof is omitted.

  In addition, after waiting for predetermined time in step S504, it returns to step S501 and a 2nd voltage pulse may be applied again. Further, after waiting for a predetermined time in step S504, the process may return to step S502 to determine whether or not the determination condition is satisfied.

  Note that the second voltage pulse applied in step S501 may be a single pulse or a plurality of pulses.

  In such an operation method, when the number of verify write operations exceeds the first threshold number, the resistance change element is recovered from deterioration by waiting for a predetermined time, and the resistance value of the resistance change element becomes higher. Accordingly, for example, when writing again in step S501 and in the subsequent writing operation, the probability of verify fail is reduced, and the writing speed is improved.

  In the above description, the number of verifications may or may not be reset to 0 after step S504. Since the deterioration of the resistance variable element is recovered by waiting for a predetermined time, the number of verifications is reset to 0, and it is not necessary to provide a waiting time for subsequent writing. When the average number of verify write operations exceeds the first threshold number, it means that the resistance variable element is being deteriorated. In some cases, it is effective to always provide a standby time in subsequent writing without resetting the number of verify writing operations.

  Also in the fifth embodiment, the same modification as in the first embodiment is possible.

  The fifth embodiment may be arbitrarily combined with the second to fourth embodiments.

(Examination example)
FIG. 8 is a block diagram illustrating a schematic configuration of a variable resistance nonvolatile memory device according to a study example.

(1) Device Configuration As shown in FIG. 8, the variable resistance nonvolatile memory device 200 according to the study example includes a memory main body 201 on a semiconductor substrate, and the memory main body 201 is the same as FIG. 2. The memory cell array 202 composed of 1T1R type memory cells having the configuration described above, the row selection circuit 208, the row driver 207 including the word line driver WLD and the source line driver SLD, the column selection circuit 203, and data writing are performed. For detecting the amount of current flowing through the selected bit line, determining the high resistance state as data “0”, and determining the low resistance state as data “1”, and a terminal DQ A data input / output circuit 205 that performs input / output processing of input / output data, and a write power supply 211.

  As will be described later, the sense amplifier 204 includes a read reference current generation circuit 702, an LR conversion reference current generation circuit 703, and an HR conversion reference current generation circuit 704.

  The variable resistance nonvolatile memory device 200 further includes an address input circuit 209 that receives an address signal input from the outside, and a control circuit 210 that controls the operation of the memory body 201 based on the control signal input from the outside. And.

  The memory cell array 202 includes a plurality of word lines WL0, WL1, WL2, WL3,... And a plurality of bit lines BL0, BL1, BL2,.・ With. A plurality of NMOS transistors N11, N12, N13, N14 provided corresponding to the intersections of these word lines WL0, WL1, WL2, WL3,... And bit lines BL0, BL1, BL2,. ..., N21, N22, N23, N24, ..., N31, N32, N33, N34, ... (hereinafter referred to as "transistors N11, N12, ...") and transistors N11, N12, A plurality of variable resistance elements R11, R12, R13, R14,..., R21, R22, R23, R24,..., R31, R32, R33, R34,. (Hereinafter referred to as “resistance variable elements R11, R12,...”). A structure in which individual NMOS transistors and individual resistance change elements, which are provided corresponding to the intersections of the plurality of bit lines and the plurality of word lines, are connected in series to the memory cells M11, M12, M13, M14, ..., M21, M22, M23, M24, ... M31, M32, M33, M34, ... (hereinafter referred to as "memory cells M11, M12, ..."). .

  As shown in FIG. 8, the gates of the transistors N11, N21, N31,... Are connected to the word line WL0, and the gates of the transistors N12, N22, N32,. Further, the gates of the transistors N13, N23, N33,... Are connected to the word line WL2, and the gates of the transistors N14, N24, N34,.

  The transistors N11, N21, N31,... And the transistors N12, N22, N32,... Are connected in common to the source line SL0, and the transistors N13, N23, N33, ... and the transistors N14, N24, N34,. .. Are commonly connected to the source line SL2. That is, the source lines SL0, SL2,... Are parallel to the word lines WL0, WL1, WL2, WL3,... And intersect the bit lines BL0, BL1, BL2,. In the form, they are arranged in a vertical direction).

  In the above configuration example, the source line is arranged parallel to the word line, but may be arranged parallel to the bit line. The source line is configured to apply a common potential to the transistors connected as plate lines. However, the source line includes a source line selection circuit having a configuration similar to that of the row selection circuit 208, and the selected source line is not selected. The source line may be driven with a different voltage (including polarity).

  The resistance change elements R11, R12, R13, R14,... Are connected to the bit line BL0, and the resistance change elements R21, R22, R23, R24,. Further, the resistance variable elements R31, R32, R33, R34,... Are connected to the bit line BL2. As described above, in the memory cell array 202 in the embodiment, the resistance variable elements R11, R21, R31,... Do not pass through the NMOS transistors N11, N21, N31. The structure directly connected to is adopted.

  In the data write cycle, the control circuit 210 outputs a write signal instructing application of a write voltage to the write circuit 206 according to the input data Din input to the data input / output circuit 205. On the other hand, in the data read cycle, the control circuit 210 outputs a read signal instructing a read operation to the sense amplifier 204.

  The row selection circuit 208 receives the row address signal output from the address input circuit 209, and in response to the row address signal, a plurality of word lines WL0, WL1, WL2, WL3,. Is selected. Then, a predetermined voltage is applied to the selected word line from the word line driver circuit WLD corresponding to the selected word line.

  Similarly, the row selection circuit 208 receives the row address signal output from the address input circuit 209, and selects one of the plurality of source lines SL0, SL2,... According to the row address signal. . Then, a predetermined voltage is applied to the selected source line from the source line driver circuit SLD corresponding to the selected source line.

  When the write circuit 206 receives a write signal (not shown) output from the control circuit 210, the write circuit 206 applies a write voltage to the bit line selected by the column selection circuit 203.

  The write power supply 211 supplies the word line voltage Vw and the source line voltage Vs to the row driver 207, and supplies the bit line voltage Vb to the write circuit 206.

  FIG. 9 is a circuit diagram illustrating an example of a schematic configuration of a sense amplifier included in the variable resistance nonvolatile memory device according to the study example.

  For example, the sense amplifier 204 includes a current mirror circuit 218 having a mirror ratio of 1: 1, clamp transistors 219 and 220 having the same size, a reference circuit 221, and a differential amplifier 224. The reference circuit 221 includes a read reference current generation circuit 702, an LR conversion reference current generation circuit 703, and an HR conversion reference current generation circuit 704.

  In the read reference current generating circuit 702, one end of the branch (the drain terminal of the select transistor 222) in which the selection transistor 222 and the read reference resistor Rref are connected in series is connected to the ground potential, and the other terminal is the clamp transistor 219. Connected to the source terminal. A read enable signal C <b> 1 is input to the gate terminal of the selection transistor 222. The selection transistor 222 is switched between a conductive / non-conductive state by the read enable signal C1. Note that the source terminal and the drain terminal may be interchanged (the same applies hereinafter).

  Similarly, in the LR reference current generation circuit 703, one end of the branch in which the selection transistor 223 and the LR verification reference resistor RL (RL <Rref) are connected in series (the drain terminal of the selection transistor 223) is set to the ground potential. The other terminal is connected to the source terminal of the clamp transistor 219. The LR verify enable signal C2 is input to the gate terminal of the selection transistor 223. The select transistor 223 is switched between a conductive / non-conductive state by the LR verify enable signal C2.

  Similarly, in the HR reference current generation circuit 704, one end of the branch in which the selection transistor 227 and the HR verification reference resistor RH (RH> Rref) are connected in series (the drain terminal of the selection transistor 227) is set to the ground potential. The other terminal is connected to the source terminal of the clamp transistor 219. The HR verify enable signal C3 is input to the gate terminal of the selection transistor 227. The select transistor 227 is switched between a conductive / non-conductive state by the HR verify enable signal C3.

  The clamp transistors VC219 (VCLP <VDD) are input to the gate terminals of the clamp transistors 219 and 220. The source terminal of the clamp transistor 220 is connected to the memory cell via the column selection circuit 203 and the bit line. The drain terminals of the clamp transistors (here, N-type MOS transistors) 219 and 220 are connected to the drain terminals of transistors (here, P-type MOS transistors) 225 and 226 constituting the current mirror circuit 218, respectively. The drain terminal potential of the clamp transistor 220 is compared with the reference voltage VREF (1.1V as an example) by the differential amplifier 224 to determine whether it is higher or lower than the reference voltage VREF. The determination result is transmitted to the data input / output circuit 205 as the sense amplifier output SAO.

  FIG. 10 is a schematic diagram showing the determination level of the sense amplifier in the writing method of the variable resistance nonvolatile memory device according to the study example, and the resistance value (vertical axis) when writing is performed on a certain memory cell region. And the number of bits (horizontal axis).

  As shown in FIG. 10, the sense amplifier 204 has a determination level of the read reference resistance Rref between the resistance value of the memory cell in the HR state and the resistance value of the memory cell in the LR state. Further, the sense amplifier 204 has determination levels of an LR verification reference resistance RL (RL <Rref) smaller than the read reference resistance Rref and an HR verification reference resistance RH (Rref <RH) larger than the read reference resistance Rref. .

  The LR verification reference resistor RL is used to determine whether or not LR writing of the resistance variable element is completed. The HR verification reference resistor RH is used to determine whether or not the HR writing of the resistance variable element is completed. The read reference resistor Rref is used to determine whether the resistance variable element is in a high resistance state or a low resistance state.

(2) Operation In the variable resistance nonvolatile memory device configured as described above, the operation of main circuit blocks will be described below, and then the read operation and the write operation of the variable resistance nonvolatile memory device will be described. To do.

  First, the operation of the sense amplifier 204 shown in FIG. 9 will be described. In the LR writing process for reducing the resistance variable element to LR (reducing resistance), the sense amplifier 204 is connected to the column selection circuit 203 and the bit line after the low resistance voltage pulse set 14 is applied from the writing circuit 206. , Connected to the target memory cell. At this time, a voltage higher than the voltage (VCLP−Vth), which is lower than the clamp voltage VCLP by the threshold voltage (Vth) of the clamp transistors 219 and 220, is not applied to the memory cell.

  On the other hand, in the reference circuit 221, the selection transistor 223 is activated by the LR verification enable signal C2, and becomes conductive. The LR verification reference resistor RL is selected, and the other selection transistors 222 and 227 are deactivated by the read enable signal C1 and the HR verification enable signal C3, and are made non-conductive. Thereby, a reference current Iref (≈ (VCLP−Vth) / RL) flows.

  Accordingly, the reference current Iref is transferred by the current mirror circuit 218, and the current substantially the same as Iref flows as the load current IL (IL = Iref). The clamp transistor 220 compares the magnitude relationship between the load current IL and the memory cell current Ic. Depending on the comparison result, the differential amplifier 224 detects whether the drain terminal voltage of the clamp transistor 220 is higher or lower than the reference voltage VREF (1.1 V as an example). The differential amplifier 224 outputs a sense amplifier output SAO based on the detection result.

  Here, the memory cell current Ic (= (VCLP−Vth) / RLt) flows when the resistance value of the resistance variable element after application of the low resistance voltage pulse set 14 (see FIG. 11B) is RLt. . At this time, if load current IL> memory cell current Ic, the drain terminal voltage of clamp transistor 220 becomes higher than reference voltage VREF after a predetermined time, and sense amplifier output SAO outputs L level. That is, when the selected memory cell is in a resistance state higher than the LR verification reference resistance RL, the sense amplifier 204 outputs “0”. This is determined as failure (verify fail).

  On the other hand, if load current IL <memory cell current Ic, the drain terminal voltage of clamp transistor 220 becomes lower than reference voltage VREF after a predetermined time, and sense amplifier output SAO outputs H level. That is, when the selected memory cell is in a resistance state lower than the LR verification reference resistance RL, the sense amplifier 204 outputs “1”. This is a pass determination, which indicates that the writing to the low resistance state of the target memory cell has been completed.

  Similarly, in the HR write process for HR (high resistance) of the variable resistance element, after the high resistance voltage pulse set 13 is applied from the write circuit 206, the sense amplifier 204 is connected to the column selection circuit 203 and the bit line. To the target memory cell. At this time, a voltage higher than the voltage (VCLP−Vth), which is lower than the clamp voltage VCLP by the threshold voltage (Vth) of the clamp transistors 219 and 220, is not applied to the memory cell.

  On the other hand, in the reference circuit 221, the selection transistor 227 is activated by the HR verify enable signal C3 and becomes conductive. The HR verify reference resistor RH is selected, and the other select transistors 222 and 223 are deactivated by the read enable signal C1 and the LR verify enable signal C2, and are made non-conductive. Thereby, a reference current Iref (≈ (VCLP−Vth) / RH) flows.

  Accordingly, the reference current Iref is transferred by the current mirror circuit 218, and almost the same current as Iref flows as the load current IL (IL = Iref). The magnitude relationship between the load current IL and the memory cell current Ic is determined by the clamp transistor 220. To be compared.

  Here, when the resistance value of the resistance variable element after application of the high-resistance voltage pulse set 13 (see FIG. 11A) is RHt, the memory cell current Ic (= (VCLP−Vth) / RHt) flows. . At this time, if load current IL <memory cell current Ic, the drain terminal voltage of clamp transistor 220 becomes lower than reference voltage VREF after a predetermined time, and sense amplifier output SAO outputs H level. That is, when the selected memory cell is in a resistance state lower than the HR verification reference resistance RH, the sense amplifier 204 outputs “1”. This is determined as failure (verify fail).

  On the other hand, if load current IL> memory cell current Ic, the drain terminal voltage of clamp transistor 220 becomes higher than reference voltage VREF after a predetermined time, and sense amplifier output SAO outputs L level. That is, when the selected memory cell is in a resistance state higher than the HR verification reference resistance RH, the sense amplifier 204 outputs “0”. This is determined as a pass determination, and indicates that writing to the high resistance state of the target memory cell is completed.

  At the time of reading, in the reference circuit 221, the selection transistor 222 is activated by the read enable signal C1 and becomes conductive. The read reference resistor Rref is selected, and the other select transistors 223 and 227 are deactivated by the LR verify enable signal C2 and the HR verify enable signal C3, and are made non-conductive. Thereby, the reference current Iref (= (VCLP−Vth) / Rref) flows.

  Accordingly, the reference current Iref is transferred by the current mirror circuit 218, and the current substantially the same as Iref flows as the load current IL (IL = Iref). The clamp transistor 220 compares the magnitude relationship between the load current IL and the memory cell current Ic. Depending on the comparison result, whether the drain terminal voltage of the clamp transistor 220 is higher or lower than the reference voltage VREF is detected and detected by the differential amplifier 224. The differential amplifier 224 outputs a sense amplifier output SAO based on the detection result.

  Here, the resistance value of the memory cell in the high resistance state is Rhr, and the resistance value of the memory cell in the low resistance state is Rlr (Rhr> Rref> Rlr). When the selected memory cell is in a high resistance state, a memory cell current Ic (= (VCLP−Vth) / Rhr) flows. At this time, the load current IL> the memory cell current Ic, the drain terminal voltage of the clamp transistor 220 becomes higher than the reference voltage VREF, and the sense amplifier output SAO outputs L level. That is, when the selected memory cell is in a high resistance state (Rhr) higher than the read reference resistance Rref, the sense amplifier 204 determines “0” data.

  On the other hand, when the selected memory cell is in the low resistance state, a memory cell current Ic (= (VCLP−Vth) / Rlr) flows. At this time, the load current IL <the memory cell current Ic, the drain terminal voltage of the clamp transistor 220 becomes lower than the reference voltage VREF, and the sense amplifier output SAO outputs the H level. That is, when the selected memory cell is in a low resistance state (Rlr) lower than the read reference resistance Rref, the sense amplifier 204 determines that the data is “1”.

  FIG. 11A is a schematic flowchart for explaining a verify write operation at the time of increasing the resistance of the variable resistance nonvolatile memory device according to the study example.

  In the 1T1R type memory cell shown in FIG. 2, the high-resistance voltage pulse set 13 is applied (S601), and then whether or not the cell current of the write target cell is lower than a predetermined HR cell current level, that is, It is determined whether or not HR writing has been completed (HR verification: S602).

  Here, if the determination of HR verification S602 fails, the high resistance voltage pulse set 13 is applied again to the write target cell (S601), and the determination of HR verification S602 is performed. This operation is subsequently repeated until a pass is determined in the determination of HR verification S602 (S602).

  Here, if the determination of HR verification (S602) is NO (verification fail), the high-resistance voltage pulse set 13 is again applied to the write target cell (S601), and the determination of HR verification is performed (S602). ). This operation is thereafter repeated until YES is determined in the HR verification determination (S602).

  As an example, the high-resistance voltage pulse set 13 includes a negative pre-voltage pulse 15 (pre-voltage Vph = −1.0 V, pulse width 50 ns) and a positive high-resistance voltage pulse 16 (HR voltage). VH, pulse width 50 ns). In the negative pre-voltage pulse 15, the gate voltage VG = 2.8V is applied to the gate terminal 103 of the memory cell shown in FIG. 2, the voltage of + 1.0V is applied to the first electrode terminal 101, and the second electrode terminal A ground potential is applied to 102. In the positive high-resistance voltage pulse 16, the gate voltage VG = 2.8 V is applied to the gate terminal 103, and the HR voltage VH (for example, +1.8 V to +2.8 V) is applied to the second electrode terminal 102. And a ground potential is applied to the first electrode terminal 101.

  FIG. 11B is a schematic flowchart for explaining a verify write operation when the resistance of the variable resistance nonvolatile memory device according to the study example is lowered.

  In the 1T1R type memory cell shown in FIG. 2, the low resistance voltage pulse set 14 is applied (S603), and then whether or not the cell current of the write target cell is higher than a predetermined LR cell current level, that is, It is determined whether the LR writing has been completed (LR verification is Pass) (LR verification S604).

  Here, if the determination of LR verification S604 is NO (verify fail), the low resistance voltage pulse set 14 is applied to the write target cell again (S603), and the determination of LR verification is performed (S604). Thereafter, this operation is repeated until the determination in LR verification S604 is YES.

  As an example, the low-resistance voltage pulse set 14 includes a positive pre-voltage pulse 17 (pre-voltage Vpl = + 1.1 V, pulse width 50 ns) and a negative low-resistance voltage pulse 18 (LR voltage VL). = -2.8 V, pulse width 50 ns). In the positive pre-voltage pulse 17, a gate voltage VG = 2.8V is applied to the gate terminal 103 of the memory cell shown in FIG. 2, a voltage of + 1.1V is applied to the second electrode terminal 102, and the first electrode terminal A ground potential is applied to 101. In the negative voltage reduction voltage pulse 18, a gate voltage VG = 2.8 V is applied to the gate terminal 103, a voltage of +2.8 V is applied to the first electrode terminal 101, and a ground potential is applied to the second electrode terminal 102. Is applied.

  FIG. 12 is a table showing set voltages for each operation in the write method of the variable resistance nonvolatile memory device according to the study example. Hereinafter, referring to FIG. 12, a voltage pulse applied to the memory cell during low resistance write, high resistance write, and read operation, and a word line (WL) for applying the voltage pulse to the memory cell. A voltage applied to the source line (SL) and the bit line (BL) will be described.

  A voltage applied to the word line (WL), the source line (SL), and the bit line (BL) is generated by the write power supply 211. The word line voltage Vw is applied to the word line from the word line driver circuit WLD, the source line voltage Vs is applied to the source line from the source line driver circuit SLD, and the bit line voltage Vb is applied to the write circuit 206 and the column. It is applied to the bit line via the selection circuit 203.

  In FIG. 12, in the LR write operation, a negative pulse (same as the low resistance voltage pulse 18) is applied following application of a positive pulse (positive voltage pulse 17 in FIG. 11B). The bit line voltage when the positive pre-voltage pulse 17 is applied is a voltage pulse having an amplitude of 1.1V. The bit line voltage when the low resistance voltage pulse 18 is applied is a voltage pulse having an amplitude of 2.8V.

  In FIG. 12, in the HR write operation, a positive pulse (same as the high-resistance voltage pulse 16) is applied following application of a negative pulse (negative voltage pre-voltage pulse 15 in FIG. 11A). The bit line voltage when the negative pre-voltage pulse 15 is applied is a voltage pulse having an amplitude of 1.0V. The bit line voltage when the high resistance voltage pulse 16 is applied is a voltage pulse having an amplitude of 2.2V.

  The bit line BL voltage Vread at the time of reading, at the time of verifying read by LR writing, and at the time of verify reading by HR writing is adjusted so that no reading disturb occurs (that is, the resistance state of the resistance variable element does not change). The voltage value. VDD is a power supply voltage supplied to the variable resistance nonvolatile memory device 200.

  An example of a data write / read cycle of the variable resistance nonvolatile memory device configured as described above will be described with reference to FIGS. 13A to 13C and FIG.

  13A, 13B, and 13C are timing charts showing a low resistance operation, a high resistance operation, and a read operation, respectively, in the variable resistance nonvolatile memory device according to the study example. In the following description, data is written to and read from one memory cell (for example, memory cell M11).

  FIG. 13A shows a timing chart of application of the low resistance voltage pulse set 14 in the LR writing to the memory cell M11. In applying the low resistance voltage pulse set 14, a positive pre-voltage pulse 17 and a low resistance voltage pulse 18 are applied to the memory cell M11.

  In the positive voltage pre-voltage pulse 17 application cycle, first, the selected bit line BL0 and the source line SL0 are each set to a voltage of 0V. Next, the word line WL0 to be selected is set to the voltage Vw (2.8V), and the NMOS transistor N11 of the selected memory cell M11 in FIG. 8 is turned on.

  Next, the selected bit line BL0 is set to the voltage Vb (1.1V) for the time thw, and then a pulse waveform that becomes the voltage 0V is applied again. At this stage, a positive voltage pulse of the weak HR voltage VHw (+1.1 V) is applied to the memory cell M11 in FIG. 8, but the resistance value hardly changes.

  In the subsequent application cycle of the low-resistance voltage pulse 18, the selected bit line BL0 and the source line SL0 are first set to a voltage of 0V, respectively. Next, the selected bit line BL0 and the source line SL0 are set to the voltage Vs (2.8V) and the voltage Vb (2.8V), respectively. Next, the word line WL0 to be selected is set to the voltage Vw (2.8V). At this time, the NMOS transistor N11 of the selected memory cell M11 in FIG. 8 is still in the off state. At this stage, the drain terminal and the source terminal of the NMOS transistor N11 in FIG. 8 are at the same potential, and no current flows regardless of whether the transistor is on or off.

  Next, the selected bit line BL0 is set to a voltage of 0 V for a time tlw, and then a pulse waveform having a voltage Vb (2.8 V) is applied again. At this stage, a negative voltage pulse of the LR voltage VLw (−2.8 V) is applied to the memory cell M11 in FIG. 8, and the resistance value of the memory cell M11 transitions from a high resistance value to a low resistance value. Thereafter, the word line WL0 is set to a voltage of 0 V, and the application of the low resistance voltage pulse is completed. However, it is not necessarily limited to this method.

  FIG. 13B shows a timing chart of application of the high-resistance voltage pulse set 13 (see FIG. 11A) to the memory cell M11. In the application of the high resistance voltage pulse set, the negative pre voltage pulse 15 and the high resistance voltage pulse 16 are applied to the memory cell M11.

  In the negative voltage pre-voltage pulse 15 application cycle, first, the selected bit line BL0 and the source line SL0 are each set to a voltage of 0V. Next, the selected bit line BL0 is set to the voltage Vb (1.0 V), and the source line SL0 is set to Vs (1.0 V). Next, the word line WL0 to be selected is set to the voltage Vw (2.8V), and the NMOS transistor N11 of the selected memory cell M11 in FIG. 8 is turned on.

  Next, the selected bit line BL0 is set to a voltage of 0 V for a time tlw, and then a pulse waveform having a voltage Vb (1.0 V) is applied again. At this stage, the negative voltage pulse of the weak LR voltage Vph (−1.0 V) is applied to the memory cell M11 in FIG. 8, but the resistance value hardly changes and remains in the LR state.

  In the subsequent application cycle of the high-resistance voltage pulse 16, the selected bit line BL 0 and the source line SL 0 are first set to a voltage of 0V. Next, the word line WL0 to be selected is set to the voltage Vw (2.8V). At this time, the NMOS transistor N11 of the selected memory cell M11 in FIG. 8 is still in the off state. At this stage, the drain terminal and the source terminal of the NMOS transistor N11 in FIG. 8 are at the same potential, and no current flows regardless of whether the transistor is on or off.

  Next, the selected bit line BL0 is set to the voltage Vb (2.2V) for the time thw, and then a pulse waveform having a voltage of 0V is applied again. At this stage, a positive voltage pulse of the HR voltage VH (+2.2 V) is applied to the memory cell M11 in FIG. 8, and the resistance value of the memory cell M11 transitions from a low resistance value to a high resistance value. Thereafter, the word line WL0 is set to a voltage of 0V, and the application of the high resistance voltage pulse is completed. However, it is not necessarily limited to this method.

  FIG. 13C shows a timing chart of a data read cycle for the memory cell M11. In this read cycle, first, the selected bit line BL0 and the source line SL0 are set to a voltage of 0V. Next, the selected bit line BL0 is precharged to the read voltage Vread.

  Next, the selected word line WL0 is set to the voltage VDD (VDD> Vread), the NMOS transistor N11 of the selected memory cell M11 is turned on, and the selected bit line BL0 is discharged. Thereafter, the sense amplifier 204 detects the value of the current flowing through the selected memory cell M11 after a predetermined period, thereby determining the stored data as data “0” or data “1”. Thereafter, the word line WL0 is set to a voltage of 0 V, and the data read operation is completed.

  For the read operation, the read reference resistor Rref is used in the sense amplifier 204. The LR verification reference resistor RL is used at the time of LR verification reading, and the HR verification reference resistor RH is used at the time of HR verification reading. Except for the above points, the reading method shown in FIG. 13C is the same at the time of LR verify reading and at the time of HR verify reading.

  FIG. 14 is a flowchart illustrating a writing method of the variable resistance nonvolatile memory device according to the study example. Hereinafter, an example of a write operation in the variable resistance nonvolatile memory device of the study example will be described with reference to FIG.

  In FIG. 14, when the flowchart starts (S0), the memory cell (for example, M11 in FIG. 8) of the initial address of the address space to which data is written is selected (S1). When “0” data (HR) is written (Yes in S2), an HR write process for applying the high-resistance voltage pulse set 13 is executed (S3), and when “1” data (LR) is written (No in S2). ), The LR write processing for applying the low resistance voltage pulse set 14 is executed (S6).

  Next, the selected memory cell is connected to the sense amplifier 204, and HR verify read processing or LR verify read processing is performed (S4 or S7). In the case of HR writing, the resistance value of the memory cell is the reference resistance for HR verification. The HR write process (S3) is repeated until the verify determination result passes (when it is determined No in S5). In the case of LR writing, the LR writing process (S6) is performed until the resistance value of the memory cell becomes lower than the reference resistance RL for LR verification and the verification determination result passes (while it is determined No in S8). repeat. It is “verify fail” to be determined No in S5 or S8.

  If the verification determination is passed (Yes in S5 or S8), if there is a next address (No in S9), the process proceeds to the next address writing process (S10), and if there is not (Yes in S9), the process ends (S11). ).

  According to such a flow, in HR writing, writing is performed in a higher resistance state than the HR verification reference resistor RH, and in LR writing, writing is performed in a lower resistance state than the LR verification reference resistor RL, and writing with a predetermined operation window secured is possible. Become.

  Here, steps S4 and S7 correspond to the timing chart of FIG. 13C, step S3 corresponds to the timing chart of FIG. 13B, and step S6 corresponds to the timing chart of FIG. 13A.

(3) Results Next, circuit operation results and problems in the case of using the circuit configuration and circuit operation of the study example described above will be described.

  Here, as an example, in the write flow of FIG. 14, the verification determination value of HR verification (S5) (= HR verification reference resistance RH in FIG. 10) is 40 kΩ, and the verification determination value of LR verification (S8) (= LR verification use). Consider the case where the reference resistance RL) is 7.5 kΩ.

  FIGS. 15 and 16 are diagrams showing frequency distributions of resistance values when resistance increasing and resistance decreasing are repeated 50,000 times in a resistance variable nonvolatile memory device (1 kbit). More specifically, the cell immediately before and immediately after the HR verification (S5) and the LR verification (S8) when the operation of performing the entire LR write after the entire HR write is repeated 50,000 times for the 1 k-bit memory cell array. The frequency distribution of resistance (1 kbit × 50,000 times) is shown. FIG. 15 is a diagram showing a frequency distribution of resistance values when the resistance increase and the resistance decrease are repeated 50,000 times without performing the verify operation. FIG. 16 is a diagram showing a frequency distribution of resistance values when increasing resistance and decreasing resistance are repeated 50,000 times while performing a verify operation.

  The circles in the figure are the measurement limits, and in the distribution after LR writing, the cells of 17 kΩ or more are output as 17 kΩ, and in the distribution after HR writing, the cells of 43 kΩ or more are output as 43 kΩ, respectively.

  As can be seen from FIG. 15, before the verify operation is performed, the upper limit of the cell current distribution after LR writing is 17 kΩ or more, and the lower limit of the cell current distribution after HR writing is expanded to 10.6 kΩ. That is, it can be confirmed that a gap (operation window) between the resistance value distribution of the element to which the low resistance voltage pulse is applied and the resistance value distribution of the element to which the high resistance voltage pulse is applied cannot be secured.

  FIG. 16 shows the frequency distribution of cell resistance (1 kbit × 50,000 times) immediately after the verify operation is performed and the HR verify (S5) passes and immediately after the LR verify (S8) passes. is there. From FIG. 16, it can be confirmed that the resistance value on the LR side converges to 10 kΩ or less by performing the verify operation. Even on the HR side, since the resistance value fluctuates after the verify operation passes, the distribution of the resistance value exceeds 40 kΩ, but the bit with the lowest resistance value (tail bit) is 14 kΩ. Therefore, it can be seen that the operation window can be secured by performing the verify operation.

  FIG. 17 shows the transition of the average number of fail times per bit in the LR verify operation when the same operation as described above is performed. The number of verify failures is about 0.05 at the initial stage of writing, but increases to about 0.4 near 50,000 times. In other words, after 50,000 times, a verify failure occurs on average 0.4 times per write, so a total of 1.4 write operations are required, and the write speed is 40% lower than the design speed. I found that there was a problem.

[First embodiment]
The inventors of the present application have found that the above-mentioned problems can be solved by devising the circuit configuration and circuit operation. The circuit configuration and operation related to the first embodiment will be described below.

(1) Device Configuration The variable resistance nonvolatile memory device according to the first example has the same hardware configuration as the study example shown in FIGS. Note that the standby signal for a predetermined time described below may be generated by one or both of the write circuit 206 and the control circuit 210 in FIG. 8, or a control signal input to the variable resistance nonvolatile memory device 200. May be given.

(2) Operation FIG. 18 is a flowchart showing a write method of the variable resistance nonvolatile memory device according to the first embodiment. Hereinafter, the operation method and the effect of the resistance change type memory device according to the first embodiment will be described with reference to FIGS. 8, 9, and 18. FIG. The following operations can be executed based on the control of the control circuit 210, for example.

  When the flowchart starts, a memory cell (for example, M11) having an initial address in an address space in which data is written is selected (S1). In the “0” data (HR) writing (Yes in S2), the HR writing process of applying the high resistance voltage pulse set 13 is executed (S3). Next, the selected memory cell is connected to the sense amplifier 204, and HR verify read processing is performed (S4). The HR write processing is performed until the resistance value of the memory cell becomes higher than the HR verify reference resistance RH and the verify determination result is passed. Repeat (S3) (No in S5). If the verification determination is passed (Yes in S5), if there is a next address (No in S9), the process proceeds to the writing process of the next address (S10), and if there is not (Yes in S9), the process ends (END).

  In S2, when “1” data (LR) is written (No in S2), first, LR writing processing for applying the low resistance voltage pulse set 14 is executed (S6). Next, the selected memory cell is connected to the sense amplifier 204, and LR verify read processing is performed (S7). When the resistance value of the memory cell is higher than the reference resistance RL for LR verification (No in S8: verify fail), verify is performed. The LR writing process (S6) is repeated until the determination result passes.

  In the above description, when the number of failed verification results exceeds the specified number (N times) (Yes in S11), after waiting for a predetermined time (S12), the LR writing process is executed again (S6). Next, the selected memory cell is connected to the sense amplifier 204, and the LR verify read process is performed (S7). When the resistance value of the memory cell is higher than the reference resistance RL for LR verification (No in S8), the LR verify fail is performed. If the number of times (number of times No in S8) is less than N times, the LR writing process (S6) is repeated until the verification determination result passes (S11). When the number of LR verify failures has reached N times or more, a predetermined time is waited (step S12), the number of LR verify failures is reset (reset), and then the LR write processing (S6) is executed again.

  The number of LR verify failures may be stored in a register or the like provided in the variable resistance nonvolatile memory device 200, or an address signal, a control signal, or the like may be stored in the variable resistance nonvolatile memory device 200. You may memorize | store in the memory controller or arithmetic unit which supplies.

  If the LR verification determination is passed (Yes in S8), if there is a next address (No in S9), the process proceeds to writing the next address (S10), and if there is not (Yes in S9), the process ends (END). .

  Note that the number of verifications may or may not be reset to 0 after waiting for a predetermined time (S14). When the number of verifications is reset, after the next LR write, a predetermined time is not waited until the number of verifications reaches N times again. If the number of verifications is not reset, a predetermined time is always waited until the LR verification determination is passed.

  In the above, the method of relaxing the verification determination when the number of LR verify failures exceeds the specified number for LR writing has been described, but the same applies to HR writing, and for both LR writing and HR writing, A method may be applied.

[Second Embodiment]
The second embodiment differs from the first embodiment only in the operation method with the same apparatus configuration as the first embodiment.

(1) Apparatus configuration Since it can be the same as that of the first embodiment, detailed description thereof is omitted.

(2) Operation FIG. 19 is a flowchart showing a write method of the variable resistance nonvolatile memory device according to the second embodiment. In FIG. 19, the LR-V flag is set to 0 when first writing to a predetermined address space.

  When the flowchart starts, a memory cell (for example, M11) at an initial address in an address space in which data is written is selected as shown in FIG. 2 (S1). In the “0” data (HR) writing (Yes in S2), the HR writing process of applying the high resistance voltage pulse set 13 is executed (S3). Next, the selected memory cell is connected to the sense amplifier 204, and HR verify read processing is performed (S4). The HR write processing is performed until the resistance value of the memory cell becomes higher than the HR verify reference resistance RH and the verify determination result is passed. Repeat (S3) (No in S5). If the verification determination is passed (Yes in S5), if there is a next address (No in S9), the process proceeds to the next address writing process (S10), otherwise (Yes in S9), the process proceeds to step S15 (described later). move on.

  In S2, when “1” data (LR) is written (No in S2), first, LR writing processing for applying the low resistance voltage pulse set 14 is executed (S6). Next, the selected memory cell is connected to the sense amplifier 204, and LR verify read processing is performed (S7). When the resistance value of the memory cell is higher than the reference resistance RL for LR verification (No in S8: verify fail), LR The determination of the -V flag is made (S13). When the LR-V flag is “0”, the LR write process (S6) is executed again. When the LR-V flag is “1”, after waiting for a predetermined time (S14), the LR writing process (S6) is executed again. Thereafter, the LR writing process (S6) is repeated until the verification determination result passes.

  If the LR verification determination is passed (Yes in S8), if there is a next address (No in S9), the process proceeds to a writing process of the next address (S10). When there is no next address (Yes in S9) and the LR-V flag is “0”, the average of LR verification of all memory cells or a part of memory cells in the address space in which data is written in this write operation. The number of failures is determined (S15). If the average number of failures is equal to or greater than the specified number (N times), the LR-V flag is set to “1” (S16), and then the write operation is terminated (END).

  The LR-V flag continues to hold “1” once it is set to “1”. That is, at the time of LR writing, when the average number of times of LR verification of all the memory cells in the address space to which data is written or a part of the memory cells is N times or more, the verification is performed in the LR writing to the address space. When failing (No in S8), after waiting for a predetermined time, LR writing is executed again.

  In the above, the method of relaxing the verification determination when the number of LR verify failures exceeds the specified number for LR writing has been described, but the same applies to HR writing, and for both LR writing and HR writing, A method may be applied.

(3) Results Next, circuit operation results when using the circuit configuration and circuit operation of the second embodiment described above will be described.

  As described above, when LR verification fails on average N times or more, when performing LR writing to a predetermined address space thereafter, when verifying fails (No in S8), after waiting for a predetermined time, LR writing again By executing this, the number of LR verifications can be reduced.

  FIG. 20 is a diagram illustrating the transition of the average number of times per one bit of the LR verify write operation when the resistance increase and the resistance decrease are repeated in the resistance change nonvolatile memory device according to the second embodiment. is there. That is, FIG. 20 shows the transition of the average number of fail times per bit in the LR verify operation when the operation method of FIG. 19 is used for LR writing. Here, the threshold value N of the average Verify number for setting the LR-V flag to “1” was set to 8.1. The standby time was 10 minutes.

  From FIG. 20, it was confirmed that when the average number of fail times per bit in the LR verify operation exceeds 8.1 times, the average number of fail times can be reduced by providing a predetermined waiting time.

  FIG. 21 is a diagram showing the transition of the average number of times per bit of the HR verify write operation when the resistance increase and the resistance decrease are repeated in the variable resistance nonvolatile memory device according to the second embodiment. is there. That is, FIG. 21 shows the transition of the average number of fail times per bit in the HR verify operation when the operation method of FIG. 19 is used for HR writing. Here, the threshold N of the average Verify number for setting the HR-V flag to 1 was set to 0.12. The standby time was 10 minutes.

  From FIG. 21, it has been confirmed that when the average number of fail times per bit in the HR verify operation exceeds 0.12, the average number of fail times can be significantly reduced by providing a predetermined waiting time.

  In this experiment data, in order to clarify the effect, the predetermined waiting time is set to 10 minutes. However, the following experiment shows that the effect can be obtained even in a shorter time, for example, about 10 seconds. As the data shows.

  FIG. 22 is a diagram showing the transition of the resistance value until 1000 seconds after applying the high-resistance pulse to the 7-bit resistance change element. In the figure, in order to confirm the rate of change in resistance value, the resistance value of each bit immediately after writing (immediately after voltage pulse application) is Rini, and the resistance value at each time point is divided by Rini. From the figure, it can be confirmed that the resistance value transitions to a higher state with time. That is, for a resistance change element in a high resistance state, the resistance value increases further by waiting for a predetermined time after applying a high-resistance pulse, so by waiting for a predetermined time before applying an additional voltage pulse, It can be seen that the probability of verify failure can be reduced. Also from FIG. 22, since the resistance value is high even if the elapsed time after writing in the high resistance state is about 10 seconds, it can be expected that the average number of failures can be reduced even if the standby time is 10 seconds.

  8 is a so-called 1T1R type memory cell in which one resistance change type element is connected to an NMOS transistor which is a switch element. However, the present invention is not limited to this 1T1R type memory cell. It is not limited. For example, the present invention may be applied to a 1D1R type memory cell using a bidirectional diode as a switch element.

  From the foregoing description, many modifications and other embodiments of the present invention are obvious to one skilled in the art. Accordingly, the foregoing description should be construed as illustrative only and is provided for the purpose of teaching those skilled in the art the best mode of carrying out the invention. The details of the structure and / or function may be substantially changed without departing from the spirit of the invention.

  One embodiment of the present invention is useful as a variable resistance nonvolatile memory device and a writing method thereof that can improve data writing speed and suppress deterioration by improving data recording and reading accuracy.

13 High-resistance voltage pulse set 14 Low-resistance voltage pulse set 15 Pre-voltage pulse 16 High-resistance voltage pulse 17 Pre-voltage pulse 18 Low-resistance voltage pulse 100 Resistance change element 100a First electrode 100b Resistance change layer 100b-1 First variable resistance layer 100b-2 Second variable resistance layer 100c Second electrode 101 First electrode terminal 102 Second electrode terminal 103 Gate terminal 104 NMOS transistor 105 First electrode terminal 110 Memory cell 120 Memory cell array 130 Pulse application device 140 Resistance Variable nonvolatile memory device 200 Variable resistance nonvolatile memory device 201 Memory main body 202 Memory cell array 203 Column selection circuit 204 Sense amplifier 205 Data input / output circuit 206 Write circuit 207 Row driver 208 Row selection circuit 20 Address input circuit 210 Control circuit 211 Write power supply 218 Current mirror circuit 219 Clamp transistor 220 Clamp transistor 221 Reference circuit 222 Selection transistor 223 Selection transistor 224 Differential amplifier 225 Transistor 226 Transistor 227 Selection transistor 702 Read reference current generation circuit 703 LR Reference current generating circuit 704 HR reference current generating circuit

Claims (12)

A writing method of a variable resistance nonvolatile memory device including a memory cell array having a plurality of memory cells including a variable resistance element,
In the write operation, when the first voltage pulse is applied, the resistance variable element changes from the first resistance state used for storing the first information to the first resistance state used for storing the second information. It changes to a second resistance state having a low resistance value, and has a characteristic of changing from the second resistance state to the first resistance state when a second voltage pulse is applied,
For resistance variable elements that do not satisfy the criteria for confirming that the resistance state has changed despite the application of a voltage pulse for changing the resistance state, an additional element for changing the resistance state Perform a verify write operation to apply a voltage pulse,
A writing method in which, when the number of verify write operations performed on a predetermined number of resistance change elements to be written exceeds a predetermined number, the additional voltage pulse is not applied and the apparatus waits for a predetermined time. The verify write operation is performed by reading the resistance value of the resistance variable element after the first voltage pulse is applied, and determining that the read resistance value is higher than the first threshold resistance value. The first voltage pulse is applied again to the element as the additional voltage pulse,
In the verify write operation, when the number of the verify write operations that have been performed on one resistance variable element to be written exceeds the first threshold number, the additional voltage pulse is generated. The writing method according to claim 1, wherein the writing method waits for a predetermined time without applying. The verify write operation is performed by reading the resistance value of the resistance variable element after the second voltage pulse is applied, and determining that the read resistance value is lower than the second threshold resistance value. The second voltage pulse is applied again to the element as the additional voltage pulse,
In the verify write operation, when the number of the verify write operations that have been performed on one resistance variable element to be written exceeds the second threshold number, the additional voltage pulse is generated. The writing method according to claim 1, wherein the writing method waits for a predetermined time without applying. The verify write operation is performed by reading the resistance value of the resistance variable element after the first voltage pulse is applied, and determining that the read resistance value is higher than the first threshold resistance value. The first voltage pulse is applied again to the element as the additional voltage pulse,
In the verify write operation, when the average number of verify write operations performed so far on all or a part of the plurality of variable resistance elements to be written exceeds the first threshold number, The writing method according to claim 1, wherein the method waits for a predetermined time without applying an additional voltage pulse. The verify write operation is performed by reading the resistance value of the resistance variable element after the second voltage pulse is applied, and determining that the read resistance value is lower than the second threshold resistance value. The second voltage pulse is applied again to the element as the additional voltage pulse,
In the verify write operation, when the average number of times of the verify write operation performed so far on all or a part of the plurality of resistance change elements to be written exceeds the second threshold number, The writing method according to claim 1, wherein the method waits for a predetermined time without applying an additional voltage pulse.   In the verify write operation, after the number of the verify write operations performed on the predetermined number of resistance variable elements to be written exceeds the predetermined number of times, the verify write operation is always performed after that. The writing method according to claim 1, wherein the method waits for a predetermined time before applying an additional voltage pulse. A memory cell array having a plurality of memory cells including a resistance variable element;
In the write operation, when the first voltage pulse is applied, the resistance variable element changes from the first resistance state used for storing the first information to the first resistance state used for storing the second information. It changes to a second resistance state having a low resistance value, and has a characteristic of changing from the second resistance state to the first resistance state when a second voltage pulse is applied,
For resistance variable elements that do not satisfy the criteria for confirming that the resistance state has changed despite the application of a voltage pulse for changing the resistance state, an additional element for changing the resistance state When a verify write operation for applying a voltage pulse is performed and the number of verify write operations performed on a predetermined number of resistance variable elements to be written exceeds a predetermined number, the additional voltage pulse is applied. Without waiting for a predetermined time without a pulse application device,
A variable resistance nonvolatile memory device. The pulse applying device reads the resistance value of the resistance variable element after the first voltage pulse is applied as the verify writing operation, and the read resistance value is higher than the first threshold resistance value. The first voltage pulse is applied again as the additional voltage pulse to the determined resistance change element,
In the verify write operation, when the number of the verify write operations that have been performed on one resistance variable element to be written exceeds the first threshold number, the additional voltage pulse is generated. The variable resistance nonvolatile memory device according to claim 7, which waits for a predetermined time without applying voltage. The pulse applying device reads the resistance value of the resistance variable element after the second voltage pulse is applied as the verify writing operation, and the read resistance value is lower than a second threshold resistance value. The second voltage pulse is applied again as the additional voltage pulse to the determined resistance change element,
In the verify write operation, when the number of the verify write operations that have been performed on one resistance variable element to be written exceeds the second threshold number, the additional voltage pulse is generated. The variable resistance nonvolatile memory device according to claim 7, which waits for a predetermined time without applying voltage. The pulse applying device reads the resistance value of the resistance variable element after the first voltage pulse is applied as the verify writing operation, and the read resistance value is higher than the first threshold resistance value. The first voltage pulse is applied again as the additional voltage pulse to the determined resistance change element,
In the verify write operation, when the average number of verify write operations performed so far on all or a part of the plurality of variable resistance elements to be written exceeds the first threshold number, The variable resistance nonvolatile memory device according to claim 7, which waits for a predetermined time without applying an additional voltage pulse. The pulse applying device reads the resistance value of the resistance variable element after the second voltage pulse is applied as the verify writing operation, and the read resistance value is lower than a second threshold resistance value. The second voltage pulse is applied again as the additional voltage pulse to the determined resistance change element,
In the verify write operation, when the average number of times of the verify write operation performed so far on all or a part of the plurality of resistance change elements to be written exceeds the second threshold number, The variable resistance nonvolatile memory device according to claim 7, which waits for a predetermined time without applying an additional voltage pulse. When the number of times of the verify write operation performed on the predetermined number of resistance variable elements to be written exceeds the predetermined number of times, the pulse applying device always performs the verify write operation thereafter. The resistance variable nonvolatile memory device according to claim 7, wherein the variable resistance nonvolatile memory device waits for a predetermined time before applying the additional voltage pulse.

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