CN113517015A - A method and device for realizing multi-level storage of memory cells - Google Patents
A method and device for realizing multi-level storage of memory cells Download PDFInfo
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- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0035—Evaluating degradation, retention or wearout, e.g. by counting writing cycles
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0052—Read process characterized by the shape, e.g. form, length, amplitude of the read pulse
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0092—Write characterized by the shape, e.g. form, length, amplitude of the write pulse
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Abstract
本发明涉及一种实现存储单元多级存储的方法及装置，方法包括：根据存储单元的电阻随电脉冲变化率划分每个阻态对应的电阻区间；统计所述每个电阻区间对应的电脉冲范围，确定多级存储进行每个阻态操作时设置的电脉冲范围；根据所述电阻区间和所述电脉冲范围对所述存储单元进行脉冲操作，并在每次脉冲操作后通过读操作确认所述相变存储器的电阻值是否到达目标状态，用以控制脉冲操作的停止或继续。本发明能够提高较多位多级存储的成功率，并且降低了功耗，提高了效率。
The invention relates to a method and a device for realizing multi-level storage of a memory cell. The method comprises: dividing a resistance interval corresponding to each resistance state according to the rate of change of the resistance of a memory cell with an electrical pulse; and counting the electrical pulses corresponding to each resistance interval. range, determine the electrical pulse range set when multi-level storage performs each resistance state operation; perform pulse operation on the storage unit according to the resistance interval and the electrical pulse range, and confirm through the read operation after each pulse operation Whether the resistance value of the phase change memory reaches the target state is used to control the stop or continuation of the pulse operation. The invention can improve the success rate of multi-level storage with more bits, reduce power consumption, and improve efficiency.
Description
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a method and an apparatus for implementing multilevel storage of a memory cell.
Background
The phase change memory is considered as a next-generation novel nonvolatile memory due to the advantages of excellent expandability, low read-write delay, large capacity potential, low power consumption and the like, has good compatibility with a standard CMOS (complementary metal oxide semiconductor) manufacturing process, and tends to replace the traditional memory along with the continuous development of the phase change memory.
In recent years, due to the rapid development of the internet of things, cloud services, big data and artificial intelligence, the demand for high-density storage is higher than ever before. Multi-level memory technology (MLC), by storing more than one bit of data in each memory cell, can effectively further increase the storage density of the phase change memory. Amorphous and crystalline phase change materials exhibit different electrical properties, and generally a high resistance amorphous state stores information '0' and a low resistance crystalline state stores information '1', so that a memory cell can store one bit of information. If the amorphous degree or the crystalline degree of the phase-change material is different, the corresponding resistance values are also different, so that one memory cell stores multiple bits of information. The multi-level storage technology can increase the capacity of the storage by times, thereby reducing the cost.
In the research of the multi-level storage technology, the division of the intervals where different states are located is usually to divide the resistance values uniformly after taking the logarithm, and the division method can meet the requirement of multi-level storage when the number of bits is small. However, as the number of multilevel storage bits increases, the resistance interval in which each state is located inevitably decreases accordingly. Although the method of verifying after operation can ensure that the cell is accurately positioned in the target resistance value interval after operation, no matter a method of slowly operating from a low-resistance crystalline state to a high-resistance amorphous state or a method of realizing multi-level storage from high-resistance operation to low resistance is used as the target interval becomes smaller, no matter a method of controlling current amplitude or controlling current pulse width, the interval is easily skipped under the condition that the resistance changes rapidly, so that operation failure is caused.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a method and an apparatus for implementing multi-level storage of a storage unit, which can improve the success rate of multi-bit multi-level storage, reduce power consumption, and improve efficiency.
The technical scheme adopted by the invention for solving the technical problems is as follows: a method for realizing multilevel storage of a storage unit is provided, which comprises the following steps:
(1) dividing a resistance interval corresponding to each resistance state according to the rate of change of the resistance of the storage unit along with the electric pulse;
(2) counting the electric pulse range corresponding to each resistance interval, and determining the electric pulse range set when each resistance state operation is carried out in multi-stage storage;
(3) and performing pulse operation on the storage unit according to the resistance interval and the electric pulse range, and confirming whether the resistance value of the phase change memory reaches a target state through reading operation after each pulse operation so as to control the stop or continuation of the pulse operation.
The step (1) is specifically as follows: and operating the storage unit to a low resistance state or a high resistance state, operating the storage unit by using electric pulses to obtain a curve of resistance changing along with the electric pulses, calculating the slope of each point on the curve, and dividing the interval of each resistance state in the resistance range according to the slope.
When the resistance section corresponding to each resistance state is divided, the resistance section corresponding to the area with the resistance change speed larger than the threshold value is larger than the resistance section corresponding to the area with the resistance change speed smaller than the threshold value.
In the step (3), whether the resistance value of the memory cell is in the target resistance interval is judged by following one read pulse after each pulse operation, if so, the pulse operation is immediately controlled to stop, and the result is output to ensure that the resistance of the memory cell is accurately in the target range.
The electric pulse in the step (1) is a voltage pulse or a current pulse.
The electric pulse change in the step (1) refers to the change of the electric pulse amplitude and/or the change of the electric pulse width.
The technical scheme adopted by the invention for solving the technical problems is as follows: an apparatus for implementing the method is provided, which includes: a pulse generator for generating an electrical pulse to be applied to the memory cell; and the measuring system is used for measuring the resistance values of two ends of the memory cell.
The electrical pulses generated by the pulse generator are nanosecond-scale electrical pulses.
The pulse generator is also for generating a pulse for the read operation that is small enough to avoid changing the current state of the memory cell.
Advantageous effects
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects: the invention divides the different resistance states of the multi-level storage of the phase change memory into intervals by the change rate of the resistance along with the current, so that when the resistance changes quickly, the corresponding resistance interval is larger, and when the resistance changes slowly, the corresponding resistance interval is smaller, thereby obviously improving the success rate of each resistance state of the phase change memory when the bit number is larger. In addition, the electric pulse setting range corresponding to each state is obtained according to the electric pulse statistics corresponding to a large number of unit resistors, so that redundant pulses are avoided, the power consumption can be reduced, and the service life of the unit can be prolonged.
Drawings
FIG. 1 is a schematic diagram of an apparatus for carrying out an embodiment of the present invention;
FIG. 2 is a diagram illustrating a method of dividing resistors according to one embodiment of the present invention;
FIG. 3 is a current distribution corresponding to 6 resistance states in an embodiment of the present invention;
fig. 4 is a probability histogram of the resistance distribution of 16-state multi-level storage in the embodiment of the present invention.
Detailed Description
The invention will be further illustrated with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention may be made by those skilled in the art after reading the teaching of the present invention, and such equivalents may fall within the scope of the present invention as defined in the appended claims.
The embodiment of the invention relates to a method for realizing multilevel storage of a storage unit, which comprises the following steps: dividing a resistance interval corresponding to each resistance state according to the rate of change of the resistance of the storage unit along with the electric pulse; counting the electric pulse range corresponding to each resistance interval, and determining the electric pulse range set when each resistance state operation is carried out in multi-stage storage; and performing pulse operation on the storage unit according to the resistance interval and the electric pulse range, and confirming whether the resistance value of the phase change memory reaches a target state through reading operation after each pulse operation so as to control the stop or continuation of the pulse operation. The memory unit includes, but is not limited to, a phase change memory, a resistive random access memory, and a flash memory.
Taking a phase change memory as an example, in the embodiment, for a phase change memory cell originally used for storing only one bit of information (a high resistance state '0' and a low resistance state '1'), an appropriate pulse is used to operate the phase change memory cell to a low resistance state or a high resistance state, and then a specific electric pulse (different multi-level storage implementation methods correspond to different electric pulses) is used to operate the phase change memory cell, so as to obtain a curve of resistance changing along with the electric pulse, wherein the electric pulse may be a voltage pulse or a current pulse, and the waveform of the electric pulse may be a square wave, a triangular wave, a step wave, and the like, and the change of the electric pulse includes, but is not limited to, that the pulse amplitude is from large to small, that the pulse width is narrowed by a width, and that the pulse width is widened by a width. And calculating the slope of each point on the curve, wherein the larger the slope (absolute value) is, the faster the resistance change in the section is, and the smaller the slope is, the slower the resistance change is. And dividing the interval of each resistance state of the resistance range according to the slope, wherein a larger interval is given when the slope is larger, and a smaller interval is given when the slope is smaller. According to the electric pulse-resistance curves of a large number of units, the electric pulse range corresponding to each resistance state divided in the previous part is counted, so that the electric pulse range corresponding to each resistance state is set and operated, the efficiency can be greatly improved, and the power consumption can be reduced. In the implementation process of the multi-level storage, the multi-level storage of the phase change memory is implemented by using a verification method after operation. A specific pulse is applied to the phase change memory, each pulse operation being followed by a read resistance pulse, notably using a smaller voltage or a smaller current, to avoid changing the current state of the phase change memory. And judging whether the read resistance of the phase change memory is in the target interval range, and stopping sending the pulse once the read resistance reaches the target interval range so that the resistance of the phase change memory is accurately in the target range.
It is easy to find that the invention divides the different resistance states into intervals according to the change rate of the resistance of the memory cell along with the current pulse, and obtains the electric pulse range corresponding to each state according to the electric pulse-resistance curves of a large number of cells. After each operation, whether the target state is reached is confirmed through the read resistance operation, and the operation pulse is controlled to stop or continue. By adopting the method, the success rate of the multi-level storage of the multi-bit phase change memory can be obviously improved, the power consumption can be reduced, the efficiency can be improved, and the cost can be saved.
At least the following basic devices or systems are required to implement the method: at least one operable (read-write) phase change memory cell; at least one pulse generator or on-chip write circuit capable of generating nanosecond level current pulses; at least one measurement system or on-chip read circuit that can accurately measure the resistance of a two-terminal device. As shown in FIG. 1, the phase change memory cell should have a large ratio of high to low resistance values, and there are multiple stable resistance states. The pulse generator or on-chip write circuit is used to generate various pulses to operate the memory cell to various resistance states. The measurement system or on-chip read circuit is used to measure the resistance across the memory cell.
The invention is further illustrated by the following specific example.
The embodiment increases the current pulse amplitude step by step to realize sixteen-state multi-level storage of the phase change memory. In the first step, 800 phase change memory cells SET are first applied to low resistance, while applying 77 current pulses with a pulse width of 50ns, with amplitude from 0.14mA to 0.91mA in steps of 0.01. As shown in fig. 2, a current-resistance curve is obtained, and the first derivative of the curve is obtained to obtain the slope corresponding to each point, i.e. the rate of change of resistance with current. According to the size of the slope, the resistance interval corresponding to each resistance state is divided by combining the sixteen-state multilevel storage to be realized by the embodiment and the total resistance span. Secondly, as shown in fig. 3, counting the current pulses corresponding to the cells in each state resistance range in the range, and determining the current amplitude range set during the multi-stage storage of each state operation. Thirdly, as shown in fig. 4, the cell is operated according to the sixteen state resistance division regions obtained in the previous two steps and the operation current range corresponding to each state, and a read resistance operation is followed after each operation to judge whether the current resistance value of the phase change memory is in the target resistance region, once the current resistance value is reached, the current pulse is immediately stopped to be increased, the result is output, and finally the cell is accurately in the resistance range of the target state.
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