CN113517015B - Method and device for realizing multi-level storage of storage unit - Google Patents
Method and device for realizing multi-level storage of storage unit Download PDFInfo
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- CN113517015B CN113517015B CN202110471674.XA CN202110471674A CN113517015B CN 113517015 B CN113517015 B CN 113517015B CN 202110471674 A CN202110471674 A CN 202110471674A CN 113517015 B CN113517015 B CN 113517015B
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- 238000003860 storage Methods 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims abstract description 25
- 238000012795 verification Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000012782 phase change material Substances 0.000 description 2
- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 230000008092 positive effect Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0035—Evaluating degradation, retention or wearout, e.g. by counting writing cycles
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0052—Read process characterized by the shape, e.g. form, length, amplitude of the read pulse
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0092—Write characterized by the shape, e.g. form, length, amplitude of the write pulse
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Abstract
The invention relates to a method and a device for realizing multi-level storage of a storage unit, wherein the method comprises the following steps: dividing a resistance interval corresponding to each resistance state according to the change rate of the resistance of the memory cell along with the electric pulse; counting the electric pulse range corresponding to each resistance interval, and determining the electric pulse range set when each resistance state operation is carried out by multi-stage storage; and performing pulse operation on the memory unit according to the resistance interval and the electric pulse range, and confirming whether the resistance value of the phase change memory reaches a target state through read operation after each pulse operation so as to control stopping or continuing of the pulse operation. The invention can improve the success rate of multi-level storage with more bits, reduce the power consumption and improve the efficiency.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a method and apparatus for implementing multi-level storage of memory cells.
Background
The phase change memory is considered as a next generation novel nonvolatile memory because of the advantages of excellent expandability, low read-write delay, high capacity potential, low power consumption and the like, has good compatibility with a standard CMOS manufacturing process, and has a trend of replacing the traditional memory along with the continuous development of the phase change memory.
In recent years, due to rapid development of internet of things, cloud services, big data and artificial intelligence, the demand for high-density storage is higher than ever before. The multi-level memory technology (MLC) can effectively further increase the storage density of the phase change memory by storing more than one bit of data per memory cell. The amorphous and crystalline phase change materials exhibit different electrical characteristics, and typically use a high resistance amorphous state to store information '0' and a low resistance crystalline state to store information '1', so that one memory cell can store one bit of information. If the amorphous or crystalline degree of the phase change material is different, the corresponding resistance value is also different, thereby realizing that one memory cell stores a plurality of bits of information. The multi-level memory technology can increase the memory capacity by multiple times, thereby reducing the cost.
In the research of multi-stage storage technology, the intervals where different states are located are often divided uniformly after the logarithm of the resistance value is taken, and when the number of bits is small, the dividing method can meet the requirement of multi-stage storage. However, as the number of bits stored in the multi-stage memory increases, the resistance interval in which each state is located inevitably decreases accordingly. Although the method of verification after operation can ensure that the unit is accurately positioned in the target resistance interval after operation, as the target interval becomes smaller, the interval is easily skipped under the condition of relatively fast resistance change, so that operation failure is caused, whether a method of slowly operating from a low-resistance crystalline state to a high-resistance amorphous state or a method of realizing multi-level storage from high-resistance operation to low-resistance operation is used, or whether the current amplitude or the current pulse width is controlled.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a method and a device for realizing multi-level storage of a storage unit, which can improve the success rate of multi-level storage of more bits, reduce the power consumption and improve the efficiency.
The technical scheme adopted for solving the technical problems is as follows: there is provided a method for implementing multi-level storage of memory cells, comprising the steps of:
(1) Dividing a resistance interval corresponding to each resistance state according to the change rate of the resistance of the memory cell along with the electric pulse;
(2) Counting the electric pulse range corresponding to each resistance interval, and determining the electric pulse range set when each resistance state operation is carried out by multi-stage storage;
(3) And performing pulse operation on the memory unit according to the resistance interval and the electric pulse range, and confirming whether the resistance value of the phase change memory reaches a target state through read operation after each pulse operation so as to control stopping or continuing of the pulse operation.
The step (1) specifically comprises the following steps: and operating the memory unit to a low-resistance state or a high-resistance state, operating the memory unit by using electric pulses to obtain a curve of resistance changing along with the electric pulses, calculating the slope of each point on the curve, and dividing the interval of each resistance state in the resistance range according to the slope.
And when the resistance sections corresponding to each resistance state are divided, the resistance sections corresponding to the areas with the resistance change speed larger than the threshold value are larger than the resistance sections corresponding to the areas with the resistance change speed smaller than the threshold value.
In the step (3), by following a read pulse after each pulse operation, whether the resistance value of the memory cell is in the target resistance interval is judged, if so, the pulse operation is immediately controlled to stop, and the result is output to ensure that the resistance of the memory cell is accurately in the target range.
The electric pulse in the step (1) is a voltage pulse or a current pulse.
The electric pulse change in the step (1) refers to a change in the amplitude of the electric pulse and/or a change in the width of the electric pulse.
The technical scheme adopted for solving the technical problems is as follows: an apparatus for implementing the above method is provided, including: a pulse generator for generating an electrical pulse applied to the memory cell; and the measuring system is used for measuring the resistance values at two ends of the storage unit.
The electric pulse generated by the pulse generator is nanosecond electric pulse.
The pulse generator is also configured to generate a pulse for the read operation that is small enough to avoid changing the current state of the memory cell.
Advantageous effects
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects: according to the invention, different resistance states stored in the phase change memory in multiple stages are divided by the change rate of the resistor along with the current, so that when the resistance changes quickly, the corresponding resistance interval is larger, and when the resistance changes slowly, the corresponding resistance interval is smaller, thereby remarkably improving the success rate of each resistance state when the bit number of the phase change memory is more. In addition, according to the statistics of electric pulses corresponding to a large number of unit resistances, the electric pulse setting range corresponding to each state is obtained, redundant pulses are avoided, power consumption can be reduced, and the service life of the unit is prolonged.
Drawings
FIG. 1 is a schematic diagram of an apparatus for implementing an embodiment of the present invention;
FIG. 2 is a schematic diagram of a resistor partitioning method according to one embodiment of the present invention;
FIG. 3 shows current distribution corresponding to 6 resistance states in an embodiment of the invention;
FIG. 4 is a probability histogram of resistance distribution for 16-state multi-level storage in an embodiment of the invention.
Detailed Description
The application will be further illustrated with reference to specific examples. It is to be understood that these examples are illustrative of the present application and are not intended to limit the scope of the present application. Furthermore, it should be understood that various changes and modifications can be made by one skilled in the art after reading the teachings of the present application, and such equivalents are intended to fall within the scope of the application as defined in the appended claims.
The embodiment of the invention relates to a method for realizing multi-level storage of a storage unit, which comprises the following steps: dividing a resistance interval corresponding to each resistance state according to the change rate of the resistance of the memory cell along with the electric pulse; counting the electric pulse range corresponding to each resistance interval, and determining the electric pulse range set when each resistance state operation is carried out by multi-stage storage; and performing pulse operation on the memory unit according to the resistance interval and the electric pulse range, and confirming whether the resistance value of the phase change memory reaches a target state through read operation after each pulse operation so as to control stopping or continuing of the pulse operation. The memory cell includes, but is not limited to, a phase change memory, a resistance change memory, and a flash memory.
Taking a phase change memory as an example, in this embodiment, for a phase change memory cell originally used for storing only one bit of information (high-resistance state '0' low-resistance state '1'), a proper pulse is used to operate the phase change memory cell to a low-resistance state or a high-resistance state, then a specific electric pulse (different multi-stage storage implementation methods correspond to different electric pulses) is used to operate the phase change memory cell, so as to obtain a curve that the resistance changes with the electric pulse, where the electric pulse may be a voltage pulse or a current pulse, the waveform may be a square wave, a triangular wave, a step wave, etc., the electric pulse changes from large to small in pulse amplitude, and the pulse width changes from wide to narrow, and the pulse width changes from narrow to wide. The slope of each point on the curve is calculated, with a larger slope (absolute value) indicating a faster change in resistance for this portion of the interval and a smaller slope indicating a slower change in resistance. The intervals of each resistance state in the resistance range are divided according to the slope, and a larger interval is given when the slope is larger, and a smaller interval is given when the slope is smaller. According to the electric pulse-resistance curves of a large number of units, the electric pulse range corresponding to each resistance state divided in the last part is counted, so that the electric pulse range corresponding to each resistance state is set, the efficiency can be greatly improved, and the power consumption can be reduced. In the implementation process of multi-level storage, a method of verification after operation is used to realize multi-level storage of the phase change memory. It should be noted that a specific pulse is applied to the phase change memory, and each pulse is followed by a read resistor pulse, which uses a smaller voltage or a smaller current to avoid changing the current state of the phase change memory. Judging whether the read resistance of the phase-change memory is in a target interval range, and stopping sending the pulse immediately once the read resistance reaches the target interval range, so that the resistance of the phase-change memory is accurately in the target range.
It is found that the invention divides the different resistance states according to the resistance of the memory cell along with the current pulse change rate, and obtains the electric pulse range corresponding to each state according to the electric pulse-resistance curves of a large number of cells. After each operation, whether the target state is reached is confirmed through the read resistor operation, so as to control the operation pulse to stop or continue. By adopting the resistive state division, the electric pulse range setting and the verification after operation mode of the method, the success rate of multi-stage storage of the multi-bit phase change memory can be remarkably improved, the power consumption can be reduced, the efficiency can be improved, and the cost can be saved.
At least the following basic devices or systems are required to implement the method: at least one operable (read-write) phase change memory cell; at least one pulse generator or on-chip write circuit capable of generating nanosecond current pulses; at least one measuring system or on-chip read circuit capable of accurately measuring the resistance of the devices at both ends. As shown in fig. 1, the phase change memory cell should have a large ratio of high to low resistance, and have a plurality of stable resistance states. The pulse generator or on-chip write circuit is used to generate various pulses to operate the memory cell to various resistance states. The measurement system or on-chip read circuit is used to measure the resistance across the memory cell.
The invention is further illustrated by a specific example.
The embodiment gradually increases the current pulse amplitude to realize sixteen-state multi-level storage of the phase change memory. In the first step, 800 phase change memory cells SET are first brought to low resistance while pulse width is applied for 50ns, and the amplitude is 0.01 from 0.14mA to 0.91mA, for 77 current pulses. As shown in fig. 2, a current-resistance graph is obtained, and the first derivative of the graph is obtained to obtain the slope corresponding to each point, namely the change rate of resistance with current. According to the slope, the sixteen-state multi-level storage and the total resistance span to be realized in the embodiment are combined to divide the resistance interval corresponding to each resistance state. Second, as shown in fig. 3, the current pulses corresponding to the cells in each state resistance range in the range are counted, and the current amplitude range set during the operation of each state is determined by multi-stage storage. And thirdly, as shown in fig. 4, operating the unit according to the sixteen-state resistance dividing interval obtained in the previous two steps and the operation current range corresponding to each state, judging whether the resistance value of the current phase-change memory is in the target resistance interval or not immediately stopping increasing the current pulse once the resistance value is reached and outputting the result, and finally enabling the unit to be accurately in the resistance range of the target state.
Claims (7)
1. A method for implementing multi-level storage of memory cells, comprising the steps of:
(1) Dividing a resistance interval corresponding to each resistance state according to the change rate of the resistance of the memory cell along with the electric pulse, wherein the resistance interval comprises the following specific steps:
operating the memory unit to a low resistance state or a high resistance state, using electric pulses to operate the memory unit to obtain a curve of resistance changing along with the electric pulses, calculating the slope of each point on the curve, and dividing the interval of each resistance state in the resistance range according to the slope; the resistance interval corresponding to the area with the resistance change speed larger than the threshold value is larger than the resistance interval corresponding to the area with the resistance change speed smaller than the threshold value when the resistance interval corresponding to each resistance state is divided;
(2) Counting the electric pulse range corresponding to each resistance interval, and determining the electric pulse range set when each resistance state operation is carried out by multi-stage storage;
(3) And performing pulse operation on the memory cell according to the resistance interval and the electric pulse range, and confirming whether the resistance value of the memory cell reaches a target state through read operation after each pulse operation so as to control stopping or continuing of the pulse operation.
2. The method of claim 1, wherein in the step (3), it is determined whether the resistance value of the memory cell is within a target resistance interval by immediately following a read pulse after each pulse operation, if so, the pulse operation is immediately stopped, and the result is outputted so that the resistance of the memory cell is accurately within the target range.
3. The method of claim 1, wherein the electrical pulse in step (1) is a voltage pulse or a current pulse.
4. The method of claim 1, wherein the electrical pulse variation in step (1) is a variation in the amplitude of the electrical pulse and/or a variation in the width of the electrical pulse.
5. An apparatus for implementing a method for multi-level storage of memory cells, comprising: a pulse generator for generating an electrical pulse applied to the memory cell; a measuring system for measuring the resistance value across said memory cell, characterized in that the arrangement of the pulse generator and the measuring system is configured to perform the steps of the method of realizing a multi-level memory of a memory cell according to any of claims 1-4.
6. The apparatus of claim 5, wherein the electrical pulse generated by the pulse generator is a nanosecond electrical pulse.
7. The apparatus of claim 5, wherein the pulse generator is further configured to generate a pulse of the read operation that is small enough to avoid changing a current state of the memory cell.
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