CN115083474A - Control method and device for multi-resistance-state memristor and test platform - Google Patents
Control method and device for multi-resistance-state memristor and test platform Download PDFInfo
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Abstract
The application discloses a control method, a device and a test platform of a multi-resistance-state memristor, wherein the method comprises the following steps: determining a target resistance state of the memristor; calculating a target current of the memristor according to the target resistance state, and generating an optimal regulation strategy of the memristor according to the resistance state range of the target resistance state; the target gate end voltage or the target reset voltage pulse width of the memristor is matched according to the optimal adjusting strategy and the target current, and the memristor is adjusted according to the target gate end voltage or the target reset voltage pulse width until the actual resistance state of the memristor reaches the target resistance state, so that different resistance states can be stably and rapidly reached, and the service life of the memristor is prolonged while the energy consumption is reduced. Therefore, the problems that time consumption is too long, energy consumption is too large, the service life of the memristor can be shortened and the like caused by the fact that the related technology cannot be rapidly switched to the target resistance state are solved.
Description
Technical Field
The application relates to the technical field of memristor control, in particular to a control method and device for a multi-resistance-state memristor and a test platform.
Background
With the popularization and continuous development of portable electronic products such as smart phones, tablet computers, mobile storage devices and the like, the market of nonvolatile memories is continuously expanded. Flash memory based on charge storage is a mainstream product in the non-volatile memory market for more than twenty years but still has the following disadvantages under new application scenarios and application requirements. Such as poor endurance, slow programming speed, and high operating voltage. And today flash memories based on charge storage are reaching their physical scaling limits very quickly, with scaling becoming more and more important, and with decreasing speed also becoming faster. The memristor has the potential of miniaturization, is simple in structure, good in data retention characteristic and high in reading and writing speed, can be applied to multi-value storage of neural computation, and has the capacity of replacing a flash memory.
Reliability of memristors is one of the most critical factors considered in the use of memristors, with endurance being one of the most important aspects. At present, the multi-bit endurance test is mainly divided into two strategies: one method is to artificially divide a resistance state interval into different sections to define different resistance states after the high and low resistance states of the memristor are obtained through testing. The memristor can be operated to a target resistance state step by step through the pulse and the small-amplitude operation voltage, and then the endurance test is carried out.
And the other method is that after the high-low resistance state of the memristor is obtained through testing, the resistance state interval is artificially divided into different interval sections to be defined as different resistance state. By means of the mode of changing the amplitude of the operation voltage, the state of the memristor can be operated to a target resistance state through the voltage which is changed continuously in the SET/RESET operation amplitude, and then the endurance test is carried out.
However, the related art only needs to change the resistance state step by step to the target resistance state, cannot switch to the target resistance state quickly, and thus consumes a lot of time, and is poor in practicability, and multiple SET and RESET operations may be performed repeatedly to reach the target resistance state, so that the energy consumption is increased, the service life of the memristor is reduced, and a solution is urgently needed.
Disclosure of Invention
The application provides a control method and device for a multi-resistance-state memristor and a test platform, and aims to solve the problems that time consumption is too long, energy consumption is too large, the service life of the memristor can be shortened and the like due to the fact that a related technology cannot be quickly switched to a target resistance state.
An embodiment of a first aspect of the application provides a control method for a multi-resistance-state memristor, which includes the following steps: determining a target resistance state of the memristor; calculating a target current of the memristor according to the target resistance state, and generating an optimal adjusting strategy of the memristor according to the resistance state range of the target resistance state; and matching the target gate terminal voltage or the target reset voltage pulse width of the memristor according to the optimal regulation strategy and the target current, and regulating the memristor according to the target gate terminal voltage or the target reset voltage pulse width until the actual resistance state of the memristor reaches the target resistance state.
Optionally, in an embodiment of the present application, the generating an optimal adjustment strategy of the memristor according to the resistance state range of the target resistance state includes: when the target resistance state is in a preset low resistance state range, the optimal adjusting strategy is to adjust the gate terminal voltage of the memristor; when the target resistance state is within a preset high resistance state range, the optimal adjusting strategy is to adjust the reset voltage pulse width of the memristor.
Optionally, in an embodiment of the present application, the calculating a target current of the memristor according to the target resistance state includes: and matching the target resistance state with a pre-calculated resistance state-current corresponding relation to determine the target current of the memristor.
Optionally, in an embodiment of the present application, the matching a target gate terminal voltage or a target reset voltage pulse width of the memristor according to the optimal regulation strategy and a target current includes: when the optimal adjustment strategy is to adjust the gate terminal voltage of the memristor, matching the target current with a pre-calculated current-gate terminal voltage corresponding relation, and determining the target gate terminal voltage corresponding to the target current; and when the optimal adjustment strategy is to adjust the reset voltage pulse width of the memristor, matching the target current with a pre-calculated current-reset voltage pulse width corresponding relation, and determining the target reset voltage pulse width corresponding to the target current.
The embodiment of the second aspect of the present application provides a control device of a multi-resistance state memristor, including: the determination module is used for determining a target resistance state of the memristor; the generation module is used for calculating a target current of the memristor according to the target resistance state and generating an optimal regulation strategy of the memristor according to the resistance state range of the target resistance state; and the matching module is used for matching the target gate end voltage or the target reset voltage pulse width of the memristor according to the optimal regulation strategy and the target current, and regulating the memristor according to the target gate end voltage or the target reset voltage pulse width until the actual resistance state of the memristor reaches the target resistance state.
Optionally, in an embodiment of the present application, the generating module includes: the first adjusting unit is used for adjusting the gate terminal voltage of the memristor according to the optimal adjusting strategy when the target resistance state is in a preset low resistance state range; and the second adjusting unit is used for adjusting the reset voltage pulse width of the memristor according to the optimal adjusting strategy when the target resistance state is in a preset high-resistance state range.
Optionally, in an embodiment of the present application, the generating module includes: and the calculation unit is used for matching the target resistance state with a pre-calculated resistance state-current corresponding relation and determining the target current of the memristor.
Optionally, in an embodiment of the present application, the matching module includes: the first judging unit is used for matching the target current with a pre-calculated current-gate end voltage corresponding relation and determining a target gate end voltage corresponding to the target current when the optimal adjusting strategy is to adjust the gate end voltage of the memristor; and the second judging unit is used for matching the target current with a pre-calculated corresponding relation of current-reset voltage pulse width when the optimal regulation strategy is to regulate the reset voltage pulse width of the memristor, and determining the target reset voltage pulse width corresponding to the target current.
An embodiment of a third aspect of the present application provides a test platform, including: the multi-resistance memristor control method comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor executes the program to execute the multi-resistance memristor control method according to the embodiment.
Therefore, the embodiment of the application has the following beneficial effects:
the method includes the steps that a target resistance state of a memristor is determined; calculating a target current of the memristor according to the target resistance state, and generating an optimal regulation strategy of the memristor according to the resistance state range of the target resistance state; the target gate end voltage or the target reset voltage pulse width of the memristor is matched according to the optimal adjusting strategy and the target current, and the memristor is adjusted according to the target gate end voltage or the target reset voltage pulse width until the actual resistance state of the memristor reaches the target resistance state, so that different resistance states can be stably and quickly reached, and the service life of the memristor is prolonged while the energy consumption is reduced. Therefore, the problems that time consumption is too long, energy consumption is too large, the service life of the memristor can be shortened and the like caused by the fact that the related technology cannot be rapidly switched to the target resistance state are solved.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a flow chart of a control method of a multi-resistance state memristor according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a memristor sandwich structure provided according to an embodiment of the present application;
FIG. 3 is a schematic structural diagram of a memristor memory cell 1T1R provided according to an embodiment of the present application;
FIG. 4 is a diagram of memristor multi-bit states provided in accordance with an embodiment of the present application;
FIG. 5 is a schematic diagram of SET and RESET for a memristor provided in accordance with an embodiment of the present application;
FIG. 6 is a schematic diagram illustrating a principle of achieving multiple stable low resistance states of a memristor by controlling a gate voltage according to an embodiment of the present application;
FIG. 7 is a schematic diagram illustrating a principle of implementing memristors with multiple stable high-resistance states by controlling the pulse width of a RESET voltage according to an embodiment of the present application;
FIG. 8 is a typical test chart of memristor endurance provided according to an embodiment of the present application;
FIG. 9 is a schematic diagram of an execution logic of a control method for a multi-resistance state memristor according to an embodiment of the present application;
FIG. 10 is an example diagram of a control device of a multi-resistive state memristor according to an embodiment of the present application;
fig. 11 is a schematic structural diagram of a test platform provided in the application embodiment.
Description of reference numerals: the device comprises a determining module-100, a generating module-200, a matching module-300, a memory-1101, a processor-1102 and a communication interface-1103.
Detailed Description
Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application.
The following describes a control method, a control device and a test platform of a multi-resistance state memristor according to embodiments of the present application with reference to the accompanying drawings. In view of the problems mentioned in the background art, the present application provides a control method of a multi-resistance-state memristor, in which method, a target resistance state of the memristor is determined in an embodiment of the present application; calculating a target current of the memristor according to the target resistance state, and generating an optimal regulation strategy of the memristor according to the resistance state range of the target resistance state; the target gate end voltage or the target reset voltage pulse width of the memristor is matched according to the optimal adjusting strategy and the target current, and the memristor is adjusted according to the target gate end voltage or the target reset voltage pulse width until the actual resistance state of the memristor reaches the target resistance state, so that different resistance states can be stably and rapidly reached, and the service life of the memristor is prolonged while the energy consumption is reduced. Therefore, the problems that time consumption is too long, energy consumption is too large, the service life of the memristor can be shortened and the like caused by the fact that the related technology cannot be rapidly switched to the target resistance state are solved.
Specifically, fig. 1 is a flowchart of a control method of a multi-resistance state memristor according to an embodiment of the present application.
As shown in fig. 1, the control method of the multi-resistance state memristor includes the following steps:
in step S101, a target resistance state of the memristor is determined.
The most common structure of memristors is a sandwich (MIM) structure, as shown in fig. 2. The Top Electrode (TE) is made of a Top metal oxide, the Bottom Electrode (BE) is made of a Bottom metal oxide, and the middle resistive layer is made of a dielectric thin film material with variable resistivity. The change of the resistance state of the resistance change layer is controlled by different voltages applied between the two metal oxide layers, and the memristor completes information storage through the change of the high-resistance state and the low-resistance state of the middle resistance change layer.
Fig. 3 shows a common structure 1T1R (1-transistor-1-memristor) of a memristor memory cell, which is formed by connecting a transistor and a memristor in series, wherein a gate of the transistor is connected with a word line (Wordline, WL), a source is connected with a source line (Sourceline, SL), a drain is connected with one end of the memristor, and the other end of the memristor is connected with a bit line (Bitline, BL). The voltage on the WL can control whether the transistor is on or off, acting as a gate, enabling precise control of each memory cell.
In order to improve the storage density of the memristor, the memristor is no longer satisfied with a nonvolatile memory device as a single bit, and the memristor can already complete a multi-bit storage function at present. The principle of multi-bit storage is that the State of the memristor is not simply divided into two states, namely, a High Resistance State (HRS) and a Low Resistance State (LRS), but the whole High Resistance State interval and the whole Low Resistance State interval are divided into a plurality of different states, for example, the original Low Resistance State (LRS) interval is divided into different Low Resistance states such as LRS1 and LRS2, the original High Resistance State interval is divided into different High Resistance states such as HRS1 and HRS2, and at this time, the memristor is changed into a multi-bit memory device by the plurality of different states, and fig. 4 shows a schematic diagram of the multi-bit State of the memristor.
Therefore, after the bit number of the memristor during testing is determined, all resistance state intervals of the memristor are divided, and one resistance state is selected as a target resistance state.
In step S102, a target current of the memristor is calculated according to the target resistance state, and an optimal adjustment strategy of the memristor is generated according to the resistance state range of the target resistance state.
After the target resistance state is determined through the operation, the embodiment of the application determines the target current corresponding to the memristor according to the target resistance state, and obtains the optimal adjusting strategy of the memristor according to the resistance state range of the target resistance state.
Optionally, in an embodiment of the present application, calculating a target current of the memristor according to the target resistance state includes: and matching the target resistance state with the pre-calculated resistance state-current corresponding relation to determine the target current of the memristor.
It can be understood that the memory mechanism of the memristor is an operation mechanism that voltages in different directions or different magnitudes are applied between an upper electrode and a lower electrode of the memristor to enable the device to present different resistance states of high resistance and low resistance. When an SET operating voltage is applied between two electrodes of the memristor, ionized Conductive ions enter the resistive material layer to form a current flowing path, and the flowing current is increased, so that a Conductive Filament (CF) is formed, and the state of the memristor is a low-resistance state; when a RESET operation voltage is applied between the two electrodes of the memristor, the conductive ions return to the two electrodes, due to the absence of the conductive ions, the conductive filament is broken, the flowing current is reduced, the state of the memristor is a high-resistance state, and the SET and RESET principles of the memristor are shown in fig. 5.
Therefore, the corresponding relation exists between the resistance state and the current, so that the target resistance state is matched with the pre-calculated resistance state-current corresponding relation, and the target current of the memristor is determined.
Optionally, in an embodiment of the present application, generating an optimal adjustment strategy for the memristor according to a resistance state range of a target resistance state includes: when the target resistance state is in the preset low resistance state range, the optimal regulation strategy is to regulate the gate terminal voltage of the memristor; when the target resistance state is in the preset high resistance state range, the optimal adjusting strategy is to adjust the reset voltage pulse width of the memristor.
Specifically, after the target current of the memristor is calculated according to the target resistance state, the multiple different low resistance states of the memristor are achieved in a control grid end voltage mode, the conduction degree of the transistor is controlled by changing the voltage of the grid end, the maximum current value flowing through the memristor can be changed, the low resistance state values obtained under the same SET voltage are different due to the different maximum current values, the diameter of the conductive filament is increased due to the fact that the larger the current value is, and therefore the multiple different low resistance state values can be obtained. The current value of the high resistance state still does not change during the RESET operation and thus the resistance value of the high resistance state is substantially unchanged. Therefore, the operation of a plurality of different stable low-resistance states can be completed, and the specific implementation principle is shown in fig. 6.
Secondly, a plurality of different stable high-resistance states of the memristor are realized by controlling the pulse width of the RESET voltage, when the pulse width of the RESET voltage is increased, the gap between the conductive filament and the electrode is increased, the size of the conductive filament is gradually reduced, and therefore the current flowing through the memristor in the high-resistance state during RESET can be reduced. This operation does not affect the low resistance state current obtained at SET and therefore does not change the resistance at the low resistance state. By the operation, the high-resistance state interval can be flexibly divided into different stable high-resistance states, and the specific implementation principle is shown in fig. 7, so that the optimal adjusting strategy of the memristor is determined according to the resistance state range of the target resistance state.
In step S103, the target gate terminal voltage or the target reset voltage pulse width of the memristor is matched according to the optimal adjustment strategy and the target current, and the memristor is adjusted according to the target gate terminal voltage or the target reset voltage pulse width until the actual resistance state of the memristor reaches the target resistance state.
After the target current of the memristor is obtained according to the target resistance state and the optimal regulation strategy of the memristor is generated according to the resistance state range of the target resistance state, in order to enable the actual resistance state of the memristor to reach the target resistance state, the target gate terminal voltage or the target reset voltage pulse width of the memristor needs to be further obtained in the embodiment of the application.
Specifically, in one embodiment of the present application, matching a target gate terminal voltage or a target reset voltage pulse width of a memristor according to an optimal regulation strategy and a target current includes: when the optimal regulation strategy is to regulate the grid end voltage of the memristor, matching the target current with a pre-calculated current-grid end voltage corresponding relation, and determining the target grid end voltage corresponding to the target current; and when the optimal regulation strategy is to regulate the reset voltage pulse width of the memristor, matching the target current with the pre-calculated corresponding relation of the current-reset voltage pulse width, and determining the target reset voltage pulse width corresponding to the target current.
Further, the durability test of the memristor can be carried out in a mode of controlling the voltage of the control gate and controlling the pulse width of the RESET voltage. The endurance of the memristor may also be referred to as the ability to be repeatedly erased. The memristor is switched back and forth from a low resistance state to a high resistance state through the operations of the SET and the RESET until the state of the memristor cannot reach a preset resistance state range in any way when the SET or RESET operation is carried out, the memristor fails at the moment, the recorded cycles of the SET/RESET conversion are called the number of times of the durability of the memristor, and the principle of the durability test of the memristor is shown in FIG. 8.
As shown in fig. 9, when the endurance test of the memristor is performed in the present embodiment, it is first necessary to determine the bit number n during the memristor test, and then divide all resistance state intervals of the memristor into 2n-1 different low resistance states and 2n-1 different high resistance states. The operating conditions of each different low resistance state can be determined by a strategy of controlling the gate voltage; the operating conditions for each of the different high resistance states can be determined by a strategy of controlling the RESET voltage pulse width. And recording the operating conditions corresponding to different resistance states and then testing the durability. And selecting a target resistance state, achieving a preset target resistance state through the operating conditions of the resistance state, if the target resistance state can be achieved, recording the target resistance state once, and then repeating the test operation until the final test times are recorded after the target resistance state cannot be achieved, thereby completing the durability test.
According to the control method of the multi-resistance-state memristor, the low resistance state interval is divided into a plurality of different low resistance states by changing the voltage of the gate end, the high resistance state interval is divided into a plurality of different high resistance states by changing the RESET voltage pulse, the whole resistance state interval is fully and reasonably utilized, overlapping does not exist between each configuration, and the operation conditions when the resistance states are achieved are recorded. And only corresponding operating conditions need to be used during each resistance state updating, so that a large amount of time is saved, the energy consumption is reduced, and the multi-bit durability of the memristor is improved. Theoretically, as long as the interval between the high resistance state and the low resistance state is larger, the control method of the multi-resistance-state memristor provided by the embodiment of the application can more stably separate different resistance state ranges, and further more rapidly and stably improve the multi-bit durability of the memristor.
Next, a control apparatus of a multi-resistance state memristor according to an embodiment of the present application is described with reference to the drawings.
FIG. 10 is a block schematic diagram of a control apparatus of a multi-resistance state memristor of an embodiment of the present application.
As shown in fig. 10, the control device 10 of the multi-resistance state memristor includes: a determination module 100, a generation module 200 and a matching module 300.
The determination module 100 is configured to determine a target resistance state of the memristor. The generation module 200 is configured to calculate a target current of the memristor according to a target resistance state, and generate an optimal adjustment strategy of the memristor according to a resistance state range of the target resistance state. The matching module 300 is configured to match a target gate terminal voltage or a target reset voltage pulse width of the memristor according to the optimal adjustment strategy and the target current, and adjust the memristor according to the target gate terminal voltage or the target reset voltage pulse width until an actual resistance state of the memristor reaches a target resistance state.
Optionally, in an embodiment of the present application, the generating module 200 includes: the first adjusting unit is used for adjusting the gate terminal voltage of the memristor according to the optimal adjusting strategy when the target resistance state is in the preset low resistance state range; and the second adjusting unit is used for adjusting the reset voltage pulse width of the memristor according to the optimal adjusting strategy when the target resistance state is in the preset high-resistance state range.
Optionally, in an embodiment of the present application, the generating module 200 includes: and the calculating unit is used for matching the target resistance state with the pre-calculated resistance state-current corresponding relation and determining the target current of the memristor.
Optionally, in an embodiment of the present application, the matching module 300 includes: the first judgment unit is used for matching the target current with a pre-calculated current-gate end voltage corresponding relation and determining a target gate end voltage corresponding to the target current when the optimal regulation strategy is to regulate the gate end voltage of the memristor; and the second judgment unit is used for matching the target current with a pre-calculated corresponding relation of current-reset voltage pulse width when the optimal regulation strategy is to regulate the reset voltage pulse width of the memristor, and determining the target reset voltage pulse width corresponding to the target current.
It should be noted that the foregoing explanation of the embodiment of the control method for a multi-resistance state memristor is also applicable to the control device for a multi-resistance state memristor of the embodiment, and is not repeated here.
According to the control device of the multi-resistance-state memristor, the target resistance state of the memristor is determined; calculating a target current of the memristor according to the target resistance state, and generating an optimal regulation strategy of the memristor according to the resistance state range of the target resistance state; and matching the target gate end voltage or the target reset voltage pulse width of the memristor according to the optimal regulation strategy and the target current, and regulating the memristor according to the target gate end voltage or the target reset voltage pulse width until the actual resistance state of the memristor reaches the target resistance state, so that different resistance states are stably and quickly reached, lower energy consumption is ensured, and the service life of the memristor is prolonged.
Fig. 11 is a schematic structural diagram of a test platform according to an embodiment of the present application. The test platform may include:
a memory 1101, a processor 1102, and a computer program stored on the memory 1101 and executable on the processor 1102.
The processor 1102, when executing a program, implements the control method of the multi-resistance state memristor provided in the above embodiments.
Further, the test platform further comprises:
a communication interface 1103 for communicating between the memory 1101 and the processor 1102.
A memory 1101 for storing computer programs that are executable on the processor 1102.
The memory 1101 may comprise high-speed RAM memory, and may also include non-volatile memory (non-volatile memory), such as at least one disk memory.
If the memory 1101, the processor 1102 and the communication interface 1103 are implemented independently, the communication interface 1103, the memory 1101 and the processor 1102 may be connected to each other through a bus and perform communication with each other. The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended ISA (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in FIG. 11, but this is not intended to represent only one bus or type of bus.
Optionally, in a specific implementation, if the memory 1101, the processor 1102 and the communication interface 1103 are integrated on one chip, the memory 1101, the processor 1102 and the communication interface 1103 may complete communication with each other through an internal interface.
The processor 1102 may be a Central Processing Unit (CPU), an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits configured to implement embodiments of the present Application.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or N embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "N" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more N executable instructions for implementing steps of a custom logic function or process, and alternate implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of implementing the embodiments of the present application.
It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.
Claims (9)
1. A control method of a multi-resistance-state memristor is characterized by comprising the following steps:
determining a target resistance state of the memristor;
calculating a target current of the memristor according to the target resistance state, and generating an optimal adjusting strategy of the memristor according to the resistance state range of the target resistance state;
and matching the target gate terminal voltage or the target reset voltage pulse width of the memristor according to the optimal regulation strategy and the target current, and regulating the memristor according to the target gate terminal voltage or the target reset voltage pulse width until the actual resistance state of the memristor reaches the target resistance state.
2. The method of claim 1, wherein generating the optimal tuning strategy for the memristor according to the resistance state range of the target resistance state comprises:
when the target resistance state is in a preset low resistance state range, the optimal adjusting strategy is to adjust the gate terminal voltage of the memristor;
when the target resistance state is within a preset high resistance state range, the optimal adjusting strategy is to adjust the reset voltage pulse width of the memristor.
3. The method of claim 1, wherein the calculating a target current of the memristor from the target resistance state comprises:
and matching the target resistance state with a pre-calculated resistance state-current corresponding relation to determine the target current of the memristor.
4. The method of claim 2, wherein the matching a target gate terminal voltage or a target reset voltage pulse width of the memristor according to the optimal regulation strategy and a target current comprises:
when the optimal adjustment strategy is to adjust the gate terminal voltage of the memristor, matching the target current with a pre-calculated current-gate terminal voltage corresponding relation, and determining the target gate terminal voltage corresponding to the target current;
and when the optimal adjustment strategy is to adjust the reset voltage pulse width of the memristor, matching the target current with a pre-calculated current-reset voltage pulse width corresponding relation, and determining the target reset voltage pulse width corresponding to the target current.
5. A control device of a multi-resistance state memristor is characterized by comprising:
the determination module is used for determining a target resistance state of the memristor;
the generation module is used for calculating a target current of the memristor according to the target resistance state and generating an optimal regulation strategy of the memristor according to the resistance state range of the target resistance state;
and the matching module is used for matching the target gate end voltage or the target reset voltage pulse width of the memristor according to the optimal regulation strategy and the target current, and regulating the memristor according to the target gate end voltage or the target reset voltage pulse width until the actual resistance state of the memristor reaches the target resistance state.
6. The apparatus of claim 5, wherein the generating module comprises:
the first adjusting unit is used for adjusting the gate terminal voltage of the memristor according to the optimal adjusting strategy when the target resistance state is in a preset low resistance state range;
and the second adjusting unit is used for adjusting the reset voltage pulse width of the memristor according to the optimal adjusting strategy when the target resistance state is in a preset high-resistance state range.
7. The apparatus of claim 5, wherein the generating module comprises:
and the calculation unit is used for matching the target resistance state with a pre-calculated resistance state-current corresponding relation and determining the target current of the memristor.
8. The apparatus of claim 6, wherein the matching module comprises:
the first judging unit is used for matching the target current with a pre-calculated current-gate end voltage corresponding relation when the optimal adjusting strategy is to adjust the gate end voltage of the memristor, and determining the target gate end voltage corresponding to the target current;
and the second judging unit is used for matching the target current with a pre-calculated corresponding relation of current-reset voltage pulse width when the optimal regulation strategy is to regulate the reset voltage pulse width of the memristor, and determining the target reset voltage pulse width corresponding to the target current.
9. A test platform, comprising: a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor executing the program to implement the memristor multibit generation method of any of claims 1-4.
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