WO2007144026A1

WO2007144026A1 - Electroless nip adhesion and/or capping layer for copper interconnexion layer

Info

Publication number: WO2007144026A1
Application number: PCT/EP2006/063286
Authority: WO
Inventors: Akinobu Nasu; Yi-Tsung Chen; Shyuan-Fang Chen; Chiung-Sheng Hsiung; Tsu-An Lin
Original assignee: L'air Liquide Societe Anonyme Pour L'etude Et L'exploitation Des Procedes Georges Claude; Industrial Technology Research Institute
Priority date: 2006-06-16
Filing date: 2006-06-16
Publication date: 2007-12-21
Also published as: TWI417948B; JP2009540585A; TW200816291A; CN101466869A

Abstract

A method of depositing a copper interconnection layer on a substrate such on a glass substrate for use e.g. in TFT-LCD flat panel interconnection system. The method according to the invention comprising the steps of: a) optionally cleaning the substrate, b) optionally micro-etching the substrate, c) depositing a catalyzation layer on the substrate to obtain a catalyzed substrate, d) conditioning the catalyzed substrate with a conditioning solution to obtain a conditioned catalyzed substrate, e) plating the catalyzed substrate with a NiP layer by contacting said substrate or at least a portion thereof with a wet bath mixture comprising precursors of Ni and P, f) depositing a copper catalyst layer onto the plated NiP layer, depositing a Cu layer on said copper catalyst layer.

Description

Electroless NiP adhesion and/or capping layer

for copper interconnection layer

The invention relates to a process for depositing a copper

interconnection layer on a substrate, such as a glass substrate, for use e.g. in TFT-LCD flat panel interconnection system. It relates more particularly to

a process for manufacturing TFT-LCD flat display panels comprising copper

interconnection buses for electrically connecting each pixel in a pixel matrix

through a thin film transistor (TFT) to the signal electrode buses and to the

scanning electrode buses of the liquid crystal display panel (LCD) or a

plasma or similar display panel.

The basic principles of TFT-LCD panels useful as computer screens

or TV displays are well known. They are for example disclosed in details in

Liquid Crystal Television Display : Principles and applications of liquid

crystals" KTK Scientific publishers Tokyo, chap. 7, 1987 by E. Kaneko.

In a typical flat display panel such as a LCD or plasma panel, the

display material itself such as liquid crystals or discharge gas (respectively)

is sandwiched between two electrically insulating glass substrates. Electrical

interconnection lines or buses are arranged on one surface of at least one

glass substrate to apply electrical voltage to the electrodes between which

the liquid crystal or the discharge gas is provided.

For example, in an active matrix LCD system, there is provided a

plurality of signal or data electrode lines or buses and a plurality of gate electrodes or scanning electrode buses in a matrix arrangement provided on

one surface of one of the glass substrates.

Where the data electrodes and the gate electrodes cross each-other,

there is provided at least one thin film transistor acting as a switch (on-off)

and a pixel electrode, each line of the matrix being successively activated in

order to close the TFT switches and to connect each pixel electrode of this

line to its corresponding data line which provides the signal information for

proper color of the related pixel electrodes, similarly to what is done in

traditional CRT systems.

When the size of the display panel increases, the frequency of the

driving signals needs to be increased, thereby generating an increase of the

parasitic capacitance of these lines, which in turn means a delay in the propagation of the driving signals.

In an attempt to reduce these delays, it has been already suggested,

e.g. in the article entitled "Low Resistance Copper Adress line for TFT-LCD"

- Japan Display' 89 - pp. 498-501 , to use copper instead of aluminium , as

the gate electrode material of the thin film transistor and related matrix interconnection lines or buses, as copper resistivity is much more smaller

compared to aluminium resistivity. This copper layer is deposited by

sputtering process, but as its adhesion to the glass surface is poor, an intermediate Tantalum layer is necessary.

It is also known from US-B 6413845 a process for manufacturing

such metal interconnections on the glass surface of TFT-LCD display panels,

using a Ni film which is deposited on said glass surface by electroless plating, then covered by a photoresist film for patterning the metal deposition.

Then a gold film is deposited on the Ni film, and finally a copper film is

deposited on said gold layer by electroless plating (wet deposition process) to finally obtain an appropriate copper interconnection system. The use of a

photoresist, however, increases the cost of such process.

It is also known by the man skilled in the art, that copper tends to

diffuse within the layers of material on which it is deposited and it is

therefore necessary to provide a barrier layer on a substrate before

depositing the copper layer on it. It is disclosed, e.g. in the article of Osaka

et al. entitled "Electroless nickel ternary along deposition on SiO₂ for application to diffusion barrier layer in copper interconnect technology" -

Journal of the Electronic Society - 149-11-2002. However, these films

disclosed in this document show a lack of adhesion to the glass substrate

and a poor thickness uniformity under the conditions disclosed in this article.

There is accordingly still today a need to define a process which does not increase the cost of deposition on of the diffusion barrier layer,

which provides good adhesion to the glass substrate and which is preferably also applicable to the capping layer deposition process of the copper layer.

According to the invention, electroless NiP layers deposited under

certain conditions were found to be suitable for making both adhesion and

capping layers with a good Cu barrier capability. The roughness and

thickness uniformity of these layers were also found to be satisfactory.

Interconnection and/or gate structure consisting of Cu/NiP/glass is

fabricated by electroless NiP and Cu platings. The NiP layer is plated on the glass substrate for adhesion & barrier of Cu, and the Cu layer is plated on

the NiP as e.g. the gate material. The NiP layer has been found having good

adhesion properties on a glass substrate along with good barrier properties

to avoid copper diffusion. The roughness and thickness uniformity of the NiP

layer have been found satisfactory as well. X-ray analysis revealed that the

NiP is amorphous and has a good thermal stability. This NiP adhesion layer

is a single layer and it is therefore much simpler to carry it out than the

stacked layers disclosed in US-B-6413845, thereby reducing production cost

compared to other wet/dry processes.

The method of depositing a copper interconnection layer on a

substrate such as a glass substrate for use e.g. in a TFT-LCD flat panel

interconnection system according to the invention comprises the steps of:

a) optionally cleaning the substrate,

b) optionally micro-etching the substrate,

c) depositing a catalyzation layer (101 ) on the substrate (100) to

obtain a catalyzed substrate (100, 101 ),

d) conditioning the catalyzed substrate with a conditioning solution

to obtain a conditioned catalyzed substrate (100, 101 , 102),

e) plating the catalyzed substrate with an electroless NiP layer

(103) by contacting said substrate or at least a portion thereof

with a wetsbath mixture comprising precursors of Ni and of P to

obtain a plated NiP conditioned catalysed substrate (100, 101 ,

102, 103),

f) depositing a copper catalyst layer (104) onto the plated NiP layer, and

g) depositing a Cu layer (105) on said copper catalyst layer (104).

Preferably, step (f) of this process is is carried out by using a silver

or palladium salt to deposit a thin silver layer (104) onto said NiP layer while

the Cu layer (105) is deposited by plating using a copper salt such as Cu

SO₄

The invention also relates to a substrate material covered on at least

certain portions of it, successively, by a catalysation layer, a conditioning

layer, a NiP layer, a copper catalyst layer and a copper layer.

The invention will now be described in details, referring to the

following figures which represents, as examples:

Figure 1 represents a schematic top view of TFT-LCD display panel;

Figure 2 is a schematic view of the switch matrix organization.

Figure 3 is a detailed view of the interconnection' lines between the

TFT and the electrodes.

Liquid Crystal Display panels are made of a plurality of pixels

organized as a matrix on a substrate and covered by a thin layer of glass

substrate, covering all pixels together.

Each pixel can be viewed as a square electrode system, having a

bottom and a top transparent electrode between which is located the liquid

crystal layer. Above the transparent electrode, is provided the glass

substrate covered by the polarizing layer.

In order to have a structure similar to the traditional CRT system wherein the shadow mask system is associated with the colors dots and the electron

beams, organized as a matrix with successive horizontal scanning lines from

the top to the bottom of the screen, the pixel system is organized similarly

and each line of pixels successively activated (scanned), each pixel in the

activated line receiving on the top electrode an electric signal proportional to

the color needed for this pixel. Therefore, each pixel needs a switch driven

by the scanning signal (lines) which, when activated, connects the top

electrode of each pixel to the adequate voltage (signal source, usually

through a capacitor).The appropriate switches to day are thin films

transistors (TFT) usually made according to the MOS technology.

To manufacture those TFT-FDP screens, there is accordingly a need to make at regular spaces, thin film transistor (MOS type) having a drain

electrode, a source electrode and a gate electrode.

The drain electrode of each TFT is usually connected to the

transparent pixel electrode, the source electrode is connected to a signal

electrode bus, to be made now in copper, while the gate electrode is

connected to the scanning electrode bus.

Figure 1 represents schematically the plurality of pixels arranged in lines,

respectively 10, 11 ,... 12; 20, 21 ,... 22; 30, 31 ,...32; 40, 41 ,... 42. Switches

Sio, Sii... Si2 respectively S₄₀, S₄i ... S41 we connected through their

respective gates to the scanning lines l_i, L₂, L₃, ... L₄ while the respective

source of the switches are connected to the signal column Ci, C₂, ... C₄,

while the drain of each TFT is connected to its respective pixel electrode.

On Figure 2 is schematically explained the fundamentals of the switch matrix circuits (same numbers designating the same references).

On figure 2a is represented a basic TFT switch matrix wherein each

line l_i, L₂, L₃ is connected to the gate of the MOS transistor and each signal

electrode line Ci, C₂, C₃ is connected to the source of the transistor, the

drain of said transistor being connected to the liquid crystal pixel electrode,

which other electrode is ground to earth.

On figure 2b is described the same matrix organization with the

exception of a capacitor Fi, F₂, F₃ connected in parallel to the electrodes of a

pixel 10, 11 , 12... This system allows to always apply a voltage between the

electrodes of a pixel and to vary this voltage (i.e. color of the dot) at each line scanning.

Figure 3 is a schematic view of the interconnection system to realize the matrix interconnection system at a location close to the crossing of lines

L and columns C. The "scanning" interconnection line L has a small

extension 62 connected to the gate 63 of the TFT 66, both lines L and TFT

being deposited on a transparent glass substrate. The interconnection line L

is electrically insulated by the insulating layer 60 from the signal (column) line C crossing the interconnection line L. The signal line C however is

electrically connected to the source electrode 65 of the TFT while the drain

electrode 64 is electrically connected to the pixel electrode 61.

The present invention essentially relates to the way of making the copper gate electrodes of the TFT switch and the scanning interconnection

lines L (but also the signal interconnection lines C) when they are made of

copper and deposited on a glass substrate. Figure 4 exemplifies a cross view of a copper layer deposited on a

glass substrate according to the invention. The glass substrate 100 is

covered by a catalyzation layer 101 , a conditioning layer 102, a NiP layer

103, a copper catalyst layer 104, and a copper layer 105.

The process to obtain such sandwiched layers is explained

hereinafter, by way of examples.

The various steps referred to hereabove are hereafter disclosed

according to preferred embodiments.

Step (a): Cleaning of the glass surface:

Ultraviolet light, ozone solution and/or a de-grease solution such as

mixture of NaOH, Na₂CO₃ Na₃PO₄ are used, to remove organic

contaminants on the surface. It is possible to skip this step when the

surface is clean enough or if such treatment may damage the

substrate or cause unexpected chemical reactions. This step is

carried out for a duration which is preferably between 10sec and

10min for UV and/or ozone treatment, more preferably between

30sec and 3min. When a degreasing solution is used, such cleaning

step is preferably carried out for a duration between 30sec and

10min at a temperature comprised between 3O⁰C to 100⁰C, more

preferably between 1 min to 5min under 5O⁰C to 9O⁰C. The substrate

is then washed with deionized pure water.

Step (b): Micro-etching of the glass surface: The aim of this step is to create micro roughness on the glass

surface, to enhance the adhesion of the NiP layer to the substrate. It

is possible to skip this step if the glass surface has already a

roughness sufficient to provide adhesion or if such treatment may

cause detrimental reactions on the glass surface. Typically, this step

is carried out by immersion into an aqueous solution comprising

0.1 % to 5% by volume of HF, (it may also comprise from 10g/L to

100 g/L of NH₄F) for 10sec to 5min, or typically with an aqueous

solution comprising 0.3% to 3% volume HF and 30g/L to 60g/L of

NH₄F, for 30sec to 3min.

Step (c): Catalyzation layer for NiP:

SnCI₂ and PdCI₂ solutions may be used to carry out this step to

create an ultra thin Palladium layer onto the surface of the glass

substrate. For that purpose, the substrate is immersed into a SnCI₂

solution, then rinsed with Dl water, then immersed into a PdCI₂

solution. Preferably, 0.1 g/L to 50g/L of SnCI₂ in an aqueous solution

comprising 0.1 % to 10% vol. HCI with between 0,1 g/L to 50g/L of

SnCI₂. The PdCI₂ solution is made from an aqueous solution

comprising 0.01 % to 5% vol. HCI and between 0,01 g/L to 5g/L of

PdCI₂. More preferably the SnCI₂ solution comprising 1 g/L to 2Og/IO

of SnCI₂ dissolved into a 0.5% to 5% solution of HCI and the PdCI₂

solution comprises 0.1 g/L to 2g/L of PdCI₂ dissolved into a 0.05% to

1 % HCI solutions. It is anticipated that the following chemical reaction may occur on the glass surface: Sn²⁺ + Pd²⁺ => Sn⁴⁺ + Pd.

Step (d): Conditioning:

An aquaous solution containing a reducing agent is usually used to

carry out this step. It was found that this step was an essential step

to obtain a uniform NiP platied layer. This step may reduce the

oxidative Sn⁴⁺ on the surface and promote a reductive NiP plating

chemistry. This step is carried out by immersion inot a solution

having a similar composition to the solution used in step (e) below,

except that it contains no Ni salt.A solution containing from 5g/L to

50g/L NaH₂PO₂ is used. This process is usually carried out between

for IOsec to 3min.

Step (e): NiP plating:

NiSO₄ and NaH₂PO₂ are used for Ni and P sources. The NaH₂PO₂ is

also worked as reducing agent. Complexing agent is selected from

organic compounds having carboxylic group (-COOX: X is H, metals,

alkyl) and their mixtures. More typically, it is selected from acetic

acid, tartaric acid, glycolic acid, lactic acid and their mixtures. pH of

the solution is adjusted by pH buffer if necessary. In one

embodiment, a solution comprising 10g/L to 45g/L of NiSO₄ 7H₂O,

3g/L to 50g/L of NaH₂PO₂ H₂O, 5ml_/L to 5OmIJL of glycolic acid

(70%) and 3g/L of tartaric acid is used and the substrate is immersed

in it. Lead compounds can be added as stabilizer in the range of O.δppm to 10ppm. The temperature and pH of the bath are in the

range of 5O⁰C to 9O⁰C and 2 to 9, respectively, more typically, 7O⁰C

to 9O⁰C and 2 to 6. Plating time can be determined by plating rate

and required thickness, typically, 30sec to 1 min in case of NiP layers.

Finally, the substrate is washed with D.I. water.

Step (f): Catalyzation for Cu:

The glass substrate is immersed into an AgNO₃ in NH₄OH PdCI₂ in

HCI or Pd (NH₃)₄ CI2 in NH₄OH solution to make ultra thin silver or

palladium layer on NiP surface. 0.1 g/L to 10g/L Of AgNO₃ in 0.01 %

to 1% NH₄OH solution is used more typically. The step is carried out

for 10sec to 5min typically, for 30sec to 1 min more preferably.

For a palladium layer, a solution containing 0,01 g/l to 5 g/l of PdCI₂

in 0,01 % to 5% HCI is used. More preferably, 0,1 g/l to 2 g/l of PdCI₂

is dissolved into a 0,05% to 1 % HCI solution. In other embodiments,

0,1 g/l to 10 g/l of Pd (NH₃)₄CI in 0,1 % to 5% NH₄OH is used.

Then, a reducing step can be also done if the quality of plated Cu is

not satisfactory. 0.1 % to 5% of HCHO solution for 10sec to 5min is

used typically, 0.5% to 3% of HCHO solution is used more typically.

Instead of the HCHO solution, 0.1 g/L to 5g/L of DMAB

(DiMethylAmineBorane) solution for 30sec to 5min is used typically,

0.5g/L to 3g/L of DMAB solution for 1 min to 3min is used more

typically. Step (g): Cu plating:

The copper plating solution comprises a Cu source, a complexing

agent, a reducing agent and pH buffets. 2g/L to 15g/L of CuSO₄ is

typically used for Cu source. Complexing agent is selected from

EDTAS, tartrates, citrates, diamines, sugar alcohols and their

mixtures. In one embodiment, 20 g/L to 60g/L of potassium sodium

tartrate is used. Reducing agent is selected from aldehydes, amines,

hydrazines, amine boranes, glyoxylic acid, ascorbic acid,

hypophosphites and their mixtures. In one embodiment, 0.05% to 1%

of HCHO is used. Ni compounds (i.e., O.1g/L to 10g/L of NiCI₂) can

be added to promote the Cu plating if necessary. Sulfur compounds can be added as stabilizer in the range of 0.1 ppm to 2ppm. The pH

of the solution is adjusted in the range of 9 to 13 with e.g. NaOH.

Plating time can be determined by plating rate and required

thickness; 1 min to 60min typically, 5min to 40min more typically for

several hundreds nm Cu layers.

According to another embodiment of the invention, a NiP layer can

be deposited as a capping or protection layer on the Cu layer, by preferably

repeating step (c) to (e) (with possible cleaning of the copper before step

(C)).

The invention will be now better understood with the following

examples and comparative examples. Example 1

A glass substrate was immersed into a de-greasing solution comprising NaH, Na₂CO₃ Na₃PO₄ for 3min at 8O⁰C in order to remove

organic contaminants on it. After rinsing with de-ionized water, it was dipped

into diluted HF/NH₄HF solution for 1 min to make micro roughness at the

surface. After rinsing with D.I. water, it was immersed into a SnCI₂ solution comprising 10g/L of SnCI₂ in a 1% HCI solution, and then immersed into a

PdCI₂ (solution) comprising 0.3g/L PdCI₂ into a 0.1% HCI solution for 2min in

each solution. After rinsing the sustrate with D.I. water, it was immersed into

a conditioning solution containing a reducing agent for 30sec. Then, it was

immersed into a NiP plating solution. Table 1 shows the bath composition

and the plating conditions.

Table 1

After rinsing with D.I. water, the substrate was immersed for 45sec in

AgNO₃ solution containing 1.5g/L AgNO₃ in to 0.3% NH₄OH solution. After rinsing the substrate with D.I. mater, it was dipped into the Cu plating

described in Table 2, with the corresponding plating conditions:

Table 2

The plated Cu/NiP layers had an excellent adhesion to glass

substrate, as demonstrated by using a "tape" test (no peeling). The

roughness and thickness uniformity of both layers were satisfactory (less

than 5nm and within 5%, respectively). The NiP film consisted of 91 wt% Ni

and 9wt% P. X-ray analysis revealed the NiP was amorphous. The Cu layer

plated on the NiP layer had a low resistivity (2.6μΩcm). The x-ray analysis

also revealed that these two layers of NiP and Cu had good thermal

resistance 40O⁰C for 1 hour and the diffusion of copper into the NiP was

negligible after thin thermal heating step. Comparative Example 1

A copper layer was plated on the same glass substrate using all the

steps used in example 1 without the step of deposition of the NiP layer. The

copper layer obtained showed a poor adhesion onto the substrate and it was

pealed off easily.

Comparative Example 2

NiP and Cu layers were deposited as in Example 1 in a similar

manner to Example 1 , except that step (a) was not done or the temperature

of the step (a) solution was below 3OC. Plated layers showed poor uniformity

and lack of reproducibility, as surface was not clean enough.

Comparative Example 3

All the steps of Example 1 were carried out except step (b). Many

NiP layers showed pure adhesion to the substrate.

Comparative Example 4

Step (a) and (b) as provided in Example 1 were carried out on a

glass substrate. Step (c) was skipped, then steps (d) and (e) were tentatively

carried out, as explained in Example 1. However, no NiP layer was

deposited on the glass substrate.

Comparative Example 5

Various comparative examples were carried out according to Example 1 , except that the concentration of SnCI₂ in step (c) was either lower than 0.1 g/L or higher than 50g/L, or the concentration of PdCI2 was

either lower than 0.01 g/L or higher than 5g/L. In all these examples, no NiP

layer was plated on the substrate or when plated the NiP layer showed a

poor uniformity, a poor adhesion and/or a lack of reproducibility.

Comparative Example 6

All the steps of Examples 1 were carried out on a glass substrate,

except that step (d) waseither not done or the concentration of NaH₂PO₂ solution used was either lower than 5g/L, or of higher than 50g/L. In all these

different cases no NiP layer was plated on the substrate or if plated such NiP

layer showed a poor thickness uniformity, a poor adhesion and/or a lack of

reproducibility.

Comparative Example 7

Various examples were conducted according to Example 1 , except

that the concentrations of NiSO₄ 7H₂O, NAH₂PO₂ H₂O, lactic acid, glycolic

acid, tartaric acid and lead compounds were out of the respective ranges

defined in step (e) hereabove. Either no NiP layer was plated on the

susbstrate or if plated the NiP layer showed a poor uniformity, a poor

adhesion and/or a lack of reproducibility.

Comparative Example 8

Various examples were carried out in a similar way as disclosed in Example 1 , except that the temperature of the NiP plating bath was below

5O⁰C or higher than 9O⁰C. It is some case, no NiP layer was plated on the

substrate or when plated such NiP layer showed a poor thickness uniformity

and/or a lack of reproducibility.

Comparative Example 9

Various examples were carried out in accordance with Example 1 ,

except that this pH of the NiP plating bath was adjusted either below 2 or

higher than 9. In all these various examples, no NiP layer was plated onto

the substract or when plated the NiP layer showed a poor uniformity, a poor

adhesion and/or a lack of reproducibility.

Comparative Example 10

The various steps of Example 1 were carried out except step (f), in which

case, no Cu layer was plated on the NiP layer.

Comparative Example 11

Various examples similar to Example 1 were carried out, except that the concentration Of AgNO₃ in step (f) was lower than 0.1 g/L or higher than

10g/L. Either no Cu layer was plated or the plated Cu layer showed a poor

thickness uniformity, a poor adhesion, a resistivity and/or a lack of

reproducibility. Comparative Example 12

Various examples were carried out in accordance with Example 1 , except PdCI₂ in HCI solution or Pd(NH₃)₄CI₂ in NH₄OH solution was used instead of AgNO₃ in NH₄OH solution at step (f). The step was done using 0.3g/L PdCI₂ Jn 0.1 % HCI or 0.25g/L Pd(NH₃J₄CI₂ in 2 % NH₄OH for 3min immersion. The plated Cu layers showed comparative thickness uniformity, adhesion, resistivity and reproducibility to those of Example 1.

Comparative Example 13

Various examples similar to Example 1 were carried out, except that

the concentrations of respectively CuSO₄ 5H₂O, C₄H₄KNNaO₆ 5H₂O, Ni

compounds, HCHO, and/or sulfur compounds were out of the respective

ranges defined in the step (g) above. No Cu layer was plated onto the

substrate or when plated, showed a poor uniformity, a poor adhesion, a high

resistivity and/or a lack of reproductibility.

Comparative Example 14

Various examples similar to Example 1 were carried out, except that

the pH of the Cu plating bath was adjusted either below 9 or higher than 13.

Either no Cu layer was plated onto the substrate or when plated, or

the Cu layer showed a poor uniformity, a poor adhesion, a high resistivity

and/or a lack of reproducibility.

Claims

1. A method of depositing a copper interconnection layer on a

substrate such as a glass substrate for use e.g. in a TFT-LCD flat panel interconnection system, comprising the steps:

a) optionally cleaning the substrate,

b) optionally micro-etching the substrate, c) depositing a catalyzation layer (101 ) on the substrate (100)

to obtain a catalyzed substrate (100, 101 ), d) conditioning the catalyzed substrate with a conditioning

solution to obtain a conditioned catalyzed substrate (100, 101 , 102),

e) plating the catalyzed substrate with an electroless NiP layer

(103) by contacting said substrate or at least a portion thereof with a

wet bath mixture comprising precursors of Ni and of P to obtain a

plated NiP conditioned catalysed substrate (100, 101 , 102, 103), f) depositing a copper catalyst layer (104) onto the plated NiP

layer, and

g) depositing a Cu layer (105) on said copper catalyst layer

(104).

2. A method according to claim 1 , wherein said step f) is carried out by using a silver salt to deposit a thin silver layer (104) onto said NiP layer.

3. A method according to claim 1 or 2 wherein said Cu layer (105) is

deposited by plating using a copper salt such as Cu SO₄.

4. A substrate material (100) covered on at least certain portions of it successively by a catalysation layer (101 ), a conditioning layer (102), a NiP

layer (103), a copper catalyst layer (104) and a copper layer (105).