TW200839876A - Copper interconnection for flat panel display manufacturing - Google Patents

Abstract

A method of depositing a copper interconnection layer on a substrate for use in a flat panel display interconnection system, comprising the steps of: (a) Coating said substrate with a photoresist layer; (b) Patterning said photoresist layer to obtain a patterned photoresist substrate comprising at least one trench patterned into said photoresist layer; (c) Providing a first catalysation layer onto the patterned photoresist substrate; (d) Providing an electroless plated layer of an insulation layer deposited onto said first catalysation layer; (e) Removing the successively superimposed photoresist layer, catalysation layer and insulation layer except in the at least one trench, to obtain a pattern of the first catalysation layer with an insulation layer deposited thereon.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of depositing a copper interconnect layer on a substrate for use in a flat panel display interconnect system. [Prior Art] The basic principle of the TFT-LCD panel is well known, and it can be widely used as a computer glory or a TV display. In these panels, each pixel * has - the address given by the column number and row number in the pixel matrix that constitutes the screen. A pixel system exists at the intersection of each column and row, and the "column. 4" system interconnects the entire thin film transistor, so the corresponding column and row %, 'starts the thin film transistor (in a conductive state), therefore Make the appropriate pixel color at the pixel electrode; k field $ £. When the corresponding column and row (pixel address) are removed, the transistor turns off the connection of the relevant pixel and returns the pixel to its original display panel size. Shishi eight h plus k, need to increase the frequency of the drive signal,

Resistance C〇pper Address line for DiSPlay’89_pp.498 has been proposed as a gate electrode material for thin film transistors and related matrix rows because the resistivity of copper is much lower than that of aluminum.

As a result, the parasitic capacitance of these lines is increased, so it means delaying the propagation of the drive signal. In a study attempting to reduce these delays, such as the title "LOW TFT-LCD, -Japan uses a sputtered copper instead of an aluminum interconnect wiring or sinking" to fabricate a transistor, but the dry etching of copper is not Because most copper species are not volatile and/or etching gases and by-products are corrosive in most cases. 6 200839876 The semiconductor industry has developed a damascene process in which through-holes are first fabricated and then dried by combining (Standard plating) and wet process (electroplating) fill copper into the hole. As in the semiconductor industry, 'the use of steel is considered to reduce the signal delay in the flat panel display industry, but the damascene process is not considered appropriate because of this The process requires far more steps than the current wiring process ^ has not been used in large boards (such as 15 meters χΐ 8 meters for G5 TFT_LCD panels). Expected 1

The use of the method will cause some technical difficulties and increase manufacturing costs. The other side's also studied the wet etching of steel. Because the same-direction wet residual is used, the shape of the copper interconnect is more difficult to control, and the non-inverted wet money is engraved. Xianxin should be able to easily combine electroless plating process and stripping process. However, combined lithography (4) and electroless plating are not easy to implement. In essence, there are a number of pre-treatment steps to be performed in the electroless plating process, and the pre-processing steps such as the use of the majority of the photoresist are incapable of resisting the test solution. “When the electroless Cu is carried out on the photoresist pattern, the pattern is dissolved in the plating (4) and the desired pattern can no longer be obtained. Moreover, these photoresist layers cannot resist for a long time at an operating temperature of 90 C ( <1 minute). SUMMARY OF THE INVENTION A method for depositing a steel interconnect layer in a non-state interconnect system according to the present invention on a substrate includes the following steps a) coating the substrate with a photoresist layer; b) patterning the photoresist layer to obtain a patterned photoresist layer, at least one of the trenches 3 disposed in the trench in the photoresist layer; 7 on the photoresist layer of 200839876; the first photoresist layer has a better adhesion c) providing a first catalytic layer in the patterned catalytic layer in at least one trench to the substrate compared to the nature. Prison, using ... platinum U mouth up and down at least -----, 曰, The knife u the insulating layer) will adhere to the pattern on it to make a copper interconnect system. The next two steps of the method consist essentially of depositing an insulating layer into a trench and removing the photoresist pattern. These two steps can be Anything to carry out.

According to the first embodiment of the present invention (Fig....), the insulating layer plating step is performed after the first catalytic step, and the interface performs the photoresist pattern removal step, and according to the second specific aspect (Fig. 3) ^ μresist pattern removal

The step is followed by the first catalytic step followed by the step of insulating the electric clock. 9 Both specific aspects provide an insulating layer pattern and a substrate on a catalytic layer pattern on the substrate. Regardless of the particular aspect used, the subsequent steps typically include a second step and an electroless plating step of the copper deposit. Therefore, according to a first embodiment, the method of the present invention additionally comprises the steps of: d) depositing an electroless plating layer of an insulating layer on the first catalytic layer; and θ e) removing the location of at least one trench The photoresist layer, the first catalytic layer and the insulating layer are successively stacked to obtain a catalytic layer pattern and an insulating layer pattern on the substrate. 200839876 According to a second embodiment, the method of the present invention additionally includes the following steps: d) removing the photoresist layer and the layer to obtain a first catalytic layer pattern on the substrate, in addition to the position of the at least one trench, and Providing an electroless plating layer of an insulating layer deposited on the first catalyst to obtain a first catalytic layer pattern and an insulating layer pattern γ on the substrate. According to another embodiment, the method may additionally include the following steps: Providing a second catalytic layer at least on the insulating layer pattern to obtain a catalytic insulating layer. Seized

The second catalytic layer is preferably plated on the entire surface of the substrate, but should be adhered only to the insulating layer rather than to the substrate. According to another embodiment, the method may additionally comprise the step of: g) providing an electroless copper layer on top of the catalytic insulating layer of step £). Here, a simple way to deposit copper on the second catalytic layer on the top of the insulating layer is to immerse the entire substrate in a suitable solution, keeping in mind that the second catalytic layer should have very poor adhesion on the surface of the substrate, Therefore, the copper will not stick to the substrate. Any of the methods described above may additionally include the step of cleaning the substrate prior to step a) and/or the step of microetching the substrate prior to step a). " Uniform, thin and high quality copper layers are available from electroless mines regardless of substrate size. In addition, the 'required copper pattern is available, no electro-peeling method' is obtained without copper etching. The principle of the stripping method is also well known for semiconductor and LCD manufacturing (eg S. w〇lf and R. N Tauber, "silic 〇n pr〇cessing such as adding VLSI (such as ν〇1·1”, Lattice Press). The stripping method consists of the following: 9 200839876 1) Reverse patterning the template layer on the target, 2) finalizing the pattern The layer is plated on all areas of the target, 3) removing the layer on the template layer with the template layer, and leaving the other parts of the layer on the target as the final pattern. The peeling system is widely used for patterning and is not easy to dry. The etched material. The TFT-LCD manufacturing method is disclosed in U.S. Patent No. 7, (10) 5, 332, and 6, 998, 64 () to reduce the number of reticle used during the process. U.S. Patent No. 5,290,664 discloses a A method of manufacturing a gate electrode and a gate, a source, and a gateless metal are disclosed in a contact window, which are formed by a peeling method by a corresponding dry deposition (such as a ruthenium bond). A reverse pattern of light resistance is formed. The photoresist pattern is used as a template layer. Then, the substrate is immersed in various solutions (such as tin and palladium solutions) to catalyze the surface. This method is to perform particle-like adsorption on the surface of the substrate. Catalyst. Then, the electrode is plated with an insulating layer (such as NiP). The φ layer is deposited on the catalysis. Then, the photoresist pattern and the insulating layer on the photoresist are removed together with a removal solution, but no shift In addition to the layer deposited directly on the base substrate, the substrate is then immersed in a solution (such as a silver or palladium solution) to re-catalyze the surface. This method is directed to particle-like adsorption catalysis on the surface of the substrate. After that, there is no copper bond layer. Here, only the bond Cu' can be observed on the insulating layer because the efficiency of Cu on the glass is much worse than that on the insulating layer. Therefore, the desired copper pattern can be obtained. It is not in contact with an alkaline solution, and the method does not require complicated wiring processes such as damascene processes, and does not require the use of a dry/wet residue process which produces some of the problems described above. In addition, the photoresist layer 10 200839876 has a high contact. At 90 ° C The temperature is not more than 10 minutes. The multiple steps reveal that the method of the present invention is based on the preferred embodiment. The substrate cleaning step (optional) depends on - such as Na〇H, Na2C〇3, A solution of a mixture of Na3p〇4 removes any traces of organic contaminants on the substrate by, for example, impregnating a substrate (such as glass). When the surface is sufficiently cleaned or if this treatment is possible Or cause unpredictable envy and g

In the case of a +t shell/month chemical reaction, this step may be omitted. This step is usually carried out for a period of time, preferably 30 seconds to 1 G minutes at a temperature of 3 passages to HHTC, more preferably in the range of (d) Perform i minutes for 15 minutes. The substrate is then washed with deionized (m) water. This cleaning step can also be carried out using ultraviolet light or an ozone solution as necessary. Microetching the base substrate step (optional): The purpose of this step is to create a slightly thicker chain on the substrate to increase the adhesion of the first layer deposited on the substrate. This step can be omitted if the layer (e.g., the insulating layer) has sufficient adhesion to the substrate due to its original roughness or if the microetching treatment may cause an adverse reaction on the glass surface. This step can be carried out by immersing the substrate in an aqueous solution generally containing 体积 5% by volume to 5% by volume of 111 Å (which may also contain 10 gram / liter to 100 gram / liter ^ 1 仏 ^ for 1 〇 to 5 minutes Or more generally, it is accomplished by impregnation of an aqueous solution containing 体积·3 vol% to 3% by volume and 30 gram/liter to 60 gram/liter νη/ for up to 3 minutes to 3 minutes. Cleaning the substrate. 11 200839876 Photoreceptor ringing step (coating, developing and stripping) This step is accomplished by a conventional PR patterning method, which includes the steps of: h - coating the photoresist solution on the substrate; Baking (such as 90. 〇 to dry the layer; - applying a reticle to the layer; - exposing the photoresist to UV light via a reticle; - removing the reticle; ^ using TMAH solution The exposed photoresist (or unexposed, depending on the photoresist) is developed and cleaned with DI pure water; - post-baked (eg 15 〇. 〇 to harden the unremoved photoresist). a catalytic step: In general, a solution of SnCl 2 and PdCl can be used in this step to produce an ultra-thin palladium catalytic layer on the surface, In the trench where the photoresist has been removed; for this purpose, the substrate is immersed in a SnC12 solution, then washed with φ DI pure water, and then immersed in a PdCl 2 solution. Preferably, 〇·1 g is used. / liter to 50 g / liter of SnCl2 in an aqueous solution containing 0.1% by volume to 1% by volume of HC1. The Pdcl2 solution is from 1% by volume to 5% by volume of HC1 and 〇·〇1g/ It is obtained by adding an aqueous solution of pgCl2 to 5 g/L. The SnCl2 solution preferably contains 1 g/L to 20 g/L of SnCl2 dissolved in 5% by volume to 5% by volume of HCl solution, and the PdCl2 solution contains Dissolved in 〇〇5 vol% to 1 vol% 11 (:1 solution 〇.1 g / liter to 2 g / liter of PdCl2. It is expected that the following chemical reactions may occur on the surface of the substrate · · Sn2+ + Pd2+ 12 200839876 , + Pd. Then, the substrate is immersed in a conditioning solution. This conditioning dissolves the original agent, which can reduce the oxidation of Sn4+ on the surface and promote the absence of electricity, and, from the original plating chemistry. According to another specific state As such, this conditioning solution: has a jaw like the plating solution disclosed in the next step below. The group, but without the Ni salt. According to another embodiment, the conditioning solution is a solution of 5 g/liter to 50 g/liter NaHJO2. The impregnation is carried out in the conditioning solution for 10 seconds to 3 minutes.

An electroless plating step of the insulating layer, usually electroless NiP or NiMP (M is selected from the group consisting of W, Mo or -Re) as an insulating layer. NiS〇4 and NaH2P〇2 solutions were used as Ni and source. NaH2P〇2 is also used as a reducing agent. The complexing agent is selected from the group consisting of organic compounds having at least one carboxylic acid group (-COOX: X system selected from the group consisting of H, metal, and alkyl groups) and mixtures thereof. It is preferably selected from the group consisting of acetic acid, tartaric acid, glycolic acid, lactic acid, and mixtures thereof. For electroplating Nip, the substrate is immersed in the solution. When necessary, the pH of the solution is adjusted by pH buffer. A specific embodiment uses Nis04 7H2 一 from 1 gram/liter to 45 gram/liter, Nag2P 〇2 H20 from 3 gram/liter to 50 gram/liter, and 5 liters/liter to 50 liters/liter of glycol Acid (70%) and 3 g/L of tartaric acid/cold solution. A lead compound in the range of 〇5 ppm to 10 ppm may be added as a stabilizer. The bath temperature and pH are preferably maintained at 50T: to 90, respectively. Within the range of 〇 and 2 to 9, better maintained at 70 ° C to 80 ° C and 2 to 6, respectively. The plating time can be determined by the plating rate and the desired thickness, typically 30 seconds to 1 minute for a 5 nanometer NiP layer. Then, the substrate was washed with DI pure water. 13 200839876 Removal of photoresist (PR) loops with bismuth solution or organic solution

To remove the patterned photoresist, immerse the substrate in a removal solution (as in the alkaline/trough solution as used in the cleaning step selected as described above) for 1 minute to 15 minutes. Minutes, depending on photoresist thickness and removal rate. Then, the substrate was washed with DI pure water. The insulating layer plated on the surface of the photoresist is removed with the photoresist, but the layer directly plated on the substrate should remain on the surface. Even if the insulating layer on the first catalytic layer is restored to its original state, the removal solution has the ability to dissolve the photoresist. Second catalytic step: immersing the substrate in a solution containing AgN〇3 dissolved in NH4〇h, PdCl2 dissolved in hci or Pd(NH3)4Cl2 dissolved in NH4OH to deposit an ultra-thin silver or saturating on the substrate On the surface. For the silver layer, a solution of AgN〇3 dissolved in 0.001% to 1% NH4〇H is generally used in a range of from 1 gram per liter to 10 gram per liter. This step can generally be carried out for 10 seconds to 5 minutes, preferably 3 seconds to 1 minute. For the palladium layer, Pdcl2 is used in a solution of 0.01% to 5% 11 (:1). It is better to dissolve PdCh in 〇1 g/L to 2 g/L. 0.05% to i〇/〇HCl solution. In other specific cases, 0.1 g/L to 10 g/L Pd(NH3)4Cl2 is used in 〇1% to 5% NH4OH. · If the thickness uniformity and/or resistivity of the plated Cu is not within the required specification, the reduction step can be completed as the case may be. In this case, the substrate is dipped in the second step of the electric forging > In the conditioning solution, use a solution containing 0.1% to 5% HCHO, more preferably 5% to 3% HCHO. Take 14 200839876 generation using HCHO, can also be used - the sentence contains 〇 · 1 g / liter to 5 g / liter of DMAB (dimethylamine butterfly) solution, (better system 〇 · 5 g / liter to 3 liters of DMAB). ~ Electroless copper plating solution usually contains a ^ 匕 3 a Cu Source, reducing agent, complexing agent and pH buffer as the main component. - 1 person, " 』 using a CuS04 containing 2 g / liter to 15 g / liter and reducing agent, six As the embodiment, the reducing agent is selected from the group consisting of aldehyde, amine, hydrazine, amine boron pr^cutane, glyoxylic acid, ascorbic acid, hypophosphite, and any mixture thereof, M 4 &

Take < fresh. According to a preferred embodiment, 5% to 1% of HCHO is used. A Ni compound (i.e., o.i gram / liter to U) g / liter t NiCl2) may be added to promote the money Cu. The complexing agent can be selected from the group consisting of Ε〇τΑ, tartrate, citrate, diamine, phytol, and mixtures thereof. In a preferred embodiment, sodium potassium tartrate is used in an amount of from 20 g/liter to 60 g/liter. The pH of the solution was adjusted to be in the range of 9 to 13 with an alkaline solution such as Narm, ~+, iNaUH. A sulfur compound having an η 1 ^ fixed in an amount of from 0.1 ppm to 2 ppm may also be added as a stabilizer. The substrate is immersed in the mixed solution. The plating time can be determined by the rate of the ore and the desired thickness. For a few hundred nanometers of Cu layer, it is generally from minutes to 60 minutes, more preferably from 5 minutes to 4 minutes. Here, the copper layer deposited directly on the glass substrate is removed, but the copper layer deposited on the insulating layer is not removed because the effect of plating Cu on the glass is much less than that of plating on the insulating layer. Thus the desired copper pattern can be obtained. The invention will now be more clearly understood from the following examples and comparative examples and Figures 1 to 3 which represent a plurality of specific aspects of the method according to the invention. 0 15 200839876 In Fig. 1, (when necessary) successively cleaning the glass The substrate is 丨 and (if necessary) slightly engraved. Then, a photoresist (P.R.) layer 2 is deposited on the substrate i. A mask 3 having a suitable opening is placed on the p.R. layer 2 and the light is allowed to pass through σ to form a corresponding pattern on layer 2. Then, it is developed and stripped to form a trench 8. Then, a first-catalytic step is performed to deposit a catalytic layer 6 on the patterned layer 2 (in this figure and any other drawings attached to this specification).

The various layers generally do not have a thickness and shape that represent the actual thickness and y-like shape during the process; the relative thickness does not need to exhibit the normal size, and some of the patterns only indicate the superposition. The catalytic layer often has a thickness that is relatively undetectable by the thickness of the photoresist layer, the insulating layer and/or the copper layer. Then, a catalytic bump 7 is fabricated at the bottom of the trench 8. Then, an electric clock is omitted to deposit the edge layers 9, 1G on the catalytic layer 6 and the catalytic bumps 7. . After removing all the photoresist patterns (the adhesion to the substrate is better than the catalytic layer), only the desired insulating layer pattern is left on the catalytic layer (the catalytic bump and the substrate 1 (the first catalytic layer is opposite to the substrate). The adhesiveness is better than that of the photoresist layer. Fig. 2 shows another specific aspect, which is similar to the specific aspect of Fig. 1, but additionally includes depositing a second catalytic layer u on the top end of the insulating layer 1G to generate - catalytic insulation. Layer (1G, U); but the second catalytic layer (11) is preferably deposited on the entire surface of the substrate, but its adhesion to the substrate will not be as good as its adhesion to the insulating layer (10). A step of electrolessly depositing a copper pattern 12 on top of the catalytic insulating layer (10, 11). Figure 3 discloses another specific aspect similar to the specific aspect of Figure i. However, 200839876 performs a photoresist pattern after the first catalytic step. The removal step leaves the catalytic bumps 7 only where appropriate. Then an 'electroless plating step is performed to deposit the insulating layer pattern 13 on the first catalytic layer 7, followed by a second catalytic step to deposit the second catalytic layer 14 ( Preferably deposited on the entire surface as explained above) To provide a catalytic insulating layer (13, 14), and finally deposit a copper layer 15 thereon by electroless plating. Only the copper layer (15) is plated on the second catalytic layer (14) which can be suitably adhered to the previous layer. Above, that is, only plated on the insulating layer pattern (13). The following examples disclose some of the possible aspects of the invention. * [Embodiment] Example 1 At 80 C, the glass substrate is immersed in - containing Na 〇 H,

NaJO4 was removed from the oil solution for 3 minutes to remove organic contaminants from the glass surface. After washing with deionized water, it was immersed in a dilute HF/NH4HF solution for 1 minute to produce microroughness on the surface of the substrate. Then, the conventional positive light φ is applied to the substrate, exposed to UV light through a mask, patterned, and post-baked on the substrate to be developed. After developing the photoresist layer, the substrate was immersed in a SnCl2 solution containing 1 g/L of SnC12 in 1% HC1 solution, and then immersed in a solution containing 0.1 g/L of PdCl2 in 0.1% HC1 solution. In the pdcl2 solution (each in each solution for 4 minutes). After the substrate was washed with D.I. water, it was immersed in a conditioning solution containing a reducing agent for 30 seconds. Then, it is immersed in an insulating layer plating solution. Table 1 shows the composition of the bath when NiP is selected as the plating solution for the insulating layer. 17 200839876 and plating conditions: Table 1 Composition conditions NiS04 7H20: 30 g / liter The pH is 5 NaH2P02H20 ·· 30 g / liter by acetate buffer: 70 ° C lactic acid: 15 ml / liter of tartaric acid: 15 g / liter of acetic acid wrong 3H20 · · 1.5ppm After washing with DI water, the substrate is immersed in an experimental solution (composition is the same as the degreasing solution of this embodiment) to shift In addition to the patterned photoresist layer. This step is carried out for 5 minutes. The insulating layer plated on the photoresist layer is removed along with the photoresist layer, but the layer directly plated on the substrate remains on the surface of the substrate. Then, the substrate was immersed in a solution containing 1.5 g/liter of AgN03 in a 0.3% ΝΗ4 ΟΗ solution for 45 seconds in the second catalytic step. After the substrate was washed with DI water, it was immersed in the Cu plating solution described in Table 2 and corresponding plating conditions: Table 2 Composition conditions CuS04 5H20 · · 7 g / liter The pH was 12 C4H4Na06 5H20 : 34 g / by NaOH / Liters room temperature Na2C03 : 3 g / liter NiCl2 : 1 g / liter HCHO (37%) : 13 g / liter thiourea: 〇. 2ppm 200839876 After completing the key copper step, the substrate is cleaned with DI water to obtain the desired copper pattern . The Cu/NiP pattern has excellent adhesion to the glass substrate as evidenced by the win-belt test. The roughness and thickness uniformity of both layers were satisfactory (less than 1 〇 nanometer and within 1 〇%, respectively). The Nip layer contains 91% by weight of Ni and 9 parts by weight. X-ray analysis revealed that the Nip layer was amorphous. The Cii layer plated on the Nip layer has a low resistivity (measured by a four-point detection method of 3 〇μΩ cm). The X-ray analysis also revealed that the substrate had only a slight change in the nitrogen atmosphere of the oven in an oven and after 4 hours of annealing at rc. Example 2 In addition to using a stone wafer instead of a glass substrate, Example 1 was followed. The copper pattern was fabricated. The results obtained on the wafer were consistent with those obtained on the glass substrate. In order to study the Cu diffusion ability of the Nip layer, the plated Cu/NiP layer was annealed at 4 ° C and A χ-ray analysis was performed to measure the amount of Cu diffused into the 夕 曰 β曰 circle. This analysis revealed that the diffusion occurred was negligible and the NiP layer had sufficient Cu blocking ability. The control was performed with 1 insulating layer (NiP). Wet etching to pattern the layer on the substrate. The NiP layer was first plated on the substrate, and then photoresist patterning was performed on the layer as described in Example 1. Then, the insulating layer was etched using a FeC13 solution to pattern the layer. NiP layer. The etching time depends on the thickness and the etching rate, but it is usually 3 minutes to engrave the 50 nm thick Nip layer. After the last name, the substrate: 1 minute in acetone to remove the photoresist. Then, the second reminder is performed as in the first embodiment. Steps and electroless plating of steel layers. 19 200839876 Even if this method can be used to make steel patterns, τ Λ/熬 etch has been extremely difficult to batch copper interconnect shapes because of wet etching.

Floor. U Π twins and bottom etching etched NiP

NiP layer As in the case of Example 1, the copper layer was plated on the substrate, but the copper layer obtained by the helmet deposition showed a poor (four) and a sufficient (iv) separation from the substrate.贝对资施彻^

The embodiment is carried out except that the cleaning step of the base substrate is selected as the case may be or the cleaning step is carried out with a cleaning solution having a temperature lower than 30 t. All the steps. (4) The surface of the glass is contaminated by organic components (such as finger touches and grooves or wiping). The mineral layer shows poor thickness uniformity and/or lack of reproducibility. In these latter cases, performing the cleaning step under appropriate conditions as disclosed above may improve uniformity and/or reproducibility.糸/Control paste Example 4 All the steps of the examples were carried out except that the microetching step was selected as appropriate. When the surface of the substrate is not capable of providing micro-roughness, the plated layer exhibits poor adhesion to the plate. The slight roughness of the substrate can be determined to help improve adhesion. This step is usually necessary when using a commercially available TFT-LCD panel glass substrate (such as Corning 7〇59). #照实施制5 In addition to the first catalytic step, all the steps of the examples were carried out. no

The NlP layer is plated on the substrate, so the copper layer does not have sufficient adhesion to the substrate. Comparative Example 6 Except that the concentration of SnCl2 in the first catalytic step was less than 克1 g/liter or 20 200839876 π at 50 g/liter, or the concentration of pdCi2 was lower than Ο gram/liter or higher than 5 gram/liter. A plurality of comparative examples were carried out in accordance with the examples. In all of these embodiments, the non-NiP layer was plated on the substrate or the poor layer of the mineral layer exhibited poor thickness uniformity, poor adhesion and/or lack of reproducibility. Therefore, the copper layer deposited on the NiP is also unsatisfactory. Disk embodiment 7

All of the steps of Example 1 were carried out on the substrate except that the impregnation step was not carried out in the conditioning solution or the concentration of the NaH2P〇2 solution used was less than 5 g/liter or more than 5 Gg/liter. In all of these different cases, the NiP-free layer is plated on the substrate or if the Nip layer is plated, the Nip layer exhibits poor thickness uniformity, poor adhesion and/or lack of reproducibility. Therefore, the copper layer deposited on the NiP is also unsatisfactory.

Comparative Example Side S A number of examples were carried out in accordance with Example 1 except that the concentrations of NiS〇4 wo, NaH2P〇2, lanthanum, lactic acid glycolic acid and lead compounds were outside the individual ranges defined above. The Nip-free layer is plated on the substrate or if the NiP layer is on the ore, the Nip layer exhibits poor thickness uniformity, poor adhesion and/or lack of reproducibility. Therefore, depositing on the Nip < copper layer is also not satisfactory. Control sinus application 1 9 A number of examples were carried out in a manner similar to that disclosed in Example 1, except that the temperature of the NiP electroplating bath was lower than that of the thief. Usually, no NiP layer is plated

The NiP layer exhibits a poor thickness I and/or lack of reproducibility on the substrate or when the NiP layer is plated. 21 200839876 On the other hand, when the temperature is higher than 90. In the case of ruthenium, if the plating rate is too high, the NiP layer applied exhibits poor adhesion to the glass substrate, which may increase the internal stress of the layer. Therefore, the copper layer deposited on the NiP is also unsatisfactory. In addition, the photoresist layer cannot withstand 9 (the temperature of the TC exceeds i minutes. If the photoresist layer is very thick (to increase the temperature endurance), it becomes difficult to dissolve the layer during the next step. Comparative Example 10 In addition to this NiP plating In the case where the pH of the bath is adjusted to 2 or higher or higher than 9, a plurality of embodiments are carried out in accordance with Example 1. In all of these various embodiments, when no NiP layer is plated on the substrate or plated with a Nip layer, The layer does not exhibit equilibrium characteristics (such as thickness uniformity, adhesion to the substrate, and reproducibility). Therefore, the copper layer deposited on the layer is also unsatisfactory. In addition, when the pH of the bath is higher than 10, The photoresist pattern is typically destroyed (dissolved in solution) during the Nip plating step. This does not complete the desired Cu pattern. Comparative Example 11 In addition to the second catalytic step, multiple steps of Example 1 were performed, in which case It is generally impossible to plate the Cu layer on the Nip layer. #照实施例例 Example 1 is carried out except that the concentration of AgN〇3 in the photoresist pattern step is less than 01 g/liter to more than 10 g/liter. Multiple embodiments. No Cu plating or plating The Cu layer exhibits poor thickness uniformity, poor adhesion and/or lack of reproducibility. Control Example 13 In addition to the second catalytic step, PdCl2 is used in a solution of HC1 or 22 200839876

Pd_3) 4C12 was dissolved in a solution of νΗ4〇η instead of a solution in which AgN〇3 was dissolved in NH4〇h, and various examples were carried out in accordance with Example 1. This step was carried out by dissolving 0.3 g/L of PdCl 2 in 0.1% HCl or 〇 25 g/m of PcKNHAd 2 in 2% NH 4 〇H for 3 minutes. The plated cu layer exhibited thickness uniformity, adhesion, electrical resistivity and reproducibility similar to those obtained in Example 1. Comparative Example T4 A similar example was carried out except that the individual concentrations of CuS〇4 5H2〇, C4H4KNNa〇6 5H2〇, the compound, the hch〇 and/or the sulfur compound were outside the individual ranges defined in the electroless copper plating step above. Multiple embodiments. The no & layer is plated on the substrate or if a layer is plated, the layer of Cu exhibits poor thickness uniformity, poor adhesion, high resistivity and/or lack of reproducibility. Control Implementations 丨1 5 A number of examples of similar embodiments were carried out except that the pH of the CU plating bath was adjusted to below 9 or above 13. When the pH is below 9 and the electromineral dynamics are too low, no Cu layer is plated on the substrate. On the other hand, when the anode is returned to 13, the Cu layer exhibits poor thickness uniformity, poor adhesion, resistivity of the gate and/or lack of reproducibility. It has been assumed that the plating rate is too high and this may increase the internal stress of the layer. The balance of thickness uniformity, adhesion and reproducibility can be obtained within the range defined by the electroless plating step of copper. Example 3 In addition to removing the photoresist pattern before electroless plating of the insulating layer

A copper pattern was produced as disclosed in Example 1 of the yoke. Therefore, the photoresist pR case was removed together with the photoresist layer on the photoresist upper layer & p m 4 without removing the catalytic layer deposited directly on the base substrate of 23 200839876. Therefore, the purpose of catalytic patterning is achieved at the end of the removal of the photoresist pattern. Then, an insulating layer (Nip) is applied. Since only the NiP layer is selectively plated on the catalytic layer, a patterned Nip layer can be obtained on the substrate. Then, as revealed by the truth, it is completed after the second catalytic step.

Cu electroless plating step. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a first embodiment of the present invention;

Figure 2 is another embodiment similar to Figure i; the Figure is in accordance with a second embodiment of the present invention. Ttfy —* Description of the symbols】 1 substrate 2 photoresist layer 3 photomask 4 UV light 5 pattern 6 catalytic layer 7 catalytic bump 8 trench 9 insulating layer 10 insulating layer 11 second catalytic layer 12 copper pattern 13 insulating layer pattern 14 Two catalytic layer 24 200839876 15 copper layer

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Claims (1)

200839876 X. Patent Application Range: A method for depositing a steel interconnect layer on a substrate for planar display of a crying system, comprising the steps of: a) coating the substrate with a photoresist layer; b) Patterning the photoresist layer to obtain a patterned photoresist layer comprising at least one trench patterned in the photoresist layer; C) providing a first catalytic layer in the patterned photoresist layer i, a catalytic layer in at least one of the grooves 璧 + its jx - the wood-to-substrate has a better adhesion to the photoresist layer. 2. According to the method of claim i, the additional steps are: d) providing an insulating layer, electro-electric ore deposit, on the first catalytic layer And (6) removing the successively stacked photoresist layer, the first catalytic layer and the rim layer to obtain a "first catalytic layer pattern and an insulating layer pattern" on the substrate, in addition to the position of at least one trench . 3. The method of claim 3, further comprising the steps of: d) removing the photoresist layer and the first catalytic layer to obtain a first catalysis on the substrate, in addition to the location of the at least one trench a layer pattern, and e) an electroless plating layer providing an insulating layer is deposited on the first catalytic layer pattern to obtain a first catalytic layer pattern and an insulating layer pattern on the substrate. 4. The method according to claim 2 or 3, further comprising the steps of: 26 200839876 f) providing a second catalytic layer at least on the top end of the insulating layer pattern to obtain a catalytic insulating layer. 5. The method of claim 4, further comprising the step of: g) providing an electroless copper layer on top of the catalytic insulating layer of step f). 6. The method of any one of claims 1 to 5, further comprising the step of cleaning the substrate prior to step a). 7. The method according to any one of claims 1 to 6, further comprising the step of micro-etching the substrate prior to step a). XI, ancestral style: such as the next page 27