Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
  • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
  • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
  • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
  • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
  • H10W20/0238—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes through pads or through electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
  • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
  • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
  • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
  • H10W20/0253—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
  • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
  • H10W20/0265—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the sidewall insulation
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/0198—Manufacture or treatment batch processes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D88/00—Three-dimensional [3D] integrated devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/071—Manufacture or treatment of dielectric parts thereof
  • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
  • H10W20/083—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being via holes penetrating underlying conductors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/073—Connecting or disconnecting of die-attach connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/20—Configurations of stacked chips
  • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
  • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W99/00—Subject matter not provided for in other groups of this subclass

Definitions

• This invention relates in general to 3-D integration of circuits and more specifically to a barrier for use in 3-D integration of circuits.
• 3-D integration of circuits is achieved using face-to-face bonding of wafers, such as acceptor wafers and donor wafers, or dies.
• Acceptor wafer is typically the bottom wafer and donor wafer is typically the top wafer.
• Interconnects in the bonded wafers or dies are connected using various techniques, such as stitch vias.
• stitch vias which are typically formed on the backside of a donor wafer, is, however, time consuming and requires additional steps for achieving 3-D integration of wafers or dies. In particular, for example, formation of stitch vias requires two inter- wafer vias having differing lengths that are linked on the backside of the donor wafer.
• etching of inter- wafer vias can cause several problems for etch processing.
• etching of such inter- wafer vias in low-K dielectric wafers requires etching through multiple types of dielectric materials, such as silicon nitride, silicon carbon- nitride, silicon-oxide, and SiCOH containing low-K dielectrics.
• This in turn requires a wide range of etch processes, such as both physical and chemical etch processes.
• Certain physical and chemical etch processes can redistribute the copper into the dielectric layers. This problem, for example, especially occurs when inter-wafer connects are used as embedded etch masks.
• Figure 1 is a partial side view of one embodiment of an exemplary acceptor wafer during a processing stage, consistent with one embodiment of the invention
• Figure 2 is a partial side view of one embodiment of an exemplary acceptor wafer, consistent with one embodiment of the invention
• Figure 3 is a partial side view of one embodiment of a semiconductor device during a processing stage, consistent with one embodiment of the invention
• Figure 4 is a partial side view of one embodiment of a semiconductor device during a processing stage, consistent with one embodiment of the invention
• Figure 5 is a partial side view of one embodiment of a semiconductor device during a processing stage, consistent with one embodiment of the invention
• Figure 6 is a partial side view of one embodiment of a semiconductor device during a processing stage, consistent with one embodiment of the invention.
• Figure 7 is a partial side view of one embodiment of a semiconductor device during a processing stage, consistent with one embodiment of the invention.
• Figure 8 is a partial side view of one embodiment of a semiconductor device during a processing stage, consistent with one embodiment of the invention.
• Figure 9 is a partial side view of one embodiment of a semiconductor device during a processing stage, consistent with one embodiment of the invention.
• a method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer.
• the second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening.
• the method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material.
• the selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad.
• a method for forming a semiconductor device includes providing a first integrated circuit having a landing pad.
• the method further includes attaching a second integrated circuit to the first integrated circuit using at least one bonding layer, the second integrated circuit having an inter-circuit trace, the inter-circuit trace having an opening.
• the method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening.
• the method further includes forming a selective barrier on exposed portions of the inter-circuit trace in the opening, the selective barrier comprising at least one material selected from a group consisting of cobalt and nickel.
• the method further includes extending the opening through the at least one bonding layer to the landing pad.
• the method further includes after extending the opening, filling the opening with a conductive fill material, wherein the conductive fill is electrically connected to the inter-circuit trace and the landing pad.
• a semiconductor device including a first integrated circuit having a landing pad and at least one bonding layer over the landing pad.
• the semiconductor device further includes a second integrated circuit having an inter-circuit trace and at least one bonding layer over the inter-circuit trace, wherein the at least one bonding layer of the second integrated circuit is attached to the at least one bonding layer of the first integrated circuit.
• the semiconductor device further includes a conductive interconnect extending through the second integrated circuit, through an opening in the inter-circuit trace, through the at least one bonding layer of the second integrated circuit, and through the at least one bonding layer of the first integrated circuit to the landing pad, the conductive interconnect electrically connecting the inter-circuit trace to the landing pad.
• the semiconductor device further includes a barrier layer adjacent the inter-circuit trace comprising at least one material selected from a group consisting of cobalt and nickel and located in the opening of the inter-circuit trace, between the inter-circuit trace and the conductive interconnect.
• Figure 1 is a partial side view of one embodiment of an acceptor wafer during a processing stage, consistent with one embodiment of the invention.
• Acceptor wafer 10 may include an interconnect layer 12, an active layer 14, and a semiconductor layer 16.
• Interconnect layer 12 may include interconnect 20 and via 22.
• a landing feature, such as a landing pad 18 may be formed as part of interconnect layer 12, as well.
• a conductive barrier 24 having cobalt or nickel may be formed on top of landing pads.
• Figure 1 shows only one of each of interconnect layer 12, active layer 14, and semiconductor layer 16, acceptor wafer 10 may include additional such layers. Further, as shown in Figure 2, a bonding layer 26 may be formed on top of interconnect layer 12.
• a donor wafer 30 may be bonded face-to-face with acceptor wafer 10.
• Donor wafer 30 may include similar layers as acceptor wafer 10.
• donor wafer 30 may include an interconnect layer 32, an active layer 34, and a semiconductor layer 36.
• Interconnect layer 32 may include an inter- wafer connect trace 38 with an opening 40 formed in inter- wafer connect trace 38.
• Inter- wafer connect trace 38 may look like a line with a hole (opening 40) in it.
• Inter- wafer connect trace 38 may be formed using copper or any other suitable conductive material.
• inter- wafer connect trace 38 may act as an inter-circuit trace in a wafer or a die.
• Donor wafer 30 may have an etch-stop layer 50 formed on interconnect layer 32.
• a bonding layer 42 may be formed over etch-stop layer 50.
• Figure 3 shows separately formed bonding layer 42 and etch-stop layer 50, etch-stop layer may be formed as part of bonding layer 42.
• bonding layer 42 may act as an etch- stop layer.
• only one of acceptor wafer 10 and donor wafer 30 may have a bonding layer.
• active layer 34 and semiconductor layer 36 may include align-keys 46 and 48, which may be used to find features in interconnect layer 32, for example.
• align-keys 46 and 48 may be used to align patterns on the backside of donor wafer 30, which is the top surface of the bonded wafer.
• Figure 3 shows align-keys 46 and 48, these may not be necessary in a SOI wafer, where features may be visible through active layer 34 and semiconductor layer 36.
• Isolation windows 47 and 49 may be formed in active layer 34 and semiconductor layer 36 of donor wafer 30. Isolation windows 47 and 49 may be used to isolate conductive fill material formed in vias, as explained further with respect to Figures 8 and 9.
• Isolation windows 47 and 49 may contain an insulating material, such as an oxide.
• Figure 3 shows only one of each of interconnect layer 32, active layer 34, and semiconductor layer 36, donor wafer 30 may include additional such layers. Additionally, although Figure 3 shows face-to-face bonding of acceptor wafer 10 and donor wafer 30, they may be bonded in other configurations, as well.
• a barrier layer 52 may be formed on at least top and side surfaces of inter-wafer connect trace 38.
• Barrier layer 52 may be formed using tantalum, titanium, tungsten or alloys thereof.
• Figure 3 does not show barrier layer 52 formed over other interconnect traces (20, for example), barrier layer 52 may be formed over other interconnect traces in acceptor wafer 10 and donor wafer 30, as well.
• semiconductor layer 36 of donor wafer 30 may be thinned using mechanical-chemical or chemical-mechanical processes to form thinned semiconductor layer 44.
• a patterned masking layer 54 may be formed over thinned semiconductor layer 44.
• an opening 58 extending through opening 40 (shown in Figure 5) in donor wafer 30 may be formed.
• etch- stop layer 50 is shown in Figure 4 as being directly adjacent to bonding layer 42, etch-stop layer 50 may be placed at a different location in donor wafer 30.
• etch- stop layer 50 may be placed directly under inter- wafer connect trace 38, if interconnect layer 32 did not have inter-wafer connect trace 39 or if inter- wafer connect trace 39 were at the same level as inter-wafer connect trace 38.
• the etch-stop layer may always be positioned directly below the inter- wafer connect trace of an interconnect layer, such as interconnect layer 32, that is closest to the bonding surface of the wafer. Additional openings, as necessary, may be formed.
• Figure 6 shows an additional opening 56. Openings 56 and 58 may expose portions of inter- wafer connect trace 38 and 39.
• the etching process may etch away parts of barrier layer 52 to expose portions of inter-wafer connect trace 38 and 39.
• a barrier (60, 62) may be selectively formed on exposed portions of inter-wafer connect trace 38 and 39.
• barrier (60, 62) may be formed only on the exposed portions of inter- wafer connect trace 38 and 39.
• exposed portions of inter- wafer connect trace 38 and 39 may be treated prior to forming barrier (60, 62) exposed portions of inter- wafer connect trace 38 and 39 may be treated. Such treatment may include completely or partially removing barrier layer 52 or treating the exposed portions with catalytic materials, such as palladium or platinum. Exposed portions of inter-wafer connect trace 38 and 39 may result in the trace material, such as copper being exposed. Barrier (60, 62) may be formed directly on the exposed copper, for example.
• Barrier (60, 62) may be cobalt or nickel containing material, such as cobalt-tungsten-boron, cobalt-tungsten-phosphorous, cobalt-molybdenum-boron, cobalt-molybdenum-phosphorous, cobalt-rhenium-boron, cobalt-rhenium-phosphorous, nickel-tungsten-boron, nickel-tungsten-phosphorous, nickel-molybdenum-boron, nickel- molybdenum-phosphorous, nickel-rhenium-boron, nickel-rhenium-phosphorous, or it may be any other suitable etch resistant material.
• exposed portions of inter- wafer connect trace 38 and 39 may still have a portion of barrier layer 52 with at least some of the copper exposed. Exposed portions of inter- wafer connect trace 38 and 39 may be used to grow the barrier layer. Exposed portions of inter- wafer connect trace 38 and 39 may first be treated using palladium and/or platinum, prior to growing the barrier layer.
• opening 58 may be extended to a landing pad (e.g., a landing pad similar to landing pad 18).
• opening 56 may be extended to another landing pad.
• Figure 8 shows openings 56 and 58 extending to landing pads, these openings may extend to any metal line of acceptor wafer 10 to make appropriate interconnections.
• conductive fill material 64 and 66 may be filled into openings 58 and 56, respectively, for electrically interconnecting acceptor wafer 10 and donor wafer 30.
• Conductive fill material 64 and 66 may be filled using processes, such as electroplating. Isolation windows 47 and 49 may keep active layer 34 and thinned semiconductor layer 44 electrically isolated from conductive fill material.
• a liner and seed layers may be formed in openings 56 and 58 prior to filling conductive fill material 64 and 66 into these openings. These layers may be formed using a chemical vapor deposition or a physical vapor deposition process.

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• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

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• 2006
  • 2006-03-30 US US11/278,042 patent/US7378339B2/en active Active
• 2007
  • 2007-02-22 WO PCT/US2007/062538 patent/WO2007130731A2/en not_active Ceased
  • 2007-02-22 JP JP2009503112A patent/JP2009532874A/ja active Pending
  • 2007-02-22 KR KR1020087023823A patent/KR101352732B1/ko active Active
  • 2007-03-16 TW TW096109128A patent/TWI416691B/zh active
• 2008
  • 2008-04-25 US US12/110,009 patent/US20080197497A1/en not_active Abandoned

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