WO2007126907A1 - Dispositif semiconducteur comprenant des transistors soi et des transistors en bloc et son procédé de fabrication - Google Patents

Dispositif semiconducteur comprenant des transistors soi et des transistors en bloc et son procédé de fabrication Download PDF

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Publication number
WO2007126907A1
WO2007126907A1 PCT/US2007/007705 US2007007705W WO2007126907A1 WO 2007126907 A1 WO2007126907 A1 WO 2007126907A1 US 2007007705 W US2007007705 W US 2007007705W WO 2007126907 A1 WO2007126907 A1 WO 2007126907A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
transistors
crystalline
region
layer
Prior art date
Application number
PCT/US2007/007705
Other languages
English (en)
Inventor
Thomas Feudel
Manfred Horstmann
Karsten Wieczorek
Thomas Heller
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE102006015076.7A external-priority patent/DE102006015076B4/de
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Priority to CN2007800114161A priority Critical patent/CN101416300B/zh
Priority to GB0817679A priority patent/GB2452418B/en
Priority to JP2009502983A priority patent/JP2009532865A/ja
Priority to KR1020087026718A priority patent/KR101340634B1/ko
Publication of WO2007126907A1 publication Critical patent/WO2007126907A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes

Definitions

  • the drive current fluctuations associated with the threshold voltage variations are taken into consideration by appropriate design measures in order to provide a sufficiently high drive current range of the SOI transistors in the memory block.
  • the respective SOI transistors in the memory block are typically formed with a sufficiently large width so as to provide the required drive current margins, thereby requiring a moderately high amount of chip area.
  • other design measures for eliminating threshold fluctuations caused by the floating body potential for instance so-called body ties, arc a very space-consuming solution and may not be desirable for highly scaled and complex semiconductor devices including extended RAM areas.
  • Figure Ig schematically illustrates a top view of a plurality of transistor elements formed as SOl devices and bulk devices, respectively, wherein the transistor width of the bulk devices may be reduced compared to equivalent SOI devices according to the present invention
  • the present invention relates to a technique for forming SOI transistors and bulk transistors commonly in a single substrate, wherein the bulk devices may represent functional circuit blocks of increased sensitivity to hysteresis effects, i.e., to variations in the threshold voltage of respective field effect transistors caused by charge carrier accumulation in the transistor body of non-tied SOI transistors, thereby providing enhanced device stability, without requiring additional body ties or greatly increased transistor width to provide increased drive current capability margins.
  • the transistors may be provided in an SOI architecture, thereby obtaining the advantages of an SOI configuration, that is, high switching speed due to reduced parasitic capacitances, while, on the other hand, in sensitive device areas, such as static RAM areas, cache areas and the like, a significant reduction of chip area occupied by the circuitry may be achieved compared to conventional overall advanced SOI devices.
  • respective memory areas in the device 100 may be formed within the device region 150B on the basis of a bulk transistor architecture, thereby significantly reducing the required floor space, while, for time-critical circuit blocks, the highly efficient SOI architecture may be employed.
  • the lateral sizes of the regions 250S, 250B may range from several tens of micrometers to one hundred or several hundreds of micrometers.
  • a stack of layers may be provided which may include a buried insulating layer 202S, a first crystalline semiconductor region 203S and a mask 204.
  • respective second crystalline semiconductor regions 208 may be formed within the respective bulk regions 250B, wherein the crystalline characteristics of the region 208 may be the same or may differ compared to the characteristics of the region 203S, as is also previously explained with reference to the regions 103 S and 108.
  • Figure 3b schematically illustrates the semiconductor device 300 after the removal of the mask 304 and respective heat treatment so as to form a buried insulating layer 302S within the semiconductor layer 303 in the SOl region 350S.
  • the device 300 comprises a first crystalline semiconductor region 303S formed on the buried insulating layer 302S and also a second semiconductor region 308, which represents the residual of the semiconductor layer 303.
  • further processing may be continued on the basis of process techniques as are previously described with reference to Figures I f and Ig. That is, corresponding SOI transistors may be formed in and on the region 303S, while corresponding bulk devices for memory areas may be formed in and on the regions 308.
  • the semiconductor device 400 as shown in Figure 4a may be formed according to the following processes. After providing the donator substrate 420 comprising the semiconductor layer 403, the implantation process 421 may be performed to position the light atomic species 422 at the appropriate depth on the basis of well-established implantation techniques. Thereafter, an etch mask (not shown) may be formed above the layer 403 so as to expose a portion of the layer 403 corresponding to the insulating layer 402S. Thereafter, a corresponding etch process may be performed in order to remove material of the layer 403 up to a desired depth, and subsequently insulating material may be deposited, for instance by appropriate CVD techniques, wherein, depending on the process parameters, a highly non-conformal deposition process may be obtained.
  • an etch mask (not shown) may be formed above the layer 403 so as to expose a portion of the layer 403 corresponding to the insulating layer 402S.
  • a corresponding etch process may be performed in order to remove material of the layer 403 up to a desired depth

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un dispositif qui, en formant des transistors (151B) analogues à des transistors en blocs ou autres circuits CMOS basé sur SOI dans des zones de RAM sensibles, permet de réaliser des économies significatives dans des zones de valeur de la puce, car les zones de RAM peuvent être formées sur la base d'une configuration de transistors en blocs, éliminant ainsi les effets d'hystérésis qui peuvent typiquement être pris en considération en fournissant des transistors de largeur de transistor augmentée ou en fournissant des liaisons de corps. En conséquence, les bénéfices de la haute vitesse de commutation peuvent être maintenus dans des éléments de circuit, tels que des cœurs de CPU, tout en formant simultanément le circuit de RAM de manière efficace spatialement.
PCT/US2007/007705 2006-03-31 2007-03-30 Dispositif semiconducteur comprenant des transistors soi et des transistors en bloc et son procédé de fabrication WO2007126907A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN2007800114161A CN101416300B (zh) 2006-03-31 2007-03-30 形成半导体器件的方法
GB0817679A GB2452418B (en) 2006-03-31 2007-03-30 Semiconductor device comprising soi transistors and bulk transistors and a method of forming the same
JP2009502983A JP2009532865A (ja) 2006-03-31 2007-03-30 Ｓｏｉトランジスタならびにバルクトランジスタを備えた半導体デバイスとその製造方法
KR1020087026718A KR101340634B1 (ko) 2006-03-31 2007-03-30 Ｓｏｉ 트랜지스터와 벌크 트랜지스터를 포함하여 구성된 반도체 디바이스 및 이것을 형성하는 방법

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE102006015076.7 2006-03-31
DE102006015076.7A DE102006015076B4 (de) 2006-03-31 2006-03-31 Halbleiterbauelement mit SOI-Transistoren und Vollsubstrattransistoren und ein Verfahren zur Herstellung
US11/560,896 US7955937B2 (en) 2006-03-31 2006-11-17 Method for manufacturing semiconductor device comprising SOI transistors and bulk transistors
US11/560,896 2006-11-17

Publications (1)

Publication Number Publication Date
WO2007126907A1 true WO2007126907A1 (fr) 2007-11-08

Family

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Family Applications (1)

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PCT/US2007/007705 WO2007126907A1 (fr) 2006-03-31 2007-03-30 Dispositif semiconducteur comprenant des transistors soi et des transistors en bloc et son procédé de fabrication

Country Status (1)

Country Link
WO (1) WO2007126907A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010267959A (ja) * 2009-05-18 2010-11-25 Soitec Silicon On Insulator Technologies ハイブリッド半導体基板の製造プロセス

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0701286A1 (fr) * 1994-06-16 1996-03-13 Nec Corporation Substrat à silicium sur isolateur et procédé de sa fabrication
US20040026739A1 (en) * 2001-12-27 2004-02-12 Tsutomu Sato Semiconductor device formed in semiconductor layer arranged on substrate with one of insulating film and cavity interposed between the substrate and the semiconductor layer
US20040150044A1 (en) * 2003-01-21 2004-08-05 Hajime Nagano Element formation substrate, method of manufacturing the same, and semiconductor device
US20040183131A1 (en) * 2003-03-17 2004-09-23 Hajime Nagano Semiconductor substrate, method of manufacturing the same, semiconductor device, and method of manufacturing the same
US20050191797A1 (en) * 2004-02-27 2005-09-01 Koji Usuda Semiconductor device and method of manufacturing the same
US20050189610A1 (en) * 2004-02-27 2005-09-01 Koji Usuda Semiconductor device and method of manufacturing the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0701286A1 (fr) * 1994-06-16 1996-03-13 Nec Corporation Substrat à silicium sur isolateur et procédé de sa fabrication
US20040026739A1 (en) * 2001-12-27 2004-02-12 Tsutomu Sato Semiconductor device formed in semiconductor layer arranged on substrate with one of insulating film and cavity interposed between the substrate and the semiconductor layer
US20040150044A1 (en) * 2003-01-21 2004-08-05 Hajime Nagano Element formation substrate, method of manufacturing the same, and semiconductor device
US20040183131A1 (en) * 2003-03-17 2004-09-23 Hajime Nagano Semiconductor substrate, method of manufacturing the same, semiconductor device, and method of manufacturing the same
US20050191797A1 (en) * 2004-02-27 2005-09-01 Koji Usuda Semiconductor device and method of manufacturing the same
US20050189610A1 (en) * 2004-02-27 2005-09-01 Koji Usuda Semiconductor device and method of manufacturing the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
YANG M ET AL: "High Performance CMOS Fabricated on Hybrid Substrate With Different Crystal Orientations", INTERNATIONAL ELECTRON DEVICES MEETING 2003. IEDM. TECHNICAL DIGEST. WASHINGTON, DC, DEC 8 - 10, 2003, NEW YORK, NY : IEEE, US, 8 December 2003 (2003-12-08), pages 453 - 456, XP010684050, ISBN: 0-7803-7872-5 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010267959A (ja) * 2009-05-18 2010-11-25 Soitec Silicon On Insulator Technologies ハイブリッド半導体基板の製造プロセス
KR20100124202A (ko) * 2009-05-18 2010-11-26 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지 하이브리드 반도체 기판의 제조 방법
KR101687603B1 (ko) 2009-05-18 2016-12-20 소이텍 하이브리드 반도체 기판의 제조 방법

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