WO2007116566A1

WO2007116566A1 - Capacitor

Info

Publication number: WO2007116566A1
Application number: PCT/JP2006/325220
Authority: WO
Inventors: Takashi Togami; Noriyuki Kubodera; Tsuyoshi Nakagawa
Original assignee: Murata Manufacturing Co., Ltd.
Priority date: 2006-04-07
Filing date: 2006-12-19
Publication date: 2007-10-18
Also published as: TW200802444A; TWI331759B; JP4873007B2; JPWO2007116566A1

Abstract

In a capacitor, the capacitance of which is changed by an externally applied DC bias, the number of stacked electrodes equipped in the capacitor main body is reduced and a voltage required for applying the DC bias is also reduced. The capacitor main body (23) is provided with a DC bias applying electrode (25), a capacitance acquiring electrode (26), and an earth electrode (24). The DC bias applying electrode (25) is positioned between the capacitance acquiring electrode (26) and the earth electrode (24). The earth electrode (24) is made to serve not only as an electrode for applying the DC bias but also as an electrode for acquiring the capacitance.

Description

Specification

Capacitor

Technical field

The present invention relates to a capacitor, and more particularly to a capacitor whose capacitance can be changed by a DC noise applied from outside.

Background art

[0002] Among variable capacitors, a capacitor whose capacitance can be changed by a DC bias applied from the outside is, for example, described in Japanese Patent Publication No. 5-19970 (Patent Document 1). The capacitor described in Patent Document 1 will be described with reference to FIG. 24 and FIG. FIG. 24 is a front view showing the capacitor with a cross section facing in the stacking direction of the dielectric layers, and FIG. 25 is a plan view showing the capacitor with a cross section extending in the main surface direction of the dielectric layers.

As shown in FIG. 24, the capacitor 1 includes a rectangular parallelepiped capacitor body 3 having a laminated structure including a plurality of dielectric layers 2. The capacitor body 3 also includes DC bias application electrodes 4 and 5 that make a pair with each other, and capacitance acquisition electrodes 6 and 7 that make a pair with each other. Capacitance acquisition electrodes 6 and 7 are positioned between DC bias application electrodes 4 and 5. A dielectric layer 2 is positioned between each of the DC bias application electrode 4, the capacitance acquisition electrode 6, the capacitance acquisition electrode 7 and the DC bias application electrode 5.

[0004] The patterns of the DC bias applying electrodes 4 and 5 and the capacitance acquiring electrodes 6 and 7 described above are well shown in FIG. In FIG. 25, (a), (b), (c), and (d) do not correspond to the stacking order, but FIG. 25 (a) shows a cross section through which the DC bias applying electrode 4 passes. 25 (b) shows a cross section through which the DC bias application electrode 5 passes, FIG. 25 (c) shows a cross section through which the capacitance acquisition electrode 6 passes, and FIG. 25 (d) shows a cross section through which the capacitance acquisition electrode 7 passes. A cross section is shown.

As well shown in FIG. 25, the capacitor body 3 has four side surfaces 8 to L 1 extending in the stacking direction. DC bias applied to sides 8, 9, 10 and 11 respectively Terminal conductor films 12 and 13 for capacity and terminal conductor films 14 and 15 for obtaining capacitance are provided.

As shown in FIG. 25 (a), the DC bias applying electrode 4 is drawn out to the side surface 8, and is electrically connected to the DC bias applying terminal conductor film 12 here. As shown in FIG. 25 (b), the DC bias applying electrode 5 is drawn out to the side surface 9, and is electrically connected to the DC bias applying terminal conductor film 13 here. As shown in FIG. 25 (c), the capacitance acquisition electrode 6 is pulled out to the side surface 10 and is electrically connected to the capacitance acquisition terminal conductor film 14 here. As shown in FIG. 25 (d), the capacitance acquisition electrode 7 is drawn out to the side surface 11 and is electrically connected to the capacitance acquisition terminal conductor film 15 here.

In the capacitor 1 having the above-described configuration, the capacitance formed between the pair of capacitance acquisition electrodes 6 and 7 is extracted from the capacitance acquisition terminal conductor films 14 and 15. At this time, when a DC bias is applied between the DC bias applying electrodes 4 and 5 through the DC bias applying terminal conductor films 12 and 13, the dielectric layer 2 positioned between the DC bias applying electrodes 4 and 5 Dielectric properties such as dielectric constant change. Therefore, the dielectric characteristic of the dielectric layer 2 located between the capacitance acquisition electrodes 6 and 7 changes, and as a result, the capacitance taken out through the capacitance acquisition terminal conductor films 14 and 15 is reduced. Can be changed.

A configuration similar to the capacitor 1 shown in FIG. 24 is described in Japanese Patent Publication No. 5-19969 (Patent Document 2). FIG. 26 is a diagram corresponding to FIG. 24 and showing the capacitor la described in Patent Document 2. In FIG. 26, elements corresponding to those shown in FIG. 24 are denoted by the same reference numerals, and redundant description will be omitted.

In the capacitor la shown in FIG. 26, the DC bias application electrodes 4 and 5 are positioned so as to be sandwiched between the capacitance acquisition electrodes 6 and 7. Other configurations are substantially the same as those of the capacitor 1 shown in FIG.

[0010] However, these capacitors 1 and la have the following problems to be solved.

[0011] First, in order to make the capacitance variable in the capacitors 1 and la, the electrodes provided on the capacitor body 3 include the DC bias application electrodes 4 and 5 and the capacitance acquisition electrode 6. And 7 are required, and at least 3 layers are required for the dielectric layer 2 separating each of the electrodes 4 to 7, which is disadvantageous for miniaturization. Become.

[0012] In addition, in the capacitor 1 shown in FIG. 24, the dielectric layer 2 whose dielectric characteristics are to be changed is merely one layer, but the DC bias is applied to the three dielectric layers 2 because of its structure. I have to mark it. Since the electric field strength is inversely proportional to the distance between the electrodes, in the case of the above structure, if the thickness of each dielectric layer 2 is the same, in order to obtain the required electric field strength, the direct current is three times that of the single layer. It is necessary to apply a voltage, which has the adverse effect of increasing the drive voltage. In addition, not all of the dielectric layer 2 positioned between the DC bias application electrodes 4 and 5 is involved in the capacitance acquisition, so the volume capacity is reduced, and the large capacity is reduced despite the small size. It is difficult to realize.

On the other hand, in the case of the capacitor la shown in FIG. 26, since the DC bias application electrodes 4 and 5 are arranged between the capacitance acquisition electrodes 6 and 7, a dielectric for acquiring the capacitance is obtained. A DC bias is not applied to a part of the body layer 2. When the thickness of each of the dielectric layers 2 is the same, the thickness of the dielectric layers to which the DC bias is applied is 1Z3 of the total thickness of the dielectric layers 2 that contributes to the capacitance acquisition, and the capacitance change With respect to the rate, the detrimental effect of reducing the DC bias characteristic of the material of the dielectric layer 2 to 1Z3 or lower is brought about. In addition, because of the structure, it is difficult to shorten the distance between the capacitance acquisition electrodes 6 and 7, it is disadvantageous for achieving a large capacitance while being small.

Patent Document 1: Japanese Patent Publication No. 5-19970

Patent Document 2: Japanese Patent Publication No. 5-19969

Disclosure of the invention

Problems to be solved by the invention

Therefore, an object of the present invention is to provide a capacitor that can solve the above-described problems.

Means for solving the problem

[0015] The present invention is classified into first, second and third aspects regarding the arrangement of the DC bias applying electrodes. [0016] In a first aspect, a capacitor according to the present invention includes a capacitor body having a laminated structure including a plurality of dielectric layers. The capacitor body is used to apply a DC bias between a ground electrode provided along a specific dielectric layer and the ground electrode via the specific dielectric layer and between the ground electrode and the ground electrode. Capacitance is formed by positioning the DC bias applying electrode and the DC bias applying electrode between the grounding electrode and facing the grounding electrode through a specific dielectric layer. And a capacitance acquisition electrode provided as described above.

[0017] The capacitor further includes an earth terminal conductor film electrically connected to the earth electrode, a DC bias application terminal conductor film electrically connected to the DC bias application electrode, and a capacitor acquisition A first capacitance acquisition terminal conductor film electrically connected to the electrode, and the earth terminal conductor film, the DC bias application terminal conductor film, and the first capacitance acquisition terminal conductor film are formed on the capacitor body. Is provided on the outer surface.

[0018] In the first aspect, the capacitor according to the present invention further includes a second capacitance acquisition terminal conductor film provided on the outer surface of the capacitor body and electrically connected to the ground electrode. It is preferable. In this case, preferably, the capacitor main body has a rectangular parallelepiped shape having four side surfaces extending in the stacking direction, the ground terminal conductor film is provided on the first side surface, and the DC bias applying terminal conductor film is the first side surface. The first capacitance acquisition terminal conductor film is provided on the second side surface opposite to the first side surface, and the second capacitance acquisition is provided on the third side surface adjacent to the first and second side surfaces. The terminal conductor film for use is provided on the fourth side surface facing the third side surface.

[0019] In the capacitor according to the first aspect, at least the dielectric layer positioned between the grounding electrode and the DC bias applying electrode has a large DC bias dependency of the dielectric characteristics and also has a material force. I prefer that.

[0020] In the capacitor according to the first aspect, the capacitor main body may include a plurality of sets of grounding electrodes, DC noise application electrodes, and capacitance acquisition electrodes.

[0021] In a second aspect, a capacitor according to the present invention includes a capacitor body having a laminated structure including a plurality of dielectric layers. The capacitor body is provided with first and second capacitors provided to form a capacitance by facing each other through a specific dielectric layer. First and second direct current biases used to apply a DC bias to the capacitance forming region of the dielectric layer located between the first and second capacitance acquisition electrodes and the first and second capacitance acquisition electrodes. And an application electrode. The first DC bias applying electrode is provided on the same main surface as the main surface of the dielectric layer provided with the first capacitance acquisition electrode, and the second DC bias applying electrode is 2 is provided on the same main surface as the main surface of the dielectric layer provided with the capacitance acquisition electrode.

[0022] The capacitor further includes first and second DC bias applying terminal conductor films electrically connected to the first and second DC bias applying electrodes, respectively. First and second capacitance acquisition terminal conductor films electrically connected to the two capacitance acquisition electrodes, respectively, and the first and second DC bias applying terminal conductor films and the first and second The second capacitor acquisition terminal conductor film is provided on the outer surface of the capacitor body.

[0023] In the second aspect, preferably, the side on which the first DC bias application electrode is located with respect to the first capacitance acquisition electrode is with respect to the second capacitance acquisition electrode. The side on which the second DC bias application electrode is located is the opposite side.

In the capacitor according to the second aspect, preferably, the capacitor body has a rectangular parallelepiped shape having four side surfaces extending in the stacking direction, and the first DC bias applying terminal conductor film is on the first side surface. The second DC bias applying terminal conductor film is provided on the second side surface facing the first side surface, and the first capacitance acquiring terminal conductor film is provided on the first and second side surfaces. The second capacitance acquisition terminal conductor film is provided on the fourth side surface opposite to the third side surface.

[0025] In the capacitor according to the second aspect, it is preferable that at least the dielectric layer constituting the capacitance forming region is made of a material having a large DC noise dependency of dielectric characteristics.

[0026] In the capacitor according to the second aspect, the capacitor body includes a plurality of sets of first capacitance acquisition electrodes, second capacitance acquisition electrodes, first DC bias application electrodes, and second direct currents. Including a bias application electrode.

[0027] In a third aspect, the capacitor according to the present invention includes a plurality of dielectric layers. A capacitor body having a laminated structure. The capacitor body includes first and second capacitance acquisition electrodes provided so as to form a capacitance by facing each other through a specific dielectric layer, and first and second capacitance acquisition electrodes. And first and second DC bias applying electrodes used for applying a DC bias to the capacitance forming region of the dielectric layer located between the electrodes. The first and second DC noise application electrodes are provided on the same main surface of the same dielectric layer sandwiched between the first and second capacitance acquisition electrodes.

[0028] The capacitor further includes first and second DC bias applying terminal conductor films electrically connected to the first and second DC bias applying electrodes, respectively, and first and second DC bias applying electrodes. First and second capacitance acquisition terminal conductor films electrically connected to the two capacitance acquisition electrodes, respectively, and the first and second DC bias applying terminal conductor films and the first and second The second capacitor acquisition terminal conductor film is provided on the outer surface of the capacitor body.

[0029] In the third aspect, regarding the position of the dielectric layer in the principal surface direction, the first and second DC bias applying electrodes may be provided so as not to overlap the capacitance forming region, or It may be provided so as to overlap the capacitor formation region.

[0030] Further, in the capacitor according to the third aspect, the first and second DC bias applying electrodes are both comb-shaped to form a plurality of parallel electrode fingers, and the first DC The electrode fingers provided for the bias applying electrode may be positioned so as to enter between the electrode fingers provided for the second DC bias applying electrode!

[0031] In the capacitor according to the third aspect, preferably, the capacitor main body has a rectangular parallelepiped shape having four side surfaces extending in the stacking direction, and the first DC bias applying terminal conductor film is on the first side surface. The second DC bias applying terminal conductor film is provided on the second side surface facing the first side surface, and the first capacitance acquiring terminal conductor film is provided on the first and second side surfaces. The second capacitance acquisition terminal conductor film is provided on the fourth side surface opposite to the third side surface.

[0032] In the capacitor according to the third aspect, it is preferable that at least the dielectric layer constituting the capacitance forming region is made of a material having a large DC noise dependency of dielectric characteristics. That's right.

[0033] In the capacitor according to the third aspect, the capacitor body includes a plurality of sets of first capacitance acquisition electrodes, second capacitance acquisition electrodes, first DC bias application electrodes, and second direct currents. Including a bias application electrode.

The invention's effect

[0034] According to the capacitor of the first aspect of the present invention, the grounding electrode is provided so as to face both the DC bias applying electrode and the capacitance acquiring electrode in common, and thereby It functions as an electrode for applying a DC bias in a pair with a bias application electrode, and also functions as an electrode for forming a capacitance in a pair with a capacitance acquisition electrode. In order to make the capacitance variable by providing the earth electrode with two functions in this way, at least three layers of electrodes such as the earth electrode, the DC bias application electrode, and the capacitance acquisition electrode in the capacitor body, In addition, at least two dielectric layers are required as the dielectric layer separating the electrodes. Therefore, it is possible to advantageously reduce the size of the capacitor.

[0035] In addition, in the first aspect, in the capacitor body, since no capacitance acquisition electrode is interposed between the DC bias applying electrode and the ground electrode, the DC bias applying electrode and the grounding electrode are not provided. The distance between the electrodes can be easily reduced. If the distance between the DC bias application electrode and the ground electrode is reduced, the dielectric characteristics of the dielectric layer can be changed at a lower voltage. As a result, the capacitor can be operated at a lower voltage. It is possible to control the applied capacitance.

[0036] Further, in the first aspect, as described above, since the number of electrodes and dielectric layers required for the capacitor body in order to make the capacitance variable can be reduced, the volume capacity can be reduced. The amount becomes large, and it becomes easy to achieve high capacity while being small.

[0037] In the first aspect, the capacitor power grounding electrode according to the present invention is further provided with a second capacitor acquisition terminal conductor film electrically connected to the electrode, and the capacitor body has a rectangular parallelepiped shape having four side surfaces. Yes, a grounding terminal conductor film is provided on the first side surface, a DC bias applying terminal conductor film is provided on the second side surface, and the first capacitance acquisition terminal conductor film is on the third side surface. The second capacitance acquisition terminal conductor film is provided on the fourth side surface. Therefore, it is possible to employ an implementation state substantially similar to that of the variable capacitor described in Patent Documents 1 and 2.

[0038] In the capacitor according to the first aspect, if it is made of a material having a large DC bias dependency of the dielectric layer force dielectric property located at least between the grounding electrode and the DC bias applying electrode, The variable range of capacitance by bias can be made wider.

[0039] In the capacitor according to the first aspect, if the capacitor main body includes a plurality of sets of grounding electrodes, DC bias applying electrodes, and capacitance acquiring electrodes, the variable range of the capacitance due to the DC bias is increased. If it can be made wider, the acquired capacitance can be increased by force.

Next, according to the capacitor of the second aspect of the present invention, in order to form the capacitance, the first and second capacitance acquisition electrodes are required, and the capacitance can be made variable. The first and second DC bias application electrodes are required, but the first and second capacitance acquisition electrodes and the positions of the first and second DC bias application electrodes The first DC bias application electrode is provided on the same main surface as the main surface of the dielectric layer provided with the first capacitance acquisition electrode, and the second DC bias application electrode is provided with the second capacitance. It is characterized in that it is provided on the same main surface as the main surface of the dielectric layer provided with the acquisition electrode. Therefore, the minimum structure required to make the capacitance variable can be realized by one dielectric layer providing the capacitance formation region and two electrode layers sandwiching the dielectric layer. Compared to the conventional variable capacitance capacitor described in Patent Document 1 or 2, the size and size of the capacitor can be reduced.

[0041] Further, according to the capacitor according to the second aspect, since the grounded electrode does not exist between the first and second DC noise application electrodes, the first and second It is possible to suppress a decrease in the rate of change in capacitance due to a decrease in electric field strength that prevents the electric field applied to the capacitance forming region of the dielectric layer from being shielded by the DC bias applying electrode. Therefore, it is possible to control the capacitance provided by the capacitor at a lower voltage.

[0042] In the capacitor according to the second aspect, the first direct current is connected to the first capacitance acquisition electrode. Side force at which the current bias application electrode is located When the second capacitance acquisition electrode is opposite to the side at which the second direct current bias application electrode is located, the capacitance formation region of the dielectric layer The DC bias is applied in an oblique direction with respect to the thickness direction of the dielectric layer, and the first and second capacitance acquisition electrodes and the first and second DC bias applications are applied. This makes it possible to arrange four types of electrodes, such as electrodes, for use in a compact manner, contributing to the miniaturization of capacitors.

[0043] In the capacitor according to the second aspect, the capacitor body has a rectangular parallelepiped shape having four side surfaces, the first and second DC bias applying terminal conductor films, and the first and second capacitance acquisitions. The terminal conductor film for the first side, the second side facing the first side, the third side adjacent to the first and second side and the third side facing the third side, respectively. When provided on the side surface, a mounting state substantially the same as that of the variable capacitor described in Patent Documents 1 and 2 can be employed.

[0044] In the capacitor according to the second aspect, if at least the dielectric layer constituting the capacitance forming region is also configured with a material force having a large dependence on the DC noise of the dielectric characteristics, the capacitance variable range due to the DC bias Can be made wider.

[0045] In the capacitor according to the second aspect, the capacitor body includes a plurality of ^ a first capacitance acquisition electrodes, second capacitance acquisition electrodes, first DC bias application electrodes, and second direct current electrodes. When the current bias application electrode is included, if the variable range of the electrostatic capacity due to the DC bias can be made wider, the acquired electrostatic capacity can be increased.

Next, according to the capacitor of the third aspect of the present invention, in order to form the capacitance, the first and second capacitance acquisition electrodes are required, and the capacitance can be made variable. The first and second DC bias application electrodes are required, but the first and second capacitance acquisition electrodes and the positions of the first and second DC bias application electrodes The first and second DC bias applying electrodes are provided on the same main surface of the same dielectric layer sandwiched between the first and second capacitance acquiring electrodes. Therefore, the minimum structure necessary for making the capacitance variable can be realized by two dielectric layers providing a capacitance forming region and three electrode layers sandwiching each dielectric layer. Therefore, compared to the conventional variable capacitance capacitor described in Patent Document 1 or 2 described above Thus, it is possible to reduce the size and increase the capacity.

[0047] Further, according to the capacitor according to the third aspect, since the grounded electrode does not exist between the first and second DC noise applying electrodes, the first and second It is possible to suppress a decrease in the rate of change in capacitance due to a decrease in electric field strength that prevents the electric field applied to the capacitance forming region of the dielectric layer from being shielded by the DC bias applying electrode. Therefore, it is possible to control the capacitance provided by the capacitor at a lower voltage.

[0048] In the capacitor according to the third aspect, the first and second DC bias applying electrodes are provided so as not to overlap the capacitance forming region with respect to the position of the dielectric layer in the principal surface direction. In addition, since the first and second capacitance acquisition electrodes can be arranged so as not to sandwich the DC bias application electrode, the capacitance characteristics can be stabilized.

[0049] On the other hand, in the capacitor according to the third aspect, when the first and second DC bias applying electrodes are provided so as to overlap the capacitance forming region with respect to the position in the principal surface direction of the dielectric layer, The distance between the first and second DC bias application electrodes can be shortened. As a result, even when a relatively low voltage is applied as the DC bias, the effect of capacitance change can be obtained. .

[0050] In the capacitor according to the third aspect, both the first and second DC bias application electrode forces have a comb-like shape forming a plurality of parallel electrode fingers, and the first DC noise application Each electrode finger force provided for the electrode for electrode When the electrode finger provided for the second DC bias application electrode is positioned so as to enter between the electrodes, the distance between the first and second DC bias application electrodes is shortened. In addition, the opposing area of the first and second DC bias application electrodes can be increased, and the effect of capacitance change can be obtained even when a relatively low voltage is applied as the DC bias.

[0051] In the capacitor according to the third aspect, the capacitor body has a rectangular parallelepiped shape having four side surfaces, the first and second DC bias applying terminal conductor films, and the first and second capacitance acquisitions. The terminal conductor film for the first side, the second side facing the first side, the third side adjacent to the first and second side and the third side facing the third side, respectively. When provided on the side, a variable capacitor as described in Patent Documents 1 and 2 A substantially similar mounting state can be adopted.

[0052] In the capacitor according to the third aspect, if at least the dielectric layer constituting the capacitance forming region is also configured with a material force having a large DC noise dependency of the dielectric characteristics, the capacitance variable range due to the DC bias Can be made wider.

[0053] In the capacitor according to the third aspect, the capacitor body includes a plurality of ^ a first capacitance acquisition electrodes, second capacitance acquisition electrodes, first DC bias application electrodes, and second direct current electrodes. When the current bias application electrode is included, if the variable range of the electrostatic capacity due to the DC bias can be made wider, the acquired electrostatic capacity can be increased. Brief Description of Drawings

FIG. 1 is a front view showing a capacitor 21 according to a first embodiment of the present invention. FIG. 1 (a) is a front view showing the capacitor 21 with a cross section in the stacking direction of a dielectric layer 22. (B) to (d) are plan views showing the capacitor 21 with a cross section extending in the main surface direction of the dielectric layer 22, and show different cross sections.

FIG. 2 is an equivalent circuit diagram in a state where a DC bias is applied to the capacitor 21 shown in FIG.

[FIG. 3] The rate of change in capacity for each of sample 1 as an example and sample 2 as a comparative example, obtained in Example 1 for confirming the effect of the first embodiment! It is a figure which compares and shows.

FIG. 4 is a view corresponding to FIG. 1 (a), showing a capacitor 41 according to a second embodiment of the present invention.

FIG. 5 is a view corresponding to FIG. 1 (a), showing a capacitor 51 according to a third embodiment of the present invention.

FIG. 6 is a diagram for explaining a capacitor 21a according to a first modification corresponding to the first embodiment of the present invention. FIG. 6 (a) is a cross section of the capacitor 21a facing in the stacking direction of the dielectric layer 22. FIGS. 4B to 4D are plan views showing the capacitor 21a with a cross section extending in the direction of the main surface of the dielectric layer 22 and showing different cross sections.

FIG. 7 is an equivalent circuit diagram in which a DC bias is applied to the capacitor 21a shown in FIG. [8] FIG. 8 is a view corresponding to FIG. 4, showing a capacitor 41a according to a second modification corresponding to the second embodiment of the present invention.

[9] FIG. 9 is a diagram corresponding to FIG. 5, showing a capacitor 51a according to a third modification corresponding to the third embodiment of the present invention.

FIG. 10 is a front view showing a capacitor 121 according to a fourth embodiment of the present invention, in which (a) is a front view showing the capacitor 121 with a cross section in the stacking direction of the dielectric layer 122; b) to (d) are plan views showing the capacitor 121 with a cross section extending in the direction of the main surface of the dielectric layer 122, showing different cross sections.

FIG. 11 is an equivalent circuit diagram in a state where a DC noise is applied to the capacitor 121 shown in FIG.

圆 12] V and T for each of the sample 101 as an example and the sample 102 as a comparative example, which were obtained in Experimental Example 3 conducted to confirm the effect of the fourth embodiment of the present invention. It is a figure which compares and shows a capacity | capacitance change rate.

FIG. 13 is a view corresponding to FIG. 10 (a), showing a capacitor 141 according to a fifth embodiment of the present invention.

FIG. 14 is a view corresponding to FIG. 10 (a), showing a capacitor 151 according to a sixth embodiment of the present invention.

FIG. 15 is a front view showing a capacitor 221 according to a seventh embodiment of the present invention, in which (a) is a front view showing the capacitor 221 with a cross section in the stacking direction of the dielectric layer 222; b) to (d) are plan views showing the capacitor 221 with a cross section extending in the direction of the principal surface of the dielectric layer 222, showing different cross sections.

FIG. 16 is an equivalent circuit diagram in a state where a DC noise is applied to the capacitor 221 shown in FIG.

FIG. 17 shows a comparison of capacity change rates for each of sample 201 as an example and sample 202 as a comparative example obtained in Experimental Example 5 performed to confirm the effect of the seventh embodiment. FIG.

FIG. 18 is a view corresponding to FIG. 15 (c), showing a capacitor 221 a according to an eighth embodiment of the present invention. FIG. 19 is a view corresponding to FIG. 15, showing a capacitor 221b according to a ninth embodiment of the present invention.

FIG. 20 shows a capacitor 221c according to a tenth embodiment of the present invention, in which (a) and (b) correspond to FIGS. 15 (a) and (c), respectively.

FIG. 21 is a diagram corresponding to FIG. 15 and showing a capacitor 221d according to an eleventh embodiment of the present invention.

FIG. 22 is a view corresponding to FIG. 15 (a), showing a capacitor 241 according to a twelfth embodiment of the present invention.

FIG. 23 is a view corresponding to FIG. 15 (a), showing a capacitor 251 according to a thirteenth embodiment of the present invention.

FIG. 24 is a view corresponding to FIG. 1 (a), showing a conventional capacitor 1 of interest to the present invention.

FIG. 25 is a plan view showing the capacitor 1 shown in FIG. 24 with a cross section extending in the principal surface direction of the dielectric layer 2 and showing different cross sections.

FIG. 26 is a view corresponding to FIG. 1 (a) showing another conventional capacitor la of interest to the present invention.

Explanation of symbols

21, 41, 51, 121, 141, 151, 221, 221a, 221b, 221c, 221d, 241, 251 capacitors

22. 122, 222 Dielectric layer

23. 123, 223 Capacitor body

24 Grounding electrode

25, 127, 128, 227, 228 DC bias application electrode

26, 124, 125, 224, 225 Capacitance acquisition electrode

27, 129, 229 First aspect

28, 130, 230 Second side

29, 131, 231 Third side

30, 132, 232 Fourth aspect 31 Grounding terminal conductor film

32, 133, 134, 233, 234 DC bias application terminal conductor film

33, 135, 235 First capacitor acquisition terminal conductor film

34. 136, 236 Second capacitor acquisition terminal conductor film

37. 137, 237 DC noise

238, 239 electrode fingers

BEST MODE FOR CARRYING OUT THE INVENTION

[0056] (Embodiment according to the first aspect)

FIG. 1 and FIG. 2 are for explaining a capacitor 21 according to the first embodiment of the present invention. In FIG. 1, (a) is a view corresponding to FIG. 24 or FIG. 26 described above, and is a front view showing the capacitor 21 with a cross section facing the stacking direction of the dielectric layer 22, (b) to ( d) is a view corresponding to FIG. 25 described above, and is a plan view showing the capacitor 21 with a cross section extending in the principal surface direction of the dielectric layer 22. FIG. 2 is an equivalent circuit diagram in a state where a DC bias is applied to the capacitor 21.

As shown in FIG. 1 (a), the capacitor 21 includes a capacitor body 23 having a multilayer structure including a plurality of dielectric layers 22. The capacitor body 23 is disposed between the ground electrode 24 provided along the specific dielectric layer 22 and the ground electrode 24 through the specific dielectric layer 22 and facing the ground electrode 24. The DC bias application electrode 25 is used to apply a DC bias, and the DC bias application electrode 25 is sandwiched between the ground electrode 24 and grounded via a specific dielectric layer 22. And a capacitance acquisition electrode 26 provided so as to form a capacitance by facing the electrode 24.

[0058] The capacitor body 23 has a rectangular parallelepiped shape having four side surfaces 27 to 30 extending in the stacking direction, as well shown in FIGS. 1 (b) to (d). On the first side surface 27, a grounding terminal conductor film 31 is provided. A DC bias applying terminal conductor film 32 is provided on the second side face 28 facing the first side face 27. On the third side surface 29 adjacent to the first and second side surfaces 27 and 28, a first capacitance acquisition terminal conductor film 33 is provided. On the fourth side face 30 facing the third side face 29, the second capacitance acquisition terminal conductor film 34 is provided. [0059] FIG. 1 (b) shows a cross section through which the capacitance acquisition electrode 26 passes. The capacitance acquisition electrode 26 is pulled out to the third side surface 29, where it is electrically connected to the first capacitance acquisition terminal conductor film 33.

FIG. 1 (c) shows a cross section through which the DC bias applying electrode 25 passes. The DC bias applying electrode 25 is drawn out to the second side face 28 and is electrically connected to the DC bias applying terminal conductor film 32 here.

[0061] FIG. 1 (d) shows a cross section through which the ground electrode 24 passes. The grounding electrode 24 is pulled out to the first side surface 27 and also to the fourth side surface 30. The grounding electrode 24 is electrically connected to the grounding terminal conductor film 31 on the first side surface 27, and is connected to the second capacitance acquisition terminal conductor film 34 on the fourth side surface 30. Electrically connected.

In the capacitor 21 having the above-described configuration, as well shown in FIG. 2, the capacitance formed between the grounding electrode 24 and the capacitance acquiring electrode 26 is the first and The second capacitor acquisition terminal conductor films 33 and 34 are taken out. A predetermined circuit (not shown) is electrically connected to the first and second capacitor acquisition terminal conductor films 33 and 34. At this time, if a DC bias 37 is applied between the grounding electrode 24 and the DC bias applying electrode 25 through the grounding terminal conductor film 31 and the DC noise applying terminal conductor film 32, The dielectric characteristics such as the dielectric constant of the dielectric layer 22 located between the electrode 24 and the DC bias applying electrode 25 change. Therefore, the dielectric characteristics of the part of the dielectric layer 22 located between the ground electrode 24 and the capacitance acquisition electrode 26 change as described above. As a result, the first and second dielectric layers 22 change. It is possible to change the capacitance taken out through the terminal conductor films 33 and 3 4 for acquiring the capacitance of 2.

[0063] In order to further increase the capacitance change range described above, the dielectric layer 22, particularly the dielectric layer 22 positioned between the grounding electrode 24 and the DC bias applying electrode 25, has a dielectric property. It is preferable that a material force having a large DC bias dependency is also configured. Thus, as a material whose dielectric characteristics have a large DC bias dependency, for example, lOOBa (Ti Zr) 0

1.006 0.97 0.03

-2. 5GdO-2. 5MgO-0. 5MnO— 1. OSiO force ^.

3 3/2 2

[0064] Next, Experimental Example 1 performed to confirm the effect of the first embodiment will be described. To do.

In Experimental Example 1, a sample 1 having a structure substantially similar to that of the capacitor 21 shown in FIG. 1 was produced as Sample 1 according to the example within the scope of the present invention. As Sample 2 according to the comparative example, a sample having a structure substantially similar to that of the capacitor 1 shown in FIG. 24 was prepared. In each of these samples 1 and 2, a BaTiO-based high dielectric constant ceramic material is used as the dielectric constituting the dielectric layer, and the dielectric layer positioned between the electrodes is used.

Three

The thickness of the electric layer was 2 m. The electrode was mainly composed of nickel and had a thickness of 1 μm. The external dimensions of the capacitor body were 3.2 mm X l. 6 mm X O. 4 mm.

[0066] For the capacitors according to Samples 1 and 2 as described above, the rate of change in capacitance when several DC noises in the range of 0 to 36 V were applied. The result is shown in Figure 3.

[0067] From FIG. 3, it can be seen that the capacitance decreased by about 80% or more in the sample 1, while it decreased by about 25% in the sample 2. This is because, in sample 2, three dielectric layers are interposed between the pair of DC bias application electrodes, whereas in sample 1, one electrode and a capacitor for applying a DC bias are obtained. This is because one electrode for this purpose is shared by a ground electrode, and only one dielectric layer is interposed between the pair of DC bias application electrodes. As a result, according to Sample 1, the required capacity change rate can be obtained at a lower voltage.

[0068] In Experimental Example 1 described above, a specific BaTiO is used as the dielectric constituting the dielectric layer.

Force using 3 series high-permittivity ceramic material As this ceramic material, if the material has a higher DC dependency on the DC characteristics, a capacitor with a wider capacitance change range with respect to DC bias can be obtained. Is confirmed.

[0069] FIGS. 4 and 5 are diagrams corresponding to FIG. 1 (a), showing capacitors 41 and 51 according to the second and third embodiments of the present invention, respectively. In FIG. 4 and FIG. 5, elements corresponding to those shown in FIG. 1 (a) are given the same reference numerals, and redundant explanations are omitted.

[0070] Capacitors 41 and 51 according to the second and third embodiments include a plurality of sets of grounding electrodes 24, DC bias application electrodes 25, and capacitance acquisition capacitors in the capacitor body 23. The electrode 26 is formed and is characterized by! /

[0071] More specifically, in the capacitor 41 shown in FIG. 4, a plurality of ^ & ground electrodes 24, a DC bias applying electrode 25, and a capacitance acquiring electrode 26 are arranged from above with a capacitance acquiring electrode 26, The DC bias application electrode 25, the ground electrode 24, the capacitance acquisition electrode 26,... Are repeatedly arranged in the order of several times.

In the capacitor 51 shown in FIG. 5, the capacitance acquisition electrode 26, the DC bias application electrode 25, the ground electrode 24, the DC bias application electrode 25, the capacitance acquisition electrode 26,. Repeated multiple times in the same order.

In other words, in the capacitor 41 shown in FIG. 4, the arrangement of the capacitance acquisition electrode 26, the DC bias application electrode 25, and the ground electrode 24 in the capacitor 21 shown in FIG. This set is repeated several times. In the capacitor 51 shown in FIG. 5, the grounding electrode 24 is shared between adjacent pairs, and the DC bias applying electrode 25 is disposed in every two layers of the dielectric layer 22.

[0074] When comparing the capacitor main body 23 of the capacitor 41 shown in FIG. 4 and the capacitor main body 23 of the capacitor 51 shown in FIG. The reason is that the number of electrodes 24 to 26 to be different is also a result, and the difference in the thickness direction shown in the figure is not particularly meaningful.

[0075] Next, as in the case of the capacitors 41 and 51, when the capacitor body 23 includes a plurality of pairs of ground electrodes 24, DC bias application electrodes 25, and capacitance acquisition electrodes 26, this An experimental example 2 performed to confirm that a wider capacitance change range can be obtained with the capacitor according to the invention will be described.

[0076] In this Experimental Example 2, as shown in Table 1, the force that produced the capacitors according to each of Samples 11 to 13, the material and thickness of the dielectric layer and the material and thickness of the electrode in each capacitor were as follows: It was the same as the above-mentioned experimental example 1. In addition, the external dimensions of the capacitors according to each of Samples 11 to 13 were set to 3.2 mm X 1 .6 mm X 1 .6 mm.

For Sample 11, the electrode arrangement structure shown in FIG. 24 was adopted, and the number of layers of all electrodes including the DC bias application electrode and the capacitance acquisition electrode was set to 500. For Sample 12, the electrode arrangement structure shown in FIG. 26 was adopted, and the number of stacked layers of all the electrodes including the DC bias application electrode and the capacitance acquisition electrode was set to 500.

For Sample 13, the electrode arrangement structure shown in FIG. 4 was adopted, and the number of layers of all electrodes including the ground electrode, the DC bias application electrode, and the capacitance acquisition electrode was set to 501.

[0080] Table 1 shows the capacitance change range when the DC bias is changed in the range of 0 to 36 V for these samples 11 to 13.

[0081] [Table 1]

[0082] As shown in Table 1, when comparing Sample 13 within the scope of the present invention with Samples 11 and 12 outside the scope of the present invention, the capacitor dimensions were the same and the number of stacked electrodes was When they are approximately the same, according to the capacitor of the present invention, a larger capacity can be obtained and the variable width of the capacity can be made wider.

[0083] In Sample 11, since the capacitance acquisition electrode is sandwiched between the DC bias application electrodes, a larger maximum capacitance can be obtained compared to Sample 12, but the variable width of the capacitance is narrow.

[0084] On the other hand, Sample 12 has a structure in which the DC bias application electrode is sandwiched between the capacitance acquisition electrodes, so that a large capacitance cannot be obtained, and the maximum capacitance is 13. Only 7 F.

[0085] On the other hand, sample 13 has a larger maximum capacity and a larger capacity variable width than sample 11.

As described above, the first to third embodiments according to the first aspect of the present invention have been described with reference to FIGS. 1 to 5. However, various other modifications are possible within the scope of the present invention. It is possible.

For example, in the first to third embodiments, it is electrically connected to the ground electrode 24. As the terminal conductor film, in addition to the ground terminal conductor film 31, the second capacitor acquisition terminal conductor film 34 is formed. However, such a second capacitor acquisition terminal conductor film may be omitted. In this case, even if the ground terminal conductor film 31 is provided at the position where the second capacitance acquisition terminal conductor film 34 is provided, the second position force provided by the ground terminal conductor film 31 shown in FIG. The capacitor acquisition terminal conductor film 34 may be provided so as to continuously extend to the position where the capacitor acquisition terminal conductor film 34 is provided.

[0088] In the first to third embodiments, the grounding electrode 24, the DC bias applying electrode 25, and the capacitance acquiring electrode 26 are all formed inside the capacitor body 23. For example, for the capacitor 21 shown in FIG. 1 (a), the ground electrode 24 and the Z or capacitance acquisition electrode 26 are formed on the outer surface of the capacitor body 23. It will be.

[0089] Next, although not within the scope of the present invention, each modification of the first, second, and third embodiments described above, that is, the first, second, and third modifications. explain. In the description of the first to third modifications, the same reference numerals as those used in the description of the first to third embodiments are used for the corresponding elements.

FIG. 6 and FIG. 7 are for explaining a capacitor 21a according to a first modification corresponding to the first embodiment described above. In FIG. 6, (a) is a view corresponding to FIG. 1 (a) described above, and is a front view showing the capacitor 21a with a cross section in the stacking direction of the dielectric layer 22, and (b) to ( d) is a view corresponding to FIGS. 1B to 1D described above, and is a plan view showing the capacitor 21a with a cross section extending in the main surface direction of the dielectric layer 22. FIG. FIG. 7 corresponds to FIG. 2 described above.

As shown in FIG. 6 (a), the capacitor 21a includes a capacitor body 23 having a multilayer structure composed of a plurality of dielectric layers 22. The capacitor body 23 includes a grounding electrode 24 provided along a specific dielectric layer 22 and a DC bias applying electrode provided at a position facing the grounding electrode 24 through the specific dielectric layer 22. 25, located between the grounding electrode 24 and the DC bias applying electrode 25 and facing the grounding electrode 24 through a specific dielectric layer 22 so as to form a capacitance. And an electrode 26 for capacitance acquisition. The capacitor main body 23 has a rectangular parallelepiped shape having four side surfaces 27 to 30 extending in the stacking direction, as well shown in FIGS. 6 (b) to (d). On the first side surface 27, a grounding terminal conductor film 31 is provided. A DC bias applying terminal conductor film 32 is provided on the second side face 28 facing the first side face 27. On the third side surface 29 adjacent to the first and second side surfaces 27 and 28, a first capacitance acquisition terminal conductor film 33 is provided. On the fourth side face 30 facing the third side face 29, the second capacitance acquisition terminal conductor film 34 is provided.

FIG. 6 (b) shows a cross section through which the DC bias applying electrode 25 passes. The DC bias applying electrode 25 is drawn out to the second side face 28 and is electrically connected to the DC bias applying terminal conductor film 32 here.

FIG. 6 (c) shows a cross section through which the capacitance acquisition electrode 26 passes. The capacitance acquisition electrode 26 is pulled out to the third side surface 29, where it is electrically connected to the first capacitance acquisition terminal conductor film 33.

[0095] FIG. 6 (d) shows a cross-section through which the grounding electrode 24 passes! The grounding electrode 24 is pulled out to the first side surface 27 and also to the fourth side surface 30. The grounding electrode 24 is electrically connected to the grounding terminal conductor film 31 on the first side surface 27, and is connected to the second capacitance acquisition terminal conductor film 34 on the fourth side surface 30. Electrically connected.

In the capacitor 21a having the above-described configuration, as well shown in FIG. 7, the capacitance formed between the grounding electrode 24 and the capacitance acquiring electrode 26 is the first and The second capacitor acquisition terminal conductor films 33 and 34 are taken out. A predetermined circuit (not shown) is electrically connected to the first and second capacitor acquisition terminal conductor films 33 and 34. At this time, if a DC bias 37 is applied between the grounding electrode 24 and the DC bias applying electrode 25 through the grounding terminal conductor film 31 and the DC noise applying terminal conductor film 32, The dielectric characteristics such as the dielectric constant of the dielectric layer 22 located between the electrode 24 and the DC bias applying electrode 25 change. Therefore, the dielectric characteristics of the dielectric layer 22 located between the ground electrode 24 and the capacitance acquisition electrode 26 change as described above. As a result, the first and second capacitance acquisition terminal conductors change. The capacitance extracted through the membranes 33 and 34 can be varied. Also in this modified example, in order to further increase the above-described capacitance change range, the dielectric layer 22, particularly the dielectric located between the ground electrode 24 and the capacitance acquisition electrode 26 is used. It is preferable that the layer 22 has a large DC noise dependency of the dielectric properties! / And material strength.

In the first modification, the DC bias applying electrode 25 is not sandwiched between the grounding electrode 24 and the capacitance acquiring electrode 26, so that in the case of the first embodiment described above. In comparison, the capacity characteristic can be made more stable.

[0099] FIGS. 8 and 9 correspond to FIGS. 4 and 5, respectively showing capacitors 41a and 51a according to the second and third modifications corresponding to the second and third embodiments described above, respectively. FIG.

[0100] The capacitors 41a and 51a according to the second and third modifications are the same as in the second and third embodiments. In the capacitor body 23, a plurality of sets of grounding electrodes 24, DC bias applying electrodes 25 are provided. In addition, the capacitor acquisition electrode 26 is formed.

[0101] More specifically, in the capacitor 41a shown in FIG. 8, a plurality of ground electrodes 24, a DC bias application electrode 25, and a capacitance acquisition electrode 26 are arranged from the top with a DC bias application electrode 25 and a capacitance. The acquisition electrode 26, the ground electrode 24, the DC bias application electrode 25,... Are repeatedly arranged in the order of V.

[0102] In the capacitor 51a shown in FIG. 9, the DC bias application electrode 25, the capacitance acquisition electrode 26, the grounding electrode 24, the capacitance acquisition electrode 26, the DC bias application electrode 25,... Repeated several times in order and placed.

In other words, in the capacitor 41a shown in FIG. 8, the arrangement of the DC bias applying electrode 25, the capacitance acquiring electrode 26 and the grounding electrode 24 in the capacitor 21a shown in FIG. This set is repeated several times. In the capacitor 51a shown in FIG. 9, the grounding electrode 24 is shared between adjacent sets, and the capacitance acquisition electrode 26 is arranged for every two layers of the dielectric layer 22.

[0104] Like the capacitors 41a and 51a, the capacitor main body 23 forces multiple sets of grounding electrodes 24, DC bias application electrodes 25, and capacitance acquisition electrodes 26 provide a wider capacity change range. It is done. (Embodiment according to the second aspect)

FIG. 10 and FIG. 11 are for explaining a capacitor 121 according to the fourth embodiment of the present invention. In FIG. 10, (a) is a view corresponding to FIG. 24 or FIG. 26 described above, and is a front view showing the capacitor 121 with a cross section in the stacking direction of the dielectric layer 122, and (b) and ( c) is a view corresponding to FIG. 25 described above, and is a plan view showing the capacitor 121 with a cross section extending in the principal surface direction of the dielectric layer 122. FIG. FIG. 11 is an equivalent circuit diagram in a state where a DC bias is applied to the capacitor 121.

As shown in FIG. 10 (a), the capacitor 121 includes a capacitor main body 123 having a laminated structure including a plurality of dielectric layers 122. The capacitor body 123 includes first and second capacitance acquisition electrodes 124 and 125 provided to form a capacitance by facing each other through a specific dielectric layer 122, and the first and second capacitors. First and second DC bias applying electrodes 127 and 128 used to apply a direct current bias to the capacitance forming region 126 of the dielectric layer 122 located between the capacitance acquiring electrodes 124 and 125. Get ready!

The first DC bias applying electrode 127 is provided on the same main surface as the main surface of the dielectric layer 122 provided with the first capacitance acquiring electrode 124. On the other hand, the second DC bias application electrode 128 is provided on the same main surface as the main surface of the dielectric layer 122 provided with the second capacitance acquisition electrode 125.

In addition, the side on which the first DC bias application electrode 127 is positioned with respect to the first capacitance acquisition electrode 124 is the second DC bias application with respect to the second capacitance acquisition electrode 125. The side on which the working electrode 128 is located is the opposite side. Therefore, the DC bias applied by the first and second DC bias applying electrodes 127 and 128 is directed obliquely with respect to the thickness direction of the dielectric layer 122.

[0108] The capacitor body 123 has a rectangular parallelepiped shape having four side surfaces 129 to 132 extending in the stacking direction, as well shown in FIGS. 10 (b) and 10 (c). On the first side surface 129, a first DC bias applying terminal conductor film 133 is provided. On the second side surface 130 facing the first side surface 129, a second DC bias applying terminal conductor film 134 is provided. On the third side 131 adjacent to the first and second sides 129 and 130, the first capacity An obtaining terminal conductor film 135 is provided. On the fourth side surface 132 facing the third side surface 131, a second capacitance acquisition terminal conductor film 136 is provided.

FIG. 10B shows a cross section through which the first capacitance acquisition electrode 124 and the first DC bias application electrode 127 pass. The first capacitance acquisition electrode 124 is drawn out to the third side surface 131, where it is electrically connected to the first capacitance acquisition terminal conductor film 135. The first DC bias applying electrode 127 is drawn out to the first side surface 129, and is electrically connected to the first DC bias applying terminal conductor film 133 here.

FIG. 10 (c) shows a cross section through which the second capacitance acquisition electrode 125 and the second DC bias application electrode 128 pass. The second capacitance acquisition electrode 125 is drawn out to the fourth side surface 132, where it is electrically connected to the second capacitance acquisition terminal conductor film 136. The second DC bias applying electrode 128 is drawn out to the second side face 130 and is electrically connected to the second DC bias applying terminal conductor film 134 here.

In the capacitor 121 having the above-described configuration, as well shown in FIG. 11, the capacitance formed between the first and second capacitance acquisition electrodes 124 and 125 is The first and second capacitance acquisition terminal conductor films 135 and 136 are taken out. A predetermined circuit (not shown) is electrically connected to the first and second capacitance acquisition terminal conductor films 135 and 136. At this time, if a DC bias 137 is applied between the first and second DC bias application electrodes 127 and 128 through the first and second DC noise application terminal conductor films 133 and 134, the first The dielectric property of the capacitor formation region 126 (see FIG. 10 (a)) of the dielectric layer 122 located between the first and second capacitance acquisition electrodes 124 and 125 changes, and as a result, the first And the electrostatic capacitance taken out through the second capacitance acquisition terminal conductor films 135 and 136 can be changed.

[0112] In order to further increase the above-described capacitance variation range, the dielectric layer 122, particularly the capacitance forming region 126, between the first and second DC bias applying electrodes 127 and 128 is formed. It is preferable that the dielectric layer 122 located in the region is made of a material having a large DC bias dependency of dielectric characteristics. In this way, for example, lOOBa (Ti Zr) 0 — 2.5 GdO — 2.5 MgO— 0.5

1.006 0.97 0.03 3 3/2

MnO- 1. There is OSiO. [0113] Next, Experimental Example 3 performed to confirm the effect of the fourth embodiment will be described.

[0114] In Experimental Example 3, a sample 101 having a structure substantially similar to that of the capacitor 121 shown in Fig. 10 was produced as the sample 101 according to the example within the scope of the present invention. As the sample 102 according to the comparative example, a sample having a structure substantially similar to that of the capacitor 1 shown in FIG. In each of these samples 101 and 102, a BaTiO-based high dielectric constant ceramic material was used as the dielectric constituting the dielectric layer, and the electrode

Three

The thickness of the dielectric layer located at 2 is 2 m. The electrode was mainly composed of nickel and 1 μm thick. The external dimensions of the capacitor body were 3.2 mm X 1.6 mm X 0.4 mm.

[0115] For the capacitors according to Samples 101 and 102 as described above, the rate of change in capacitance when several DC biases in the range of 0 to 36 V were applied. The result is shown in Figure 12!

[0116] Normally, when a DC bias is applied to a dielectric, the capacitance change rate becomes constant at a certain applied voltage or higher. In FIG. 12, the capacity change rate of the sample 101 is shown only up to the case where the DC bias voltage is 12V, but it has been confirmed that it is constant at a DC bias voltage of 12V or more. Therefore, as shown in FIG. 12, in sample 101, the DC bias voltage at which the rate of change in capacitance is constant is about 1Z3 of sample 102. In Sample 102, three dielectric layers are interposed between the pair of DC bias application electrodes, whereas in Sample 101, the DC bias application electrode and the capacitance acquisition electrode are the same. By providing it on one surface, only one dielectric layer is interposed between the pair of DC bias application electrodes, and the electrode spacing is reduced to 1Z3 compared to Sample 102, and as a result, This is because the required capacity change rate can be obtained at a lower voltage.

[0117] In Sample 101, since there is no electrode (conductor layer) that blocks the electric field between the pair of DC bias application electrodes, a decrease in the capacity change rate due to a decrease in the electric field strength is suppressed, and As a result, a large capacity change rate is obtained.

[0118] In Experimental Example 3, a specific BaTiO is used as the dielectric constituting the dielectric layer.

Force using 3 series high dielectric constant ceramic material It has been confirmed that a capacitor having a larger capacitance change range with respect to the DC bias can be obtained by using a material having a larger dependency on noise and using a material.

FIGS. 13 and 14 are diagrams corresponding to FIG. 10 (a), showing capacitors 141 and 151 according to the fifth and sixth embodiments of the present invention, respectively. In FIG. 13 and FIG. 14, elements corresponding to the elements shown in FIG. 10 (a) are denoted by the same reference numerals, and redundant descriptions are omitted.

[0120] The capacitors 141 and 151 according to the fifth and sixth embodiments include a plurality of sets of first capacitance acquisition electrodes 124, second capacitance acquisition electrodes 125, and first DC biases in the capacitor main body 123. An application electrode 127 and a second DC bias application electrode 128 are formed! /

In more detail, in the capacitor 141 shown in FIG. 13, the dielectric layer 122 and the second capacitance acquisition forming the first capacitance acquisition electrode 124 and the first DC bias application electrode 127. The dielectric layers 122 forming the working electrodes 125 and the second DC bias applying electrodes 128 are alternately arranged in the stacking direction.

In the capacitor 151 shown in FIG. 14, with respect to the stacking direction, from the top, the dielectric layer 122 forming the first capacitance acquisition electrode 124 and the first DC bias application electrode 127, and the second capacitance acquisition Dielectric layer 122 forming first electrode 125 and second DC bias applying electrode 128, dielectric layer 122 forming second capacitance acquisition electrode 125 and second DC bias applying electrode 128, first layer The capacitor acquisition electrode 124 and the first DC bias application electrode 127 are arranged in the same order as the dielectric layers 122,.

[0123] Next, like the capacitors 141 and 151, the capacitor body 123 force includes a plurality of sets of first capacitance acquisition electrodes 124, second capacitance acquisition electrodes 125, first DC bias application electrodes 127 and In the case where the second DC bias applying electrode 128 is provided, the capacitor according to the present invention increases the electrostatic capacity per unit volume, enables further miniaturization and higher capacity, and lowers the voltage. An experimental example 4 conducted to confirm that the capacitance can be controlled over a wider range will be described.

[0124] In Experimental Example 4, capacitors according to Sample 111 as an example within the scope of the present invention and Sample 112 as a comparative example outside the scope of the present invention were fabricated. The material and thickness of the dielectric layer and the material and thickness of the electrode in the capacitor were the same as in Experimental Example 3 above. In addition, the external dimensions of the capacitors according to Samples 111 and 112 in this experimental example were both 3.2 mm × l.6 mm × l.6 mm.

[0125] More specifically, for the sample 112, the electrode arrangement structure shown in FIG. 24 was adopted, and the number of layers of all electrodes including the DC bias application electrode and the capacitance acquisition electrode was 500. . On the other hand, for sample 111, the electrode arrangement structure shown in FIG. 13 was adopted, and the number of layers of all electrodes including the first and second capacitance acquisition electrodes and the first and second DC bias application electrodes Was set to 500.

[0126] For these samples 111 and 112, Table 2 shows the capacitance change range when the DC bias is changed in the range of 0 to 36V.

[0127] [Table 2]

[0128] As shown in Table 2, when comparing sample 111 within the scope of the present invention with sample 112 outside the scope of the present invention, the capacitor dimensions were the same and the number of stacked electrodes was the same. If so, according to the capacitor of the present invention, a larger capacity can be obtained and the variable width of the capacity can be made wider.

[0129] The force described above with reference to Figs. 10 to 14 for the fourth to sixth embodiments according to the second aspect of the present invention is within the scope of the present invention, and various other modifications are possible. It is.

[0130] For example, regarding the positional relationship between the capacitance acquisition electrode and the DC bias application electrode provided on the same plane, the first and second DC bias application electrodes that face each other are used. As long as the DC bias can be applied to the capacitance forming region of the dielectric layer located between the two capacitance acquisition electrodes, the positional relationship may be other than the positional relationship as in the illustrated embodiment.

[0131] The first and second DC bias applying terminal conductor films and the first and second About the position on the capacitor body where each terminal conductor film for capacitance acquisition is provided

The first and second capacitance acquisition electrodes and the first and second DC bias application electrodes described above can be arbitrarily changed.

In the fourth to sixth embodiments, the first and second capacitance acquisition electrodes 124 and 125 and the first and second DC bias application electrodes 127 and 128 are both capacitors. Force formed in the main body 123 If there is no concern about the problem of moisture resistance, if V, at least one pair of first capacitance acquisition electrode and first DC bias application electrode or second capacitance acquisition The electrode for application and the second DC bias application electrode may be formed on the outer surface of the capacitor body.

(Embodiment according to the third aspect)

15 and 16 illustrate a capacitor 221 according to the seventh embodiment of the present invention. 15, (a) is a view corresponding to FIG. 24 or FIG. 26 described above, and is a front view showing the capacitor 221 with a cross section in the stacking direction of the dielectric layer 222, and (b) to ( d) is a diagram corresponding to FIG. 25 described above, and is a plan view showing the capacitor 221 with a cross section extending in the principal surface direction of the dielectric layer 222. FIG. FIG. 16 is an equivalent circuit diagram in a state where a DC bias is applied to the capacitor 221.

As shown in FIG. 15 (a), the capacitor 221 includes a capacitor body 223 having a laminated structure including a plurality of dielectric layers 222. The capacitor body 223 includes first and second capacitance acquisition electrodes 224 and 225, which are provided so as to form a capacitance by facing each other through a specific dielectric layer 222, and the first and second capacitors. The first and second DC bias applying electrodes 2 27 and 228 used for applying a direct current bias to the capacitance forming region 226 of the dielectric layer 222 located between the two capacitance acquiring electrodes 224 and 225; With /!

[0134] The first and second DC bias applying electrodes 227 and 228 are disposed on the same main surface of the same dielectric layer 222 sandwiched between the first and second capacitance acquiring electrodes 224 and 225. Can be established. Therefore, the DC bias applied by the first and second DC bias applying electrodes 227 and 228 is directed toward the main surface of the dielectric layer 222. In this embodiment, two layers of dielectric are provided between the first and second capacitance acquisition electrodes 224 and 225. The layer 222 force is placed, and first and second DC bias applying electrodes 227 and 228 are formed along the interface between the two dielectric layers 222.

In FIG. 15 (c), the position where the second capacitance acquisition electrode 225 is provided is indicated by a broken line. As shown in the positional relationship between the second capacitance acquisition electrode 225 and the first and second DC bias application electrodes 227 and 228, the first and second DC bias application electrodes 227 and 228 Is provided so as not to overlap the capacitance forming region 226 (see FIG. 15A) with respect to the position of the dielectric layer 222 in the main surface direction. As a result, the first and second capacitance acquisition electrodes 224 and 225 can be prevented from sandwiching the DC bias application electrodes 227 and 228. As a result, the capacitance characteristics are stabilized. be able to.

It should be noted that the dielectric layer so that the first and second capacitance acquisition electrodes 224 and 225 and the first and second DC bias application electrodes 227 and 228 are affected by the positional relationship described above. When viewed in a cross section of 222 in the stacking direction, the first and second capacitance acquisition electrodes 224 and 225 appear on the same cross section as the first and second DC bias application electrodes 227 and 228. Absent. Therefore, Fig. 15 (a) shows the positional relationship in the stacking direction between the capacitance acquisition electrodes 224 and 225 and the DC bias application electrodes 227 and 228, which does not show the capacitor 221 with a single cross section. For the purpose of illustration, it should be understood that it is shown with multiple cross sections.

[0137] The capacitor main body 223 has a rectangular parallelepiped shape having four side surfaces 229 to 232 extending in the stacking direction, as well shown in FIGS. 15 (b) to (d). On the first side surface 229, a first DC bias applying terminal conductor film 233 is provided. On the second side surface 230 facing the first side surface 229, a second DC bias applying terminal conductor film 234 is provided. On the third side surface 231 adjacent to the first and second side surfaces 229 and 230, a first capacitance obtaining terminal conductor film 235 is provided. A second capacitance acquisition terminal conductor film 236 is provided on the fourth side surface 232 facing the third side surface 231.

FIG. 15 (b) shows a cross section through which the first capacitance acquisition electrode 224 passes. The first capacitor acquisition electrode 224 is drawn out to the third side surface 231, where it is electrically connected to the first capacitor acquisition terminal conductor film 235.

In Fig. 15 (c), the first and second DC bias applying electrodes 227 and 228 are disconnected. A face is shown. The first DC bias applying electrode 227 is drawn out to the first side face 229, and is electrically connected to the first DC bias applying terminal conductor film 233. The second DC bias applying electrode 228 is drawn out to the second side face 230 and is electrically connected to the second DC bias applying terminal conductor film 234 here.

FIG. 15 (d) shows a cross section through which the second capacitance acquisition electrode 225 passes. The second capacitor acquisition electrode 225 is pulled out to the fourth side surface 232, where it is electrically connected to the second capacitor acquisition terminal conductor film 236.

In the capacitor 221 having the above-described configuration, as well shown in FIG. 16, the capacitance formed between the first and second capacitance acquisition electrodes 224 and 225 is The first and second capacitance acquisition terminal conductor films 235 and 236 are taken out. A predetermined circuit (not shown) is electrically connected to the first and second capacitance acquisition terminal conductor films 235 and 236. At this time, if a DC bias 237 is applied between the first and second DC bias application electrodes 227 and 228 through the first and second DC noise application terminal conductor films 233 and 234, The dielectric property of the capacitance forming region 226 (see FIG. 15 (a)) of the dielectric layer 222 located between the first and second capacitance acquisition electrodes 224 and 225 changes, and as a result, the first The capacitance taken out through the second capacitance acquisition terminal conductor films 235 and 236 can be changed.

[0141] In order to further increase the capacitance variation range described above, the dielectric layer 222, particularly the dielectric layer 222 constituting the capacitance forming region 226, is made of a material whose dielectric characteristics have a large DC bias dependency. Preferably, it is configured. Thus, for example, lOOBa (Ti Zr) 0 — 2.5 GdO — 2.5 MgO

1.006 0.97 0.03 3 3/2

-0. 5MnO— 1. There is OSiO.

2

[0142] Next, Experimental Example 5 performed to confirm the effect of the seventh embodiment will be described.

In Experimental Example 5, a sample 201 having a structure substantially similar to that of the capacitor 221 shown in FIG. 15 was produced as the sample 201 according to the example within the scope of the present invention. As a sample 202 according to the comparative example, a sample 202 having a structure substantially similar to that of the capacitor 1 shown in FIG. In each of these samples 201 and 202, the dielectric BaTiO-based high dielectric constant ceramic material is used as the dielectric that composes the body layer.

Three

The thickness of the dielectric layer located at 2 is 2 m. The electrode was mainly composed of nickel and 1 μm thick. The external dimensions of the capacitor body were 3.2 mm X 1.6 mm X O. 4 mm.

[0144] With respect to the capacitors according to Samples 201 and 202 as described above, the rate of change in capacitance when several DC biases in the range of 0 to 36 V were applied. The result is shown in Figure 17!

[0145] Normally, when a DC bias is applied to a dielectric, the capacitance change rate becomes constant at a certain applied voltage or higher.

As shown in FIG. 17, in Sample 201, there is no electrode (conductor layer) that blocks the electric field between the pair of DC bias application electrodes, and therefore the rate of change in capacitance due to a decrease in electric field strength. As a result, a large capacity change rate is obtained as compared with the sample 202.

[0147] In Experimental Example 5, a specific BaTiO is used as the dielectric constituting the dielectric layer.

Force using 3 type high dielectric constant ceramic material If this material is used, the capacitor has a wider capacitance change range with respect to the DC bias if the material has a higher DC dependency on the dielectric characteristics. It has been confirmed.

FIG. 18 is a view corresponding to FIG. 15 (c), showing a capacitor 221 a according to the eighth embodiment of the present invention. In FIG. 18, elements corresponding to the elements shown in FIG. 15 (c) are denoted by the same reference numerals, and redundant description is omitted.

[0149] The capacitor 221a according to the eighth embodiment differs from the capacitor 221 according to the seventh embodiment in the manner of forming the DC noise application electrodes 227 and 228. In other words, the first and second DC bias applying electrodes 227 and 228 are formed on the main surface of the dielectric layer 222 so as to exert a force from the position of the capacitance acquisition electrode 225 indicated by a broken line in FIG. The position in the direction is characterized by being provided so as to overlap with the capacitance forming region 226 (see FIG. 15 (a)). By adopting such a configuration, the distance between the first and second DC bias applying electrodes 227 and 228 can be shortened compared to the capacitor 221 according to the seventh embodiment. Even if a lower voltage is applied, the effect of capacitance change can be obtained. FIG. 19 is a view corresponding to FIG. 15, showing a capacitor 221b according to the ninth embodiment of the present invention. In FIG. 19, elements corresponding to the elements shown in FIG. 15 are denoted by the same reference numerals, and redundant description is omitted.

[0151] The capacitor 221b according to the ninth embodiment is characterized by the formation of the first and second DC bias applying electrodes 227 and 228. In other words, the first and second DC bias applying electrodes 227 and 228 are formed so as to be positioned at the ends of the dielectric layer 222 in the longitudinal direction. Further, as shown in FIG. 19A, the first and second DC bias applying electrodes 227 and 228 are provided so as not to overlap the capacitance forming region 226. Therefore, according to the ninth embodiment, the first and second capacitance acquisition electrodes 224 and 225 are connected to the DC bias application electrodes 227 and 22 as in the case of the seventh embodiment. Since 8 is not sandwiched, the capacitance characteristic can be stabilized.

FIG. 20 shows a capacitor 221c according to the tenth embodiment of the present invention. FIG. 20 (a) corresponds to FIG. 15 (a) or FIG. 19 (a), and FIG. b) corresponds to Fig. 15 (c) or Fig. 19 (c). In FIG. 20, elements corresponding to the elements shown in FIG. 15 or FIG. 19 are given the same reference numerals, and redundant descriptions are omitted.

[0153] The capacitor 221c according to the tenth embodiment is characterized in that the DC noise applying electrodes 227 and 228 are formed. That is, the first and second DC bias applying electrodes 227 and 228 are formed in the capacitance forming region with respect to the position in the principal surface direction of the force dielectric layer 222 similar to the capacitor 221b according to the ninth embodiment described above. It is provided so as to overlap 226. Therefore, as in the case of the capacitor 221a according to the eighth embodiment described above, the distance between the first and second DC bias application electrodes 227 and 228 can be further shortened, and as a result, the DC noise is applied. Even if the voltage is relatively low, the effect of capacitance change can be obtained.

FIG. 21 is a view corresponding to FIG. 15 or FIG. 19, showing a capacitor 221d according to an eleventh embodiment of the present invention. In FIG. 21, elements corresponding to the elements shown in FIG. 15 or FIG. 19 are given the same reference numerals, and redundant description is omitted.

[0155] The capacitor 221d according to the eleventh embodiment is characterized by the shapes of the DC bias applying electrodes 227 and 228. That is, the first and second DC bias applying electrodes 227 As well shown in FIG. 21 (c), and 228 are comb-shaped to form a plurality of parallel electrode fingers 238 and 239, respectively. The electrode fingers 238 provided on the first DC bias applying electrode 227 are positioned so as to enter between the electrode fingers 239 provided on the second DC bias applying electrode 228.

According to the eleventh embodiment, the facing area can be increased while the distance between the first and second DC bias applying electrodes 227 and 228 is kept short.

FIGS. 22 and 23 are diagrams corresponding to FIG. 15 (a), showing capacitors 241 and 251 according to the twelfth and thirteenth embodiments of the present invention, respectively. 22 and FIG. 23, elements corresponding to those shown in FIG. 15 (a) are denoted by the same reference numerals, and redundant description is omitted.

Capacitors 241 and 251 according to the twelfth and thirteenth embodiments include a plurality of sets of first capacitance acquisition electrodes 224, second capacitance acquisition electrodes 225, and first DC bias application in the capacitor main body 223. Electrode 227 and a second DC bias applying electrode 228 are formed! /! /

More specifically, in the capacitor 241 according to the twelfth embodiment shown in FIG. 22, the first capacitance acquisition electrode 224, the DC bias application electrodes 227 and 228 from the top in the stacking direction. The second capacitance acquisition electrode 225 is repeatedly arranged in the order of several times.

In the capacitor 251 according to the thirteenth embodiment shown in FIG. 23, the first capacitance acquisition electrode 224, the DC bias application electrodes 227 and 228, and the second capacitance acquisition electrode from the top in the stacking direction. 225, DC bias application electrodes 227 and 228, first capacitance acquisition electrodes 224, t, which are arranged in a plurality of times in the same order.

Note that when comparing the capacitor body 223 of the capacitor 241 shown in FIG. 22 and the capacitor body 223 of the capacitor 251 shown in FIG. It is only a result brought about because the number of electrodes 224, 225, 227 and 228 to be shown is different, and the difference in the thickness direction shown in the drawing is not particularly meaningful.

[0162] Next, as in the capacitors 241 and 251, the capacitor body 223 forces multiple sets of In the case of including the first capacitance acquisition electrode 224, the second capacitance acquisition electrode 225, the first DC bias application electrode 227, and the second DC bias application electrode 228, the capacitor according to the present invention In Example 6, which was conducted to confirm that the capacitance per unit volume was increased, and that it was possible to reduce the size and increase the capacitance, and that the capacitance could be controlled over a wider range at a lower voltage. I will explain.

[0163] In Experimental Example 6, capacitors according to Sample 211 as an example within the scope of the present invention and Sample 212 as a comparative example outside the scope of the present invention were fabricated. The material and thickness of the dielectric layer and the material and thickness of the electrode were the same as in Experimental Example 5 described above. In addition, the external dimensions of the capacitors according to Samples 211 and 21 2 in this experimental example were both 3.2 mm X l.6 mm X l.6 mm.

More specifically, for the sample 212, the electrode arrangement structure shown in FIG. 24 was adopted, and the number of layers of all electrodes including the DC bias application electrode and the capacitance acquisition electrode was 500. . On the other hand, for sample 211, the electrode arrangement structure shown in FIG. 22 was adopted, and the number of stacked layers of all electrodes including the first and second capacitance acquisition electrodes and the first and second DC bias application electrodes Was set to 500.

[0165] Table 3 shows the capacitance change ranges of these samples 211 and 212 when the DC bias is changed in the range of 0 to 36V.

[0166] [Table 3]

[0167] As shown in Table 3, when comparing sample 211 within the scope of the present invention with sample 212 outside the scope of the present invention, the capacitor dimensions were the same and the number of stacked electrodes was the same. If so, according to the capacitor of the present invention, a larger capacity can be obtained and the variable width of the capacity can be made wider.

[0168] The forces described above with reference to Figs. 15 to 23 for the seventh to thirteenth embodiments according to the third aspect of the present invention are within the scope of the present invention. Possible It is.

[0169] For example, regarding the positional relationship between the capacitance acquisition electrode and the DC bias application electrode, the first and second DC bias application electrodes facing each other are used to connect the first and second capacitance acquisition electrodes. Any positional relationship other than the positional relationship in the illustrated embodiment may be used as long as it can apply a DC bias to the capacitance forming region of the dielectric layer.

[0170] Also, the positions on the capacitor body where the first and second DC bias applying terminal conductor films and the first and second capacitance acquisition terminal conductor films are provided are described above. The capacitance acquisition electrode and the positions of the first and second DC bias application electrodes can be arbitrarily changed.

In the seventh to thirteenth embodiments, the first and second capacitance acquisition electrodes 224 and 225 and the first and second DC bias application electrodes 227 and 228 are both capacitors. If there is no concern about the moisture resistance problem formed inside the main body 223, the electrode located at the end in the stacking direction, for example, the capacitor 221 shown in FIG. The first and / or second capacitance acquisition electrodes 224 and / or 225 can be formed on the outer surface of the capacitor body!

Claims

The scope of the claims

[1] A capacitor main body having a laminated structure including a plurality of dielectric layers, the capacitor main body including a ground electrode provided along the specific dielectric layer, and the specific dielectric layer A DC bias applying electrode that is used to apply a DC bias between and opposite to the grounding electrode, and the DC bias applying electrode is sandwiched between the grounding electrode And a capacitance acquisition electrode provided so as to form a capacitance by facing the grounding electrode through the specific dielectric layer,

A grounding terminal conductor film provided on the outer surface of the capacitor body and electrically connected to the grounding electrode;

A DC bias applying terminal conductor film provided on the outer surface of the capacitor body and electrically connected to the DC bias applying electrode;

A first capacitance acquisition terminal conductor film provided on the outer surface of the capacitor body and electrically connected to the capacitance acquisition electrode;

Further comprising a capacitor.

[2] The capacitor body further includes a second capacitance acquisition terminal conductor film provided on the outer surface of the capacitor body and electrically connected to the ground electrode, and the capacitor body extends in the stacking direction. The ground terminal conductor film is provided on the first side face, and the DC bias applying terminal conductor film is a second side facing the first side face. The first capacitance acquisition terminal conductor film is provided on the side surface, and the first capacitance acquisition terminal conductor film is provided on the third side surface adjacent to the first and second side surfaces, and the second capacitance acquisition terminal conductor is provided. The capacitor according to claim 1, wherein the film is provided on the fourth side surface facing the third side surface.

3. The capacitor according to claim 1, wherein the dielectric layer positioned at least between the grounding electrode and the DC bias applying electrode is also configured with a material force having a large DC noise dependency of dielectric characteristics.

[4] The capacitor body according to any one of claims 1 to 3, wherein the capacitor body includes a plurality of sets of the grounding electrode, the DC bias application electrode, and the capacitance acquisition electrode. Nsa.

[5] A capacitor body having a laminated structure composed of a plurality of dielectric layers, wherein the capacitor body is provided so as to form a capacitance by facing each other with the specific dielectric layer interposed therebetween. First and second capacitance acquisition electrodes, and the first and second capacitors used to apply a DC bias to the capacitance formation region of the dielectric layer located between the first and second capacitance acquisition electrodes. 2 DC bias application electrodes,

The first DC bias application electrode is provided on the same main surface as the main surface of the dielectric layer provided with the first capacitance acquisition electrode,

The second DC bias application electrode is provided on the same main surface as the main surface of the dielectric layer provided with the second capacitance acquisition electrode,

First and second DC bias applying terminal conductor films provided on an outer surface of the capacitor body and electrically connected to the first and second DC bias applying electrodes, respectively;

A capacitor further comprising: first and second capacitor acquisition terminal conductor films provided on an outer surface of the capacitor body and electrically connected to the first and second capacitor acquisition electrodes, respectively. .

[6] The side on which the first DC bias application electrode is located with respect to the first capacitance acquisition electrode is the second DC bias application with respect to the second capacitance acquisition electrode. 6. The capacitor according to claim 5, wherein the capacitor is on a side opposite to a side where the electrode is located.

[7] The capacitor body has a rectangular parallelepiped shape having four side surfaces extending in the stacking direction, and the first DC bias applying terminal conductor film is provided on the first side surface, and the second side A DC bias applying terminal conductor film is provided on the second side surface facing the first side surface, and the first capacitance acquisition terminal conductor film is adjacent to the first and second side surfaces. 6. The capacitor according to claim 5, wherein the capacitor is provided on the third side surface, and the second capacitance acquisition terminal conductor film is provided on the fourth side surface facing the third side surface.

[8] At least the dielectric layer constituting the capacitance forming region has a DC bias having dielectric characteristics. Great dependence on the service! 6. The capacitor according to claim 5, wherein the capacitor is made of a material.

The capacitor body includes a plurality of sets of the first capacitance acquisition electrode, the second capacitance acquisition electrode, the first DC bias application electrode, and the second DC bias application electrode. Item 5 !, then 8!

A capacitor body having a laminated structure including a plurality of dielectric layers, wherein the capacitor body is provided so as to form a capacitance by facing each other through the specific dielectric layer; First and second DCs used to apply a DC bias to the capacitance forming region of the dielectric layer located between the first and second capacitance acquisition electrodes and the first and second capacitance acquisition electrodes. A bias application electrode,

The first and second DC bias application electrodes are provided on the same main surface of the same dielectric layer sandwiched between the first and second capacitance acquisition electrodes;

11. The capacitor according to claim 10, wherein the first and second DC bias applying electrodes are provided so as not to overlap the capacitance forming region with respect to a position of the dielectric layer in a main surface direction.

11. The capacitor according to claim 10, wherein the first and second DC bias applying electrodes are provided so as to overlap the capacitance forming region with respect to the position of the dielectric layer in the main surface direction.

Each of the first and second DC bias applying electrodes has a comb-tooth shape forming a plurality of parallel electrode fingers, and each of the electrode fingers included in the first DC bias applying electrode is 11. The capacitor according to claim 10, wherein the capacitor is positioned so as to enter between each of the electrode fingers provided in the second DC bias application electrode. [14] The capacitor body has a rectangular parallelepiped shape having four side surfaces extending in the stacking direction, and the first DC bias applying terminal conductor film is provided on the first side surface, and the second side A DC bias applying terminal conductor film is provided on the second side surface facing the first side surface, and the first capacitance acquisition terminal conductor film is adjacent to the first and second side surfaces. 11. The capacitor according to claim 10, wherein the capacitor is provided on the third side surface, and the second capacitance acquisition terminal conductor film is provided on the fourth side surface facing the third side surface.

15. The capacitor according to claim 10, wherein at least the dielectric layer constituting the capacitance forming region also has a material force having a large DC bias dependence of dielectric characteristics.

[16] The capacitor body includes a plurality of sets of the first capacitance acquisition electrode, the second capacitance acquisition electrode, the first DC bias application electrode, and the second DC bias application electrode. The capacitor according to claim 10, and 15!