TWI331759B - Capacitor - Google Patents

Description

1331759 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a capacitor, which is a capacitor that changes the capacitance by an externally applied DC bias voltage. [Prior Art] In the variable capacitor, the electric valley state of the electric valley is changed by the DC bias applied by the externally applied fy jin, for example, there is a Japanese special fair ^ ^ 么 5 - 1997 公报 公报 (Patent Document 1) The place has been. Referring to Fig. 24 and Fig. ♦ ♦ 电 The electric grid device described in Patent Document 1 will be described. Fig. 24 is a front view showing the capacitor in a direction facing the lamination direction of the dielectric sound * gg _ _ S; Fig. ^ + shows a plan view of the capacitor by a section extending in the direction of the main surface of the dielectric layer. As shown in Fig. 24, the capacitor 丨 is provided with a body body 3 having a dielectric body 3 having a rectangular structure in which a plurality of dielectric layers 2 are formed in a laminated structure. Further, the capacitor body 3 has DC bias application electrodes 4 and 5 which are paired with each other, and a pair of capacitors which are mutually coupled to each other. The electric valley obtaining electrodes 6 and 7 are located between the DC biasing electrodes 4 and 5. The DC bias application electrode 4, the capacitance take Si ^ m ^ evaluation 1: the pole 6, the capacitor transfer electrode 7 and the DC bias application electrode $ each drawer layer 2β ... each layer has a dielectric diagram 25 display The above-described DC bias application electrode * and each layer pattern of each of the electrodes 6 and 7 are taken. In Fig. 25: Ά fA. , * (a), (b), (c) (d) are not arranged in the order of stacking, Figure 25 () ^, you do not pass the DC bias plus electrode 4 The cross section, Fig. 25(b) shows the section through which the electrode 5 is passed by the DC bias, and Fig. 25(c) is the section through which the electrode 5 Π31759 6 is obtained. 25(d) shows the cross section of the capacitor. As clearly shown in Fig. 25, the capacitor body 3 has four side faces 8 to 11 extending in the lamination direction. On the side faces 8, 9, 10, and B 1 1 L ' 夂 11, the DC bias application terminal conductor films 12 and 13 and the capacitance acquisition terminal conductor films 14 and 15 are provided, respectively. As shown in Fig. 25 (a), the DC bias application electrode 4 is pulled out to the side surface 8, and is electrically connected to the DC bias application terminal conductor film 12. As shown in Fig. 25(b), the DC bias application electrode 5 is pulled out to the side surface 9, where it is electrically connected to the DC bias application terminal conductor film 13. As shown in Fig. 25(c), the capacitor-acquisition electrode 6 is pulled out to the side surface 10, and is electrically connected to the capacitor-acquisition terminal conductor film 14 here. As shown in Fig. 25 (d), the capacitor-acquisition electrode 7 is pulled out to the side surface 11' to be electrically connected to the capacitor-acquisition terminal conductor film Μ. The capacitor 1 having the above configuration is obtained by the capacitance-acquisition terminal conductor films w and 15 between the pair of capacitance-acquisition electrodes 6 and 7. At this time, when the DC bias application terminal conductor films 12 and 13 are applied, and a DC bias voltage is applied between the DC bias application electrodes 4 and 5, the dielectric layer 2 between the DC bias application electrodes 4 and 5 is placed. Dielectric constant, etc.; I electrical characteristics will change. The dielectric properties of the dielectric layer 2 between the capacitor-capturing electrodes 6 and 7 are changed. As a result, the capacitance of the terminal conductor films 14 and 15 obtained by the capacitors can be changed. No. (Patent Document 2) is described. Fig. 26 shows a capacitor la as described in Patent Document 2, which is similar to the configuration of the capacitor 1 shown in Fig. 24, and corresponds to Fig. 24. In FIG. 26, the same reference numerals are given to the same components as those in FIG. 24, and the repeated description is omitted. In the capacitor ia shown in Fig. 26, the DC bias application electrodes 4 and 5 are sandwiched between the capacitance acquisition electrodes 6 and 7. As for the other configurations, it is substantially the same as the capacitor 1 shown in Fig. 24. However, the capacitors 1 and 1a have the following problems to be solved. First, in the capacitors 1 and 1a, in order to make the capacitance variable, the electrodes provided in the capacitor body 3, such as the DC bias application electrodes 4 and 5, and the capacitance acquisition electrodes 6 and 7, require at least four layers of electrodes. Further, at least three layers are required to separate the dielectric layers 2 each of the electrodes 4 to 7 from each other, which is not advantageous for miniaturization. Further, in the capacitor 1 shown in Fig. 24, the dielectric layer 2 having a dielectric property change has only one layer, but it is necessary to apply a DC bias voltage to the dielectric layer 2 of the three layers. Since the electric field strength is inversely proportional to the distance between the electrodes, since φ is in the above configuration, if the thickness of each dielectric layer 2 is the same, in order to obtain the required electric field strength, it is necessary to apply a DC voltage three times that of one layer, which causes the driving voltage. The problem of getting higher. Further, not all of the dielectric layers 2 located between the DC bias application electrodes 4 and 5 are related to the electrostatic capacitance.

The case of the capacitor la shown, due to the capacitance

When the thickness of each layer is the same, the thickness of the dielectric layer 7 丄 1 1759 to which the DC bias is applied is 丨/3 which contributes to the total thickness of the dielectric layer 2 which contributes to the electrostatic capacitance, and the rate of change of the capacitance is lowered to the dielectric. The bulk layer 2 material itself has a problem of less than one third of the DC bias characteristics. Further, since it is difficult to shorten the distance between the capacitor-acquisition electrodes 6 and 7, it is not advantageous for small size and large capacitance. [Patent Document 1] Japanese Patent Application Laid-Open No. Hei. No. Hei. The present invention is classified into the i-th, second, and third types in terms of the arrangement of the DC bias application electrodes.

In the first type, the capacitor of the present invention comprises a capacitor body having a laminated structure composed of a plurality of dielectric layers. The capacitor body includes: a grounding electrode disposed along a specific dielectric layer; the DC biasing application electrode is opposed to the grounding electrode through a specific dielectric layer, and is used to apply a DC bias between the grounding electrode and the grounding electrode. The capacitor and the capacitor-acquisition electrode are disposed so as to sandwich the DC bias application electrode between the ground electrode and the specific dielectric layer, and face the ground electrode to form a static capacitance P. Further, the capacitor further includes: a grounding terminal conductor film electrically connected to the grounding electrode; a DC bias application terminal conductor film electrically connected to the DC bias application electrode; and an ith capacitor electrically connected to the capacitance obtaining electrode The terminal conductor film ′ is used for the grounding terminal conductor film, the DC bias 8 1331759 pressure application terminal conductor film, and the second capacitor acquisition terminal conductor film, and is provided on the outer surface of the capacitor body. In the first aspect, the capacitor of the present invention preferably further includes a second capacitor-acquisition terminal conductor film which is provided on the outer surface of the capacitor body and is electrically connected to the ground electrode. In this case, it is preferable that the capacitor main body has a rectangular parallelepiped shape having four side faces extending in the lamination direction, the ground terminal conductor film is provided on the first side surface, and the DC bias application terminal conductor film is "> The second capacitor-acquisition terminal conductor film is provided on the third side surface adjacent to the first and second side faces, and the second capacitor-acquisition terminal conductor film is provided on the second side surface opposite to the first side surface. On the fourth side opposite to the third side. In the capacitor of the first type, it is preferable that at least the dielectric layer between the ground electrode and the DC bias application electrode is made of a material having a large DC bias dependence of dielectric characteristics. In the capacitor of the first type, the capacitor body may include a plurality of electrodes for grounding the array, a DC bias application electrode, and a capacitor acquisition electrode. In the second type, the capacitor of the present invention includes a capacitor body having a laminated structure composed of a plurality of dielectric layers. The capacitor body includes: the first and second capacitor-acquisition electrodes are disposed such that the dielectric layers of the first and second capacitors are disposed opposite each other to form a static capacitance; and the first and second DC bias application electrodes are used for A DC bias voltage is applied to a capacitance forming region of the dielectric layer between the first and second capacitor obtaining electrodes. Further, the first DC bias application electrode is provided on the same main surface as the main surface of the dielectric layer provided on the first capacitance acquisition electrode.

L 1331759 Adding an electrode is set on the same main surface as the main surface of the electric layer. Further, the capacitors are further provided with first and second DC bias application terminal conductors electrically connected to the first and second straight bias application electrodes, respectively, and electrically connected to the first And the second and second capacitor-acquisition terminal conductor films of the second capacitor-acquisition electrode, such 帛i and the second DC (four)

The terminal conductor film for application and the terminal conductor film for obtaining the first and second capacitors are provided on the outer surface of the capacitor body. ★ In the second type, it is better, relative to the first! The capacitor-acquisition electrode is located on the side where the first DC bias application electrode is located on the side opposite to the side on which the second DC bias application electrode of the second capacitor-receiving electrode is located. In the capacitor of the second type, preferably, the capacitor body has a rectangular parallelepiped shape having four side faces extending in the lamination direction, and the second DC bias application terminal conductor film is disposed on the second side surface, the second DC bias voltage The application terminal conductor film is provided on the second side opposite to the first side surface, the first! The terminal conductor film for capacitor acquisition is provided on the third side surface adjacent to the first and second side faces, and the second capacitor-acquisition terminal conductor film is provided on the fourth side face opposed to the third side face. In the capacitor of the second type, it is preferable that at least the dielectric layer constituting the capacitance forming region is made of a material having a large DC bias dependence of dielectric characteristics. In the capacitor of the second type, the capacitor body may include a plurality of first capacitor acquisition electrodes, a second capacitor acquisition electrode, a first DC bias application electrode, and a second DC bias application electrode. 10 1331759 i to the third type The capacitor of the present invention includes a capacitor body having a laminated structure composed of a plurality of dielectric layers. The capacitor body includes: a flute 1 «π and a second capacitor-acquisition electrode, which are arranged to pass each other through a specific dielectric layer f + + &&&& + T, thereby forming a static capacitance; and And the second straight bias biasing electrode is a capacitor forming region for applying a DC bias voltage to the dielectric layer between the first and second capacitor obtaining electrodes. Further, the first J9^n upper music 2 DC bias application electrode is provided on the same main surface of the same dielectric layer sandwiched between the first and second electric current acquisition electrodes. Further, the electric grid device further includes: first and second DC bias application terminal conductor films ' electrically connected to the first and second DC bias application electrodes, and a tool f connected to the i-th and second capacitors The terminal conductor film for obtaining the first and second capacitors of the electrode; the first and second DC biases are used to mount the terminal conductor film and the terminal conductor film for the i-th and second capacitors in the capacitor body On the outer surface. Φ In the third type, the first and second DC bias application electrodes may be disposed so as not to overlap with the capacitance formation region in the direction of the main surface of the dielectric layer, or may be disposed to overlap with the capacitance formation region. . In the capacitor of the third type, the jth and the second DC bias electrodes are the comb-shaped portions of the plurality of electrode fingers formed in parallel, and the electrode fingers of the first DC bias application electrode are provided. Further, it may be placed at a position between each of the electrode fingers provided in the second DC bias application electrode. In the capacitor of the third type, it is preferable that the capacitor system has a rectangular parallelepiped shape in which four side faces extend in the lamination direction, and the first DC bias application 1331759 is provided to the second DC bias application terminal conductor by the terminal conductor film. The film system is provided on the second side surface facing the i-th side, and the second (the capacitor-acquisition terminal conductor film is provided on the first side Φ adjacent to the i-th and second side faces, and the second f-groove end + conductor The film is disposed on the fourth side opposite to the third side. The third type of electric grid device preferably has at least a dielectric layer constituting the capacitance forming region, and a DC bias biased by dielectric characteristics. Dependent material

Material composition. In the capacitor of the third type, the capacitor main body may include a plurality of first capacitor acquisition electrodes, a second capacitor acquisition electrode, a 直流1 DC bias application electrode, and a second DC bias application electrode. A capacitor of the type 1 is provided with a DC biasing electrode in accordance with the present invention, and the grounding electrode is provided in a direction in which both the first applied electrode and the capacitor-acquisition electrode are opposed to each other. The electrode for applying a DC bias is also paired with the capacitor obtaining electrode as an electrode for forming a static capacitance. For example, & 'has two functions for the grounding electrode', and the tantalum capacitor is variable, and gj is the capacitor body, and at least three electrodes of the grounding electrode, the DC bias applying electrode, and the capacitor obtaining electrode are required. And at least two dielectric layers act as an "electrical layer separating the electrodes. Therefore, it is advantageous to develop the miniaturization of the capacitor. Further, in the first embodiment, the capacitor body is not interposed between the DC bias application electrode and the ground electrode. Therefore, the DC bias application electrode and the ground electrode can be easily narrowed. Further, when the DC bias application electrode and the ground electrode are spaced apart from each other, 12 1331759 改变 changes the dielectric characteristics of the dielectric layer at a lower voltage, and as a result, the capacitor can be controlled with a lower voltage. Static capacitance. Further, in the first type, since the capacitance is made variable as described above, the number of electrodes and the dielectric layer required for the capacitor body can be reduced, so that the volume capacitance can be increased, and the size and capacitance can be easily reduced. In the first type, the capacitor of the present invention further includes a second capacitor-acquisition terminal conductor film electrically connected to the grounding electrode, wherein the capacitor body has a rectangular parallelepiped shape having four side faces, and the grounding terminal conductor film is provided in the first In the side surface, the terminal-bonding film for applying a DC bias is provided on the second side surface. The first capacitor-acquisition terminal conductor film is provided on the third side surface, and the second capacitor-acquisition terminal conductor film is provided on the fourth side surface. The configuration state substantially the same as that of the variable capacitors disclosed in Patent Documents 1 and 2 can be employed. In the capacitor of the first type, if at least the dielectric layer between the grounding electrode and the DC bias application electrode is made of a material having a high DC bias and dependence of dielectric characteristics, DC bias can be used. The variable capacitance has a wider range of variations. In the capacitor of the first type, if the capacitor body includes the multi-array grounding electrode, the DC bias application electrode, and the capacitance-acquisition electrode, the variable range of the DC bias static capacitance can be made wider. It is also possible to make the electrostatic capacitance larger. According to the second type of capacitor of the present invention, the first and second capacitor-preventing electrodes are required to form the electrostatic capacitance, and the first and second DC bias-applying electrodes are required to make the capacitance constant. 1331759 φ capacitance acquisition electrode and each of the first and second DC bias housing applications have the following characteristics, that is, the 1 ! DC bias application electrode, the money is placed and the first capacitance acquisition electrode is provided. The DC bias applying electrode on the main surface of the dielectric layer having the same main surface is provided on the same main surface as the main surface of the dielectric layer on which the second capacitor obtaining electrode is provided. Therefore, 'the minimum configuration required to make the capacitance variable is realized by the layer dielectric layer (forming the capacitor formation region) and the two electrode layers sandwiching the dielectric layer. Therefore, the patent document i Or the conventional capacitance variable capacitor disclosed in 2 can be miniaturized and capacitive. In the capacitor of the second type, the first and second DC bias application electrodes are applied to the dielectric layer because there is no grounding electrode between the i-th and second DC bias application electrodes. The electric field in the capacity forming region is not shielded, and it is possible to suppress a decrease in the rate of change in capacitance caused by a decrease in electric field strength. Therefore, the electrostatic capacitance given by the capacitor can be suppressed with a lower voltage. In the capacitor of the second type, the electrode for the first DC bias application electrode is located on the side of the first DC bias application electrode and the second DC bias application electrode for the second capacitance acquisition electrode. The side is the phase side, and in the capacitance forming region of the dielectric layer, a DC bias is applied to the oblique direction of the dielectric sound direction, and the first and second capacitor receiving electrodes and the first and second electrodes can be used. The application of DC dust is a compact configuration of the Remy quadrupole, which contributes to the miniaturization of the capacitor. In the capacitor of the second type, the capacitor body has a rectangular parallelepiped shape having four side faces 1331759, and the first and second DC bias application terminal conductor films and the first and second capacitor-acquisition terminal conductor films are respectively The first side surface, the second side surface opposite to the first side surface, the third side surface adjacent to the first and second side surfaces, and the fourth side surface opposite to the third side surface can be used The variable capacitors described in Patent Documents 1 and 2 have substantially the same configuration state. - In the capacitor of the second type, if at least the dielectric layer of the capacitor forming region is made of a material having a large DC bias dependence of dielectric characteristics, the variable range of the DC bias can be made more variable. wide. In the capacitor of the second type, if the capacitor body includes the plurality of first capacitor acquisition electrodes, the second capacitor acquisition electrode, the ith DC bias electrode, and the second DC bias electrode, The static capacitance of the DC bias is wider, and the electrostatic capacitance can be obtained for a longer period of time. According to the first embodiment of the present invention, the first and second capacitors are required for forming the electrostatic valley; Emperor | Needs 1st and hope" ☆ #用电极, in order to make the static capacitance variable *The first and second DC bias apply thunder...θ... (4) Add the electrode, but these 帛i and 2nd In the present invention, the electrode for use and the position of the second electrode, which is the electrode for the electrode to be applied, is provided on the same main surface of the same dielectric layer as the second and second DC biases. The minimum structure required for clamping between the electrodes is as follows: two:: electric body = electric ... ^ domain) and three layers of electric layers that sandwich each dielectric layer (formation of capacitance forming region 1 or 2) It is recorded that this is compared with the variable capacitors in the above-mentioned special office. In the case of the capacitor of the third type, since the ground electrode is not present between the first and second DC bias application electrodes, the second and second DC biases are used. The electric field applied to the capacitance forming region of the dielectric layer by the pressure applying electrode is not shielded, and the decrease in the capacitance change rate due to the decrease in the electric field strength can be suppressed. Therefore, the electrostatic capacitance given by the capacitor can be suppressed with a lower voltage. In the capacitor of the third type, the position of the second and second DC bias application electrodes in the main surface direction of the dielectric layer is set to overlap with the capacitance formation region, whereby the second and second capacitors can be obtained. Since the electrode does not sandwich the DC bias application electrode, the capacitance characteristics can be stabilized. On the other hand, in the third type of capacitor, the first and second DC bias application electrodes are in the direction of the main surface of the dielectric layer. When the position is overlapped with the capacitance forming region, the distance between the second and second DC bias application electrodes can be shortened, and as a result, even if a lower voltage is applied as a straight In the case of the flow bias, the effect of the capacitance change can also be obtained. In the capacitor of the third type, the second and second DC bias application electrodes are comb-shaped teeth forming a plurality of electrode fingers juxtaposed, if Between each of the electrode fingers of the second DC bias application electrode, the electrode fingers of the DC bias application electrode are interposed between the first and second DC bias application electrodes. The distance is shortened, and the opposing area of the first and second DC bias application electrodes can be increased, and even if a lower voltage is applied as a DC bias, a capacitance change effect can be obtained. The capacitor body is a rectangular parallelepiped having four side faces 16 1331759. The first and second DC bias application terminal conductor films and the first and second capacitor-acquisition terminal conductor films are respectively disposed on the first side. The second side surface opposite to the first side surface, the third side surface adjacent to the first and second side surfaces, and the fourth side surface facing the third side surface can be used in Patent Documents 1 and 2. The variable capacitors described are substantially identical in construction. State. In the capacitor of the third type, if at least the dielectric layer constituting the capacitance forming region is made of a material having a large DC bias dependence of dielectric characteristics, the variable range of the electrostatic capacitance of the DC bias can be made wider. In the capacitor of the third type, the capacitor body includes the plurality of first capacitor acquisition electrodes, the second capacitor acquisition electrode, the second DC bias application electrode, and the second DC bias application electrode. It is also possible to make the static capacitance larger than the variable capacitance of the DC bias of '1'. [Embodiment] (Embodiment 1) FIG. 1 and FIG. 2 are for explaining the first aspect of the present invention. In the capacitor 21 of the embodiment, FIG. 1 and (4) are diagrams corresponding to FIG. 24 or FIG. 26, and the cross section of the dielectric layer 22 is shown in the cross section of the dielectric layer 22 to show the view of the capacitor 21 (b) to (4). In the drawing corresponding to FIG. 25, a plan view of the capacitor η is shown in a cross section extending in the direction of the main surface of the dielectric layer 22. FIG. 2 is an equivalent circuit diagram of the state in which the capacitor 21 is applied with a DC bias. - As shown in Fig. 1 (4), the capacitor 21 is provided with a capacitor body 23 having a laminated structure of a plurality of dielectric layers 22, which is provided with a plurality of dielectric layers 22. The grounding electrode 24 provided in the specific dielectric layer 22; the DC bias applying electrode 25 is transmitted through the specific dielectric layer 22 and the grounding electrode 24, and is used to apply a DC bias between the grounding electrode 24 and the grounding electrode 24. And the capacitor acquisition electrode 26 is disposed so as to be sandwiched between the DC bias application electrode 25 and the ground electrode 24, and is transmitted through the specific dielectric layer 22 and the ground electrode 24, thereby forming Static capacitance. As clearly shown in Figs. 1(b) to 1(d), the capacitor body 23 has a rectangular parallelepiped shape having four side faces 27 to 30 extending in the lamination direction. On the side surface 27, a grounding terminal conductor film 31 is provided. On the second side face 28 opposed to the second side 27, the DC bias application terminal conductor film 3 2 is not provided. On the third side face 29 adjacent to the first and second side faces 27 and 28, a first capacitor-acquisition terminal conductor film 33 is provided on the fourth side face 30 opposed to the third side face 29, and is provided. The second capacitor acquisition terminal conductor film 34. Fig. 1(b) shows a cross section through which the capacitor obtaining electrode 26 passes. The capacitor-acquisition electrode 26 is pulled out to the third side face 29, and is electrically connected to the first capacitor-acquisition terminal conductor film 33. Fig. 1(c) shows a cross section through which the DC bias applying electrode 25 passes. The DC bias application electrode 25 is pulled out to the second side surface 28, where it is electrically connected to the DC offset application terminal conductor film 32. In Fig. 1(d), the grounding electrode 24 is shown to be pulled out to the i-th side 27, and is also pulled out to the fourth side of the fourth side, and the grounding power S24 is used. The side surface 27 is electrically connected to the grounding end 1331759 sub-conductor film 31', and the terminal conductor film 34 is electrically connected to the fourth side surface 30. The capacitor 21 having the above configuration is as shown in FIG. 2, and the electrostatic capacitance formed between the grounding electrode 24 and the capacitor (four) electrode 26 is obtained from the first and second capacitor-forming terminal conductor films 33 and 34. take out. The first and second capacitor-acquisition terminal conductor films 33 & 34 are electrically connected to a predetermined circuit (not shown). At this time, when the terminal conductor film 32 for grounding and the terminal conductor film 32 for direct bias application are applied, a DC bias 37 is applied between the ground electrode 24 and the DC bias voltage to the application electrode 25, and the ground electrode μ is placed. = The dielectric constant of the dielectric layer 22 between the DC bias application electrodes 25 is changed, and the characteristics are changed. Therefore, the dielectric properties of the dielectric layer 22 located between the grounding electrode 24 and the capacitor electrode 26 are changed. As a result, the terminal conductor film 33 for obtaining the first and second capacitors can be changed. And the electrostatic capacitance taken out of 34. In order to increase the variation of the electrostatic capacitance, the dielectric layer 22, particularly the dielectric layer 22 between the grounding electrode 24 and the DC bias applying electrode 25, is preferably DC-biased by dielectric characteristics. Sexual material structure =. Thus, as a material having a large DC bias dependence of dielectric characteristics, for example, ^^®ai.o〇6(Ti0 97Zr0 03)〇3 — 2.5Gd〇3 / 2~2.5Mg〇—〇.5Mn〇—i 。 〇 1 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次Further, a sample 2 of a comparative example which is substantially the same as the range of the present invention, which is substantially the same as the capacitance stomach 1 shown in Fig. 24, is prepared. In each of the samples 2 and 2, as the dielectric material constituting the dielectric layer, a BaTi〇3 type high dielectric constant ceramic material was used, and the thickness of the dielectric layer between the electrodes was 2 Å. Further, the electrode is recorded as a main component, and the thickness is again. The external dimensions of the capacitor body are 3.2 mm x 1.6 mm x 0.4 mm. For each of the samples 1 and 2 described above, the rate of change in capacitance when a plurality of DC bias voltages in the range of 0 to 36 V were applied was determined. The results are shown in Fig. 3. As can be seen from Fig. 3, the electrostatic capacitance is reduced by about 8% or more in the sample 1, and the other is reduced by about 25% in the sample 2. This is due to the pair of DC bias application electrodes in Sample 2.

In contrast, in the sample, one of the Z electrodes for applying the direct voltage and one of the electrodes for obtaining the capacitance are octoberized by the grounding electrode, so that the DC bias is paired. There is only one dielectric layer between the electrodes for application. As a result, depending on the sample i, the required rate of change of capacitance can be obtained at a lower voltage. Further, in the above experimental example i, although a specific BaTi〇3 type of the same electric material is used as the dielectric body constituting the dielectric layer, the ceramic material of the ceramic material is used for right flow. A material with a higher bias dependence can obtain a capacitor with a wider range of capacitance variations from a DC bias. 4 and 5 show capacitors "and 51" according to the second and third embodiments of the present invention, respectively, corresponding to Fig. 1 (a). Fig. 4 and Fig. 1 and Fig. 1 (a) The same reference numerals will be given to the same reference numerals, and the description will be omitted. 20 1331759 The capacitors of the second and third embodiments are characterized in that: a capacitor array body 23 is formed with a plurality of array ground electrodes 24 and DC bias The application electrode 25 and the capacitance acquisition electrode 26 are provided. More specifically, in the capacitor 41 shown in FIG. 4, the complex array grounding electrode 24' DC bias application power 3525 and the capacitance acquisition electrode are started from above, and the capacitance acquisition electrode 26 and the DC bias application electrode are used. 25. The order of the grounding electrode 24 and the capacitor obtaining electrode 26 and . is repeated a plurality of times. In the capacitor 5" shown in FIG. 5, the capacitor acquisition electrode 26, the DC bias application electrode, the ground electrode 24, the DC bias application electrode 25, the capacitance acquisition electrode 26, ... Order, repeat the configuration multiple times.

In other words, in the capacitor 41 shown in FIG. 4, the arrangement of the capacitance obtaining electrode 26, the DC bias applying electrode, and the grounding electrode 24 of the capacitor shown in Fig. 4) is 纟" Repeat this group. In the capacitor 51 shown in Fig. 5, the grounding electrode 24 is shared between adjacent groups, and the DC bias applying electrode is disposed every two layers of the dielectric layer 22. Further, when the capacitor body 23 of the capacitor 4 shown in FIG. 4 and the capacitor body 23 of the capacitor 51 shown in FIG. 5 are compared, the thickness direction dimension is different, but this is because the electrode is to be illustrated. The result of the difference in the number of Μ~26, the difference in the thickness direction of the figure, is not of special significance. Next, as described above, the capacitors 41 and 51 have the capacitor array body 24, the DC bias application electrode 25, and the capacitor 21 1331759. The capacitor 26 can be used to confirm that the capacitor according to the present invention can be used. Experimental Example 2 was carried out to obtain a wider range of capacitance variation. b In the experimental example 2, as shown in Table 1, the capacitors of the respective samples were prepared, but the materials and thicknesses of the dielectric layers of the capacitors, and the materials and thicknesses of the electrodes were compared with the experimental example. ; the same. χ, the outer dimensions of the capacitors of each sample m were both 3.2 mm x 16__ι 6_. In the sample U, the arrangement of the electrodes shown in Fig. 24 was employed, and the number of layers including all the electrodes of the application electrode and the capacitance acquisition electrode was 50,000. The structure of the electrode shown in Fig. 26 is used for the layering of the electrodes of the application electrode and the capacitor acquisition electrode: 13' is the arrangement of the electrodes shown in Fig. 4 , the number of layers including the electrode:: one electrode and the capacitor to obtain all of the electrode when the second two:: "1 circumference: 13' DC (four) in the range of ~ ~ 36V to change the dry circumference shown in Table 1 .

13 6·8~13·7 6.0 to 36.4 [Table 1] From the sample UD of Table 1 ^γΤ ——~~, the sample 13 within the scope of the present invention and the layered teaching of the present invention are When comparing 12, the capacitors are the same size and electrically: at the same level, 'according to the capacitor of the present invention, a larger capacitance of 22 1331759 can be obtained and the variable amplitude of the capacitor can be made wider. Since the sample 11' has a structure in which the electrode for capacitor acquisition is sandwiched between the electrodes for applying a DC bias, the maximum capacitance larger than that of the sample 12 can be obtained, but the variable width of the capacitor is narrow. On the other hand, in the sample 12, since the DC bias application electrode was sandwiched between the electrodes for electric pickup, it was not possible to obtain a large capacitance. Even if the number of layers of the electrodes was 500', the maximum capacitance was only 13.7/zF. . Compared with the sample 丨3, the maximum capacitance is larger and the capacitance variable width is wider than that of the sample 丨3. Although the first to third embodiments of the first aspect of the present invention have been described above with reference to Figs. 1 to 5, other various modifications are possible within the scope of the present invention. For example, in the first to third embodiments, the second conductor valley-acquisition terminal conductor film 34 is formed in addition to the grounding terminal conductor film 31 as the terminal conductor film electrically connected to the grounding electrode 24. The terminal conductor film for obtaining the second capacitor may be omitted. In this case, the grounding terminal conductor film 31 may be provided at a position where the second capacitor obtaining terminal conductor film 34 is provided, or may be provided to extend from the position where the grounding terminal conductor film 31 is illustrated to the second position. The position at which the terminal conductor film 34 for capacitance acquisition is provided. Further, in the first to third embodiments, the grounding electrode 24, the DC biasing electrode 25 and the capacitance obtaining electrode 26 are formed inside the capacitor body 23, but are located at the outermost edge of the stacking direction, for example. The capacitor 21 shown in FIG. 1(a), the grounding electrode 24 and/or the capacitor obtaining electrode 26' may be formed on the outer surface of the capacitor body 23. 23 1331759 The various modifications of the above-mentioned i-th embodiment in the scope of the present invention are as follows: p ^ , music 2 and third change H, that is, $ 1 1 U 3 _ in addition to the description of the first to third modifications The elements corresponding to the reference symbols used in the description of the embodiments; the reference symbols to the second. The capacitors 21a according to the modification of the first embodiment will be described using the same Figs. 6 and 7. In Fig. 6~, FI, m A into " corresponds to the ® 1(a)

The figure shows the month of the capacitive 2U in the direction of the layer facing the dielectric layer... (8) ~ (d) corresponds to the figure i(b) ~ (4) along the dielectric layer 9 9 &gt * + a μ , the cross section of the main surface of the crucible 22 extends to show a plan view of the capacitor 21a. 7 corresponds to FIG. 2. As shown in Fig. 6 (4), the capacitor 21a includes a capacitor body 23 having a laminated body body 23 composed of a plurality of dielectric layers 22, and is provided with a grounding layer provided along the specific dielectric layer 22. The electrode 24; the DC bias application electrode is provided at a position that passes through the 2 constant conductor layer 22 and faces the ground electrode 24; and the electric T acquisition electrode 26 is provided at the ground electrode 24 and the DC The position between the bias application electrodes 25 is transmitted through the specific dielectric layer 22, and is opposed to the ground electrode 24 to thereby form a static capacitance. As shown clearly in Figs. 6(b) to 6(d), the cell body 23 has a rectangular parallelepiped shape having four side faces 27 to 3〇 extending in the stacking direction. The grounding terminal conductor film 31 is slanted on the first side surface 27. The DC bias application terminal conductor film 32 is provided on the second side surface 28 opposed to the first side surface 27. On the third side surface 29 adjacent to the first and second side faces 27 and 28, 24 1331759 is provided with a first capacitor-acquisition terminal conductor film 33. The second capacitor-acquisition terminal conductor film 34 is provided on the fourth side face 30 opposed to the third side face 29. Fig. 6(b) shows a cross section through which the DC bias application electrode 25 passes. The DC biasing application electrode 25 is pulled out to the second side face 28 where it is electrically connected to the DC bias! The terminal conductor film 3 2 for application is applied. Fig. 6(c) shows a section through which the capacitor-acquisition electrode 26 passes. "The capacitor-receiving electrode 26 is pulled out to the third side face 29, where it is electrically connected to the first! The terminal conductor film 33 for capacitor acquisition. Fig. 6(d) shows a cross section through which the grounding electrode 24 passes. The grounding electrode 24 is pulled out to the first! The side 27 is also pulled out to the fourth side 3〇. Further, the grounding electrode 24 is electrically connected to the grounding terminal conductor film 31 on the first side surface 27, and is electrically connected to the second capacitor-receiving terminal conductor film 34 on the fourth side surface 30. The capacitance formed between the grounding electrode 24 and the capacitance obtaining electrode 26 in the capacitor 21a having the above configuration is shown in Fig. 7. The first and second capacitor-acquisition terminal conductor films 33 and 34 are obtained. Take it out. The first and second capacitor-acquisition terminal conductor films 33 and % are electrically connected to a predetermined circuit (not shown). At this time, when the grounding terminal conductor film 3i and the DC bias application terminal conductor film 32 are applied, the DC bias voltage η is applied between the grounding electrode 24 and the DC bias application electrode, and is located between the grounding electrode 24 and the direct current. The dielectric characteristics such as the dielectric constant of the dielectric layer U between the bias application electrodes are changed. Therefore, the dielectric layer u dielectric property 25 J between the grounding electrode 24 and the capacitance obtaining electrode 26 is changed. As a result, the first and second capacitor-acquisition terminal body films 33 and 34 can be used. The static capacitance taken out changes. In this modification, in order to increase the amplitude of the change in the electrostatic capacitance, the dielectric layer 22' is particularly located between the ground electrode 24 and the capacitor-forming electrode %, preferably by dielectric properties. The material composition of the DC bias dependence is large. Further, in the first modification, since the DC bias application electrode 25 is not interposed between the ground electrode 24 and the capacitor (four) electrode 26, the capacitance can be made in comparison with the case of the first embodiment. The characteristics are more stable. FIGS. 8 and 9 show the capacitors 41a and 5U of the second and third modifications corresponding to the second and third embodiments, respectively, and correspond to FIGS. The capacitors 413 and 51a according to the second and third modifications are characterized in that, in the same manner as in the second and third embodiments, the capacitor array body 24 and the DC bias electrode are formed in the capacitor body. 25 and capacitor acquisition electrode 26. More specifically, the capacitor 41a shown in the circle 8, the complex array grounding electrode 24, the DC bias application electrode 25, and the capacitance obtaining electrode 26 are used from the top to follow the DC bias application electrode 25 and the capacitance acquisition. The order of the electrode 26, the grounding electrode 24, and the DC bias application electrodes 25, ... is repeatedly arranged plural times. The capacitor 51 a ' shown in Fig. 9 is the DC bias application electrode 25, the capacitance acquisition electrode 26, the ground electrode Μ, the capacitance acquisition electrode 26, the DC bias application electrode 25, ... The order, 26 1331759 is repeated in multiples. In other words, the capacitor 41a shown in Fig. 8 is a group of the DC bias applying electrode 25 of the capacitor 21a of Fig. 6 (mad), and the electrode for grounding and the grounding electrode 24. , and ^ I repeat this group a number of times. In the capacitor 51a shown in Fig. 9, the ground electrode 24' is shared between adjacent groups, and the capacitor electrode 26 is disposed every two layers of the dielectric layer 22. When the capacitor 4a lamella body 23 has the group grounding electrode 24, the DC bias application electrode %丨, and the capacitance obtaining electrode 26, a wider capacitance variation range can be obtained. (Embodiment of the second type) Figs. 10 and 9 are views for explaining the solar cell m of the fourth embodiment of the present invention. In FIG. 10, '(4) corresponds to FIG. 24 or FIG. 26, and the view of the capacitor ΐ2ι is shown in a cross section facing the lamination direction of the dielectric layer 122, and FIGS. 25(b) and (4) correspond to FIG. 25. In the figure, a plan view of the capacitor 121 is shown in a cross section extending in the direction of the main surface of the dielectric layer 122. FIG. 11 is an equivalent circuit diagram when a DC bias voltage is applied to the capacitor 121. As shown in Fig. 10 (4), the capacitor 121 is provided with a capacitor body 123 having a laminate of a plurality of dielectric layers 122. The capacitor body 123 includes: second and second capacitor-acquisition electric directions 24 and 125, which are formed to pass through a specific dielectric layer 122 to form a static capacitance; and a second and second DC bias are applied The electric power units 27 and 128 are used to apply a DC bias voltage to the capacitance forming 27/^9 region 126 of the dielectric layer 122 between the first and second ^ obtaining electrodes 124 and 125. The first DC bias application electrode 127 is provided on the same main surface as the main surface of the dielectric body 122 on which the i-th addition electrode 124 is provided. The second DC bias application electrode 128 is provided on the same main surface as the main surface of the dielectric layer 122 on which the second capacitance acquisition electrode 125 is provided. The first capacitor-acquisition electrode 124 is disposed, and the side where the first DC bias application electrode 127 is located and the second DC bias application electrode 128 of the second capacitor-acquisition electrode 125 are located. The side is the opposite side. The DC biases applied by the first and second DC bias application electrodes i27 and i28 are oriented in the oblique direction with respect to the thickness direction of the dielectric layer 122. As clearly shown in Figs. 10(b) and (4), the capacitor body 123' has a rectangular parallelepiped shape having four side faces 129 to 132 extending in the lamination direction. The first DC bias application terminal conductor film 33 is provided on the first side 129. The second DC bias application terminal conductor 臈 134 is provided on the second side surface [3" opposite to the first side surface 129. On the third side surface 131 adjacent to the i-th and second side faces 129 and 130, a second capacitor-acquisition terminal conductor film 135 is provided. The second capacitor-acquisition terminal conductor film 136 is provided on the fourth side surface 132 opposite to the third side surface 131. Fig. 10(b) shows a cross section through which the first capacitance acquiring electrode ία and the first DC bias applying electrode 127 pass. The second capacitor-acquisition electrode 124 is pulled out to the third side surface 131, and is electrically connected to the second capacitor-acquisition terminal conductor film 135. The first DC bias application electrode ι27 is pulled 1331759 to the first side surface 129, and is electrically connected to the first DC bias application terminal conductor film 133. A cross section through which the second capacitance acquisition electrode 125 and the second DC bias application electrode 128 pass is shown in Fig. 10(c)'. The second capacitor obtaining electrode 125' is pulled out to the fourth side face 132, and is electrically connected to the second capacitor obtaining terminal conductor film 136. The second DC bias application electrode 128 is pulled out to the second side surface 130, and is electrically connected to the second DC bias application terminal conductor film 134. In the capacitor 121 having the above configuration, the electrostatic capacitance formed between the first and second capacitance-capturing electrodes 124 and 125 is the first and second capacitance-acquisition terminal conductor film 135 as clearly shown in FIG. And 136 are taken out. The first and second capacitor-capturing terminal conductor films 135 and 136 are electrically connected to a predetermined circuit (not shown). At this time, when the DC bias voltage 137 is applied between the first and second DC bias application electrodes 127 and 128 by the second and second DC bias application terminal conductor films 133 and 134, the first and the first The dielectric characteristics of the valley formation region 126 (see Fig. i (a)) of the dielectric layer 122 between the electric grid obtaining electrodes i 24 and 125 are changed. As a result, the electrostatic capacitance taken out by the second and second capacitor-capturing terminal conductor films 135 and 136 can be changed. In order to increase the variation of the electrostatic capacitance, the dielectric layer 122, particularly the dielectric layer 122 between the ith and second DC bias application electrodes 127 and 128 constituting the capacitance forming region 126, is preferably The material has a dielectric bias with a large DC bias dependence. Thus, a material having a large DC bias dependence of dielectric characteristics is, for example, 1 〇〇Bai coffee (Ti. - 29 1331759 2.5Gd 〇 3/2_ 2_5Mg 〇 - 〇, 5MnO-l. 〇si〇2. Second, In the experimental example 3 in which the effect of the fourth embodiment was confirmed, the experimental example 3 was prepared, and the sample having substantially the same structure as the capacitor 121 shown in FIG. 10 was produced as a sample in the range of the present invention. A sample 1〇2 which is substantially the same as the capacitor i shown in FIG. 24 is prepared as a comparative example outside the scope of the present invention, and each of the samples ι〇ι and 1〇2 is used, and BaTi〇3 is used. The high dielectric constant ceramic material is used as a dielectric layer, and the thickness of the dielectric layer between the electrodes is 2 m. Further, the electrode is mainly composed of nickel and has a thickness of a capacitor. The external dimensions of the main body were 3.2 mm x 1.6 mm. 4 mm. For each of the samples 101 and 102, the rate of change in capacitance when a plurality of DC biases were applied in the range of 〇 to ≤ were obtained. The results are shown in Fig. 12 ° If a DC bias is applied to the dielectric, it is above a certain applied voltage. The capacitance change rate is constant. In Fig. 12, the capacitance change rate of the sample ι〇ι is only shown as a DC bias voltage of 12 V, but it can be confirmed that the DC bias voltage is 12 V or more. Therefore, as can be seen from Fig. 12, the sample 101' capacitance change rate is a predetermined DC bias, which is about 1/3 of the sample 102. This is because the sample 1〇2 is applied to the paired DC bias. There are three dielectric layers between the electrodes. On the other hand, in the case of the sample, the DC bias application electrode and the capacitance acquisition electrode are provided on the same surface, thereby applying a pair of DC biases. There is only one dielectric layer between the electrodes, and the electrode spacing is reduced to 1/3 compared with the sample 102, and as a result, the required rate of change of capacitance can be obtained at a lower voltage. In the sample 101, since there is no electrode (conductor layer) that shields the electric field between the pair of DC bias application electrodes, the decrease in the capacitance change rate due to the decrease in the electric field strength can be suppressed, and as a result, a large size can be obtained. Capacitance change rate. In addition, in the above In Example 3, although a specific BaTi〇3 φ high dielectric constant ceramic material is used as the dielectric material constituting the dielectric layer, the ceramic material is a material having a higher DC bias dependence using dielectric characteristics. Further, a capacitor having a wider range of capacitance variation of the DC bias voltage can be obtained. Fig. 13 and Fig. 14 show capacitors 141 and 151 of the fifth and sixth embodiments of the present invention, respectively, and correspond to Fig. 1 (4). 13 and FIG. 14 are denoted by the same reference numerals as those of the components shown in FIG. 10(a), and the description thereof will be omitted. The capacitors 141 and 151 of the fifth and sixth embodiments are characterized by In the capacitor body 123, a complex array of the ith capacitor obtaining electrode 124, the second capacitor obtaining electrode 125, the first DC bias applying electrode 127, and the second DC bias applying electrode 128 are formed. More specifically, in the capacitor 141 shown in FIG. 13, the dielectric layer 122 of the i-th capacitor-acquisition electrode 丨24 and the ith-th DC bias application electrode 127 is formed, and the second capacitor-acquisition electrode 125 and the second electrode are formed. The dielectric layer 122 of the DC bias application electrode 128 is alternately arranged in the stacking direction. In the capacitor 151 which is not shown in FIG. 14, the electric layer 122 which forms the first capacitance acquisition electrode 124 and the i-th DC bias application 31 丄09 electrode 127 is formed from the upper side in the lamination direction, and the second capacitance acquisition electrode 125 is formed. The dielectric layer 122 of the biasing application electrode 128, the body layer 122 forming the first acquisition electrode 125 and the second DC bias application electrode 128, and the first capacitance acquisition electrode 124 and the first The DC bias is applied in the order of the dielectric layers 122 of the electrodes 127 of the Thunder 197. The capacitors 141 and 151 as described above have a complex array in the capacitor body 123! When the capacitor acquisition electrode 124 and the second capacitor acquisition power: 1 125, the first DC bias application electrode 127, and the second DC bias application electrode 128 are described, it is described that the capacitor according to the present invention can be confirmed. The electrostatic capacitance per unit volume was increased, and the capacitance was further reduced and the capacitance was increased, and the experimental example 4 in which the static capacitance was controlled to a wider range was performed at a lower voltage. In the experimental example 4, each of the capacitors of the sample ΐ2 which is an example of the embodiment of the present invention and the comparative example outside the scope of the present invention was produced, but the dielectric layer material and thickness of each capacitor, and the electrode material were prepared. And thickness ' is the same as Experimental Example 3 above. Further, the appearance of each of the electric grids of the samples 1U and 112 of this experimental example was 3 ^ ^ . More specifically, the sample "2 is an arrangement structure of electrodes shown in Fig. 24, and the number of layers including all the electrodes of the DC bias application electrode and the capacitance acquisition electrode is 500. On the other hand, the sample ηι is an arrangement structure of the electrodes shown in FIG. 2, and includes all of the electrodes for the second and second capacitor-acquisition electrodes and the electrodes for the i-th and second DC bias application electrodes. The range of capacitance change when the DC bias voltage was changed from 〇 to 36 V for the samples 111 and 112 is shown in Table 2.内32 1331759 [Table 2] Outside: Table J shows that when the sample 1" within the scope of the present invention is compared with the paradigm 112 of the present invention, the size of the capacitor is the same and the number of electrodes is the same degree. The inventive capacitor can achieve a larger capacitance and can make the variable amplitude of the capacitor wider.

Although the fourth to sixth embodiments of the second type of the present invention have been described above with reference to Figs. 10 to 14, a variety of other modifications are possible within the scope of the present invention. For example, the positional relationship between the capacitor-acquisition electrode and the DC-bias-applied electrode which are provided on the same surface, and the DC bias can be applied by the mutually opposing and second DC bias application electrodes. The position of the capacitance forming region of the dielectric layer between the electrodes for the second and second valley acquisition electrodes

The relationship may be other than the positional relationship of the embodiment shown in the figure. Further, the first and second capacitor-applied terminal conductor films and the first and second capacitor-acquisition terminal conductor films are respectively disposed on the capacitor body at the position 'in accordance with the first and second capacitor-acquisition electrodes, The respective positions of the first and second DC bias application electrodes are arbitrarily changed. Further, in the fourth to sixth embodiments, the first and second capacitor-acquisition electrodes 124 and 125 and the first and second DC bias-applying electrodes 127 and 128 are formed inside the capacitor body 123, but If there is no problem of moisture resistance, at least one of the first capacitor-acquisition electrodes and the first DC bias 33 1331759 electrode and the second DC bias are applied to the outer surface. The pressure application electrode or the second capacitance acquisition electrode may be formed in the capacitor body (the third type of embodiment). FIG. 15 and FIG. 16 are used to find the seventh embodiment of the present invention. Electricity

21, (4) is a view corresponding to FIG. 24 or FIG. %, showing a front view of the capacitor 221 'b) to (d) with a cross section facing the lamination direction of the dielectric layer 222. Fig. 25 corresponds to the figure, showing the top view of the capacitor m with the wearing surface extending in the direction of the main surface of the dielectric 222, and Fig. 16 is an equivalent circuit diagram when the electric bar 221 applies a DC bias. As shown in Fig. 15 (4), the capacitor 221 is provided with a capacitor body (2) having a laminated structure composed of a plurality of dielectric layers 222. The capacitor body 223 includes: the second capacitor-capturing electrodes 224 and 225 are disposed to face each other through a specific dielectric layer 222 to form a capacitance; and the first & second DC bias application The electrodes 227 and 228 are used to apply a DC bias voltage to the capacitance forming region 226 of the dielectric layer 222 between the first and second capacitance obtaining electrodes 224 and 225. The first and second DC bias application electrodes 227 and 228 are provided on the same main surface of the same dielectric layer 222 sandwiched between the first and second capacitance acquisition electrodes 224 and 225. Therefore, the DC bias voltage applied to the i-th and second straight-flow bias application electrodes 227 and 228 faces the main surface of the dielectric layer 222. In this embodiment, two dielectric layers 222 are formed between the i-th and second capacitor-acquisition electrodes 224 and 225, and the i-th and second DC bias are applied along the interface between the two layers of dielectric 34 1331759 22 . Electrodes 2" and 228. The position of the second capacitor-acquisition electrode (2) is shown by a broken line in Fig. 15(c). From here, the second capacitor-acquisition dragon (2) and the second and second DC bias application electrodes are provided. In the positional relationship between 227 and 228, the i-th and second DC bias application electrodes 227 and 228 are disposed in the main surface direction of the dielectric layer so as not to form the capacitance region 226 (see FIG. 15(a)). In this way, the first and second capacitor-capturing electrodes (2) and 225 can prevent the capacitance characteristics from being stabilized by the DC bias application electrodes 227 and 228. As a result, the first and second states can be stabilized. The positional relationship between the capacitance-acquisition electrodes 224 and 225 and the first and second DC bias application electrodes 227 and 228 is such that the first and second capacitors are obtained when viewed in a cross section facing the stacking direction of the dielectric layer 222. The electrodes 224 and (2) do not appear in the first and second DC bias application electrodes 22 7 and 228 are the same cross-sections. Therefore, it should be understood that the capacitor 221 is not shown in a single cross section in Fig. 15(a), and the capacitance obtaining electrodes 224 and 225 and the DC bias applying electrode 227 are more clearly shown. And the positional relationship of 228 in the lamination direction, so that a plurality of cross sections are displayed. The capacitor body 223, as clearly shown in Figs. 15(b) to (d), is a rectangular parallelepiped having four side faces 229 to 232 extending in the lamination direction. The first DC bias application terminal conductor film 233 is provided on the i-side 229. The second DC bias application terminal conductor film is provided on the second side surface 230 opposite to the first side surface 229. 234. The third side surface 231 adjacent to the first and second side faces 229 35 1331759 and 230 is provided with a first capacitor-acquisition terminal conductor film 235. The fourth side surface (3) facing the third side surface 231 The second capacitor-acquisition terminal conductor film 236 is provided with a cross section through which the first capacitor-acquisition electrode 224 passes. The first valley-acquisition electrode 224 is pulled out to the first portion. The side surface 231 is electrically connected to the first capacitor-acquisition terminal conductor film 235.

The cross section through which the i-th and second DC bias application electrodes and 228 pass is shown in Fig. 15(c)'. The first DC bias application electrode 227 is pulled out to the first side ® 229 'here, and is electrically connected to the ith DC bias application terminal conductor film 233. The second DC bias application electrode 228 is pulled out to the second side surface 230, and is electrically connected to the second DC bias application terminal conductor film 234. The cross section through which the second capacitance obtaining electrode 225 passes is shown in Fig. 15 (d)'. The second capacitance acquisition electrode 225' is pulled out to the fourth side surface 232, and is electrically connected to the second capacitance acquisition terminal conductor film 236. In the capacitor 221 having the above configuration, as shown in FIG. 16, the electrostatic capacitance formed between the first and second capacitance-capturing electrodes 224 and 225 is obtained from the first and second capacitor-acquisition terminal conductor films 235 and 236 was taken out. The first and second capacitor-capturing terminal conductor films 235 and 236 are electrically connected to a predetermined circuit (not shown). At this time, when the DC bias voltage 237 is applied between the first and second DC bias application electrodes 227 and 228 by the second and second DC bias application terminal conductor films 233 and 234', the first and second DC bias application electrodes are located between the first and second DC bias application electrodes 227 and 228. The dielectric characteristics of the capacitance forming region 226 (see FIG. 15(a)) of the dielectric layer 222 between the second capacitance obtaining electrodes 224 and 225 are changed. The result of the change in the capacitance of the first and second capacitor-capturing terminal conductor films 235 and 236 can be changed. In order to make the variation of the electrostatic capacitance larger, the dielectric layer 222, particularly the dielectric layer 222 constituting the capacitance forming region 226, is preferably made of a material having a large DC bias dependence of dielectric characteristics. Thus, as a material having a large DC bias dependence as a dielectric property, for example, lOOBa, 〇〇6(Ti〇972r〇〇3)〇3 _ 2.5Gd03//2~2.5Mg〇—0.5Mn〇—l .〇Si〇2. Next, an experimental example 5 in which the effects of the seventh embodiment are performed will be described. Thus, a sample having substantially the same structure as the capacitor 221 shown in FIG. 15 is produced as an embodiment within the scope of the present invention. A sample of the sample 201 was prepared, and a sample having the same constitution as that of the capacitor 4 shown in Fig. 24 as a comparative example outside the scope of the present invention was produced. These ancient rabbits 1 and 202 use BaTl〇3 high dielectric constant ceramic material as the dielectric body constituting the dielectric layer, and the thickness of the dielectric layer between the electrodes = again, the electrode is made of nickel The main component has a thickness of iym. Further, the external dimensions of each of the main bodies were 3.2 mm×1.6 mm×〇.4 mm » and the respective capacitors 201 and 202 of the outer and outer electrodes were subjected to a capacitance change rate when a plurality of DC biases in the target circumference of 〇 36 w were applied. Generally, when a DC bias voltage is applied to a dielectric body, the capacitance change rate is constant on a certain application 蕙坌U. In Fig. 17, it can be seen that in the sample 2〇1, in the paired DC bias application, since the electrode (conductor layer) capable of shielding the electric field does not exist, the capacity change rate caused by the suppression of the electric field strength can be suppressed by 37 1331759. As a result, as compared with the sample 202, a large capacitance change rate can be obtained. • In addition, in the above Experimental Example 5, a specific dielectric constant ceramic material of the BaTi〇3 type is used as the dielectric body constituting the dielectric layer, but the ceramic material “DC bias using dielectric characteristics” When the pressure-dependent material is larger, it can be confirmed that an electric-container having a wider range of capacitance variation to a DC bias can be obtained. Fig. 18 is a view showing a capacitor 221a' according to the eighth embodiment of the present invention and corresponding to Fig. 15(c). In FIG. 18, the same reference numerals will be given to the same components as those in FIG. 15 and the overlapping description will be omitted. The capacitor 221a of the eighth embodiment is compared with the capacitor 221 of the seventh embodiment. The positions of the application electrodes 227 and 228 are different. That is, the first and second DC bias application electrodes 227 and 228 are characterized by the position of the capacitance acquisition electrode 225 shown by a broken line in Fig. 18, which is characterized in that The position in the main surface direction of the dielectric layer 222 is set to overlap with the electric valley forming region 226 (see Fig. 15 (a)). By adopting such a configuration, it is compared with the capacitor 221 of the seventh embodiment. In the following, since the distance between the first and second DC bias application electrodes 227 and 228 can be shortened, even if a lower voltage is applied as a DC bias, the effect of capacitance change can be obtained. In the embodiment of the present invention, the capacitors 221b of the ninth embodiment are denoted by the same reference numerals and the description thereof will not be repeated. i and the second DC Pressure 38 1331759 The formation of the application electrodes 227 and 228 is characterized in that the first and second DC bias application electrodes 227 and 228 are formed at the ends in the longitudinal direction of the dielectric layer 222. Further, as is clear from Fig. 9 (a), the first and second DC bias application electrodes 227 and 228 are arranged such that the disk formation region 226 overlaps. Therefore, according to the ninth embodiment, In the case of the embodiment, the first and second capacitor-acquisition electrodes 224 and 225 are not sandwiched between the DC bias application electrodes 227 and 228, so that the capacitance characteristics can be stabilized. Fig. 20 shows a tenth embodiment of the present invention. Capacitor 221c, Fig. 2(a) corresponds to Fig. 15(a) or Fig. 19(a), and Fig. 2(b) corresponds to Fig. 15(c) or Fig. 19(c). The components that are the same as those of the components shown in Fig. 15 or Fig. 19 are denoted by the same reference numerals and the description thereof will not be repeated. The capacitor 221c' of the first embodiment has characteristics in the formation of the DC bias application electrodes 22 7 and 228. In other words, the i-th and second DC bias application electrodes 227 and 228 are electrically connected to the ninth embodiment. Similarly to the dielectric layer 222, the 221b is placed in the main surface direction of the dielectric layer 222 so as to overlap the electric valley forming region 226. Therefore, as in the case of the capacitor 221a of the eighth embodiment, the first and The distance between the second DC bias application electrodes 227 and 228 results in an effect of capacitance change even if the applied voltage as a DC bias is low. Fig. 2 shows the third embodiment of the present invention. The capacitor 22 丨d of the form corresponds to FIG. 15 or FIG. In FIG. 2i, the same reference numerals are given to the same reference numerals as those in FIG. 39 1331759 The capacitor 221d of the η embodiment is characterized by the shape of the DC bias application electrodes 227 and 228. That is, the i-th DC bias application electrodes 227 and 228' are clearly shown in Fig. 21(c) as comb-tooth shapes in which a plurality of electrode fingers 238 and 239 are formed in parallel. Further, each of the electrode fingers 238 included in the first DC bias application electrode 227 is located between each of the electrode fingers 239 included in the second DC bias application electrode 228. According to the eleventh embodiment, the opposing area can be increased while maintaining the short distance between the first and second DC bias application electrodes 227 and 228. Fig. 22 and Fig. 23 show capacitors 241 and 251 of the twelfth and thirteenth embodiments of the present invention, respectively, and correspond to Fig. 15(a). It is to be noted that the same reference numerals are given to the elements in the drawings, and the description thereof will be omitted. The capacitors 241 and 251 of the twelfth and thirteenth embodiments are characterized in that the capacitor body 223 is formed with a plurality of ith capacitor acquisition electrodes 224, a second capacitor acquisition electrode 225, and a first DC bias application. The electrode 227 and the second DC bias application electrode 228 are used. More specifically, in the capacitor 241 of the twelfth embodiment shown in FIG. 22, the first capacitor acquisition electrode 224, the DC bias application electrodes 227 and 228, and the second capacitor acquisition electrode are formed from the upper side in the lamination direction. The order of 225 is repeated in a plurality of times. The capacitor 251 of the thirteenth embodiment shown in FIG. 23 starts from the upper side in the lamination direction, and the first capacitor obtaining electrode 224, the DC bias 40 1331759 pressure applying electrode 227, and 228. The order of the second capacitor obtaining electrode 225, the DC bias applying electrodes 227 and 228, and the ith capacitor obtaining electrode 224 is repeated a plurality of times. Further, when the capacitor body 223 of the capacitor 241 shown in FIG. 22 and the capacitor body 223 of the capacitor 251 shown in FIG. 23 are compared, the thickness direction dimension is different, but this is only the electrode to be illustrated. The results of the different numbers of 224, 225, 227, and 228, the difference in the thickness direction of the figure, are not of special significance. Next, it is explained that, as described above, the capacitors 241 and 251 have a complex array in the capacitor body 223! When the capacitor acquisition electrode, the second capacitance sensing electrode 225, the first DC bias application electrode 227, and the second DC bias application power 35528 are described, it is confirmed that the capacitor "per unit volume of static electricity according to the present invention" The capacity will become larger, & smaller and more capacitive, and the lower voltage static capacitance can be controlled in a wider range of experimental examples.

In the sixth experimental example, the capacitors of the sample of the example 2 in the range of the present invention and the sample 212 of the comparative example outside the scope of the present invention were produced, but the material and thickness of the dielectric layer of each capacitor, and the material of the electrode and The yield was the same as in Experimental Example 5 above. X, the sample 211 of this experimental example and the external dimensions of the capacitors are all 3_2 mmxl 6 mmxi 6_. More specifically, in the sample 212, the number of layers of the electrode including the DC bias|application electrode and the capacitor acquisition electrode was 500. On the other hand, the sample 211 has the arrangement structure of the electrodes shown in Fig. 22, and includes the number of layers of all the electrodes of the electrode for the second DC bias application, including the electrode for the second capacitor and 41, 31, 31,759, =1. Samples 2H and 212 show the range of capacitance change when the DC bias voltage is changed from 〇 to 36 V. (Table 3) Sample number capacitance variation range 211 6.8 to 41.0 212 20.5 to 27.3 - As is apparent from Table 3, when the sample 211 within the scope of the present invention is compared with the sample 212 outside the scope of the present invention, the size of the capacitor is In the case where the number of laminated layers of the electrodes is the same, if the capacitor according to the present invention, a larger capacitance can be obtained and the variable width of the capacitor can be made wider. Although the seventh to thirteenth embodiments of the third type of the present invention have been described above with reference to Figs. 15 to 23, other various modifications are possible within the scope of the present invention. For example, the positional relationship between the capacitor-acquisition electrode and the DC bias-applying electrode can be achieved by mutual opposition! And 帛2 DC bias application electrode, the DC bias is applied to the positional relationship of the capacitance formation region of the dielectric layer between the second and second capacitance acquisition electrodes, and the positional relationship of the embodiment as shown in the figure Other location relationships are also possible. Further, the positions of the first and second DC bias application terminal conductor films and the first and second capacitor acquisition terminal conductor films on the capacitor body are respectively provided, and the first and second capacitance acquisition electrodes can be used. The respective positions of the first and second DC bias application electrodes are arbitrarily changed. 42 丄幻1759 The two electric valley obtaining electrodes 224 and 225 and the first and second DC biasing application electrodes such as = coffee are formed inside the capacitor body 223, but if there is no problem of moisture resistance, they are located. The electrode having the outermost edge in the stacking direction is, for example, FIG. 15 (the second and/or second capacitor-acquisition electrodes 224 and/or 225 of the capacitor 221 may be formed on the outer surface of the capacitor body. Description]

Figure 1 is a diagram for explaining the present invention! The capacitors 2, (4) of the embodiment show a front view of the capacitor 2ι in a cross section facing the lamination direction of the dielectric layer 22, and (b) to (d) are sections extending in the direction of the main surface of the dielectric layer 22. A top view of the display capacitor 21 shows mutually different cross sections. Fig. 2 is an equivalent circuit diagram when a DC bias voltage is applied to the capacitor 2 丨 shown in Fig. 。. Fig. 3 is a comparison of the respective capacitance change rates of the sample 作为 as the sample and the sample 2 as the comparative example, which were obtained in the test example 1 in which the effect of the second embodiment was confirmed. Fig. 4 is a view showing a capacitor 41 according to a second embodiment of the present invention, and corresponds to Fig. 1(a). Fig. 5' shows a capacitor $1 according to the third embodiment of the present invention, and corresponds to Fig. 1(a). FIG. 2A shows a capacitor 21a according to a first modification of the first embodiment of the present invention, and (a) shows a front view of the capacitor 21a in a cross section facing the laminated direction of the dielectric layer 22, (b) ~(d) shows a top view of the capacitor 21a in a cross section extending in the direction of the main surface of the dielectric layer 22, and a cross section of 43 shows the capacitor rfij 〇 Figure 16, which is equivalent to applying a DC bias voltage to the figure. Circuit diagram. In the experimental example 5 which was carried out by comparing the effects of the seventh embodiment with respect to the effect of the seventh embodiment, the sample 2 〇1 which is obtained as an example and the test as a comparative example were compared. The change rate of each capacitor of sample 202.

Fig. 18 shows a capacitor 221a of the embodiment of the present invention 8 and corresponds to Fig. 15(c). Fig. 19 shows a capacitor 221b according to a ninth embodiment of the present invention, and corresponds to Fig. 15. Fig. 20' shows a capacitor 221 (&) and (b) according to the first embodiment of the present invention, which correspond to Figs. 15 (a) and (c), respectively. Fig. 21' is a view showing a capacitor 22id according to the ηth embodiment of the present invention, and corresponds to Fig. 15.

The top view of 221' shows a capacitor 221 which is different from each other. Fig. 22' shows a capacitor 241 according to a twelfth embodiment of the present invention, and corresponds to Fig. 15(a). Fig. 23 is a view showing a capacitor 25 1 according to a thirteenth embodiment of the present invention, and corresponds to Fig. 15 (a). Fig. 24' shows a conventional capacitor 1 and corresponds to Fig. i(a). Fig. 25' is a plan view showing the capacitor 1 shown in Fig. 24, showing the mutually different cross sections, with the wearing surface extending in the direction of the main surface of the dielectric layer 2. Fig. 26' shows another conventional capacitor ia and corresponds to Fig. 1(a). 45 Ϊ331759 [Description of main component symbols] 2 1,41,5 1,12 1,141,1 5 1,221,22 la522 1b,221c,221 ¢1,241,251 Capacitor 22,122,222 Dielectric layer 23,123,223 Capacitor body 24 Grounding electrode 25,127,128,227,228 DC bias application Electrode 26, 124, 125, 224, 225 Capacitance acquisition electrode 27, 129, 229 First side 28, 130, 230 Second side 29, 13 1, 231 Third side 30, 132, 232 Fourth side 31 32, 133, 134, 233, 234 33.135.235 34.136.236 37.137.237 Terminal conductor film for DC bias application terminal conductor film 1 terminal conductor film for capacitor acquisition second terminal acquisition terminal conductor film DC bias 238, 239 electrode finger 46

Claims (1)

1331759 X. Patent Application Range: 1. A capacitor comprising: a capacitor body having a laminated structure composed of a plurality of dielectric layers; the capacitor body comprising a grounding electrode, along a specific The dielectric layer is provided; the DC bias application electrode is opposed to the ground electrode through the specific dielectric layer, and is configured to apply a DC bias voltage a and a capacitance between the ground electrode and the ground electrode. The electrode is disposed so as to be sandwiched between the DC bias application electrode and the ground electrode, and the specific dielectric layer is opposed to the ground electrode to form a static capacitance; Further, the grounding terminal conductor film ' is disposed on the outer surface of the capacitor body' and electrically connected to the grounding electrode; the DC bias application terminal conductor film 'is disposed on the outer surface of the capacitor body' And electrically connected to the DC bias application electrode; and the first capacitor acquisition terminal conductor film is provided outside the capacitor body Surface, and electrically connected to the capacitor electrode made. 2. The capacitor according to the first aspect of the invention, further comprising a second capacitor-acquisition terminal conductor film provided on an outer surface of the capacitor body and electrically connected to the ground electrode; the capacitor body has a The terminal conductor film for grounding is provided on the first side surface of the four side faces extending in the stacking direction, and the DC bias application terminal conductor film is provided on the second side opposite to the first side surface. The first capacitor 47 ^ 31759 is obtained by providing the terminal conductor film on the side surface adjacent to the first and second side faces, and the second capacitor-acquisition terminal conductor film is provided in the shai The third side faces the fourth side of the direction. 3. The capacitor of claim 1, wherein at least the dielectric layer between the electrode for grounding and the electrode for applying the DC bias is a material having a large direct current bias dependence of dielectric characteristics. Composition. 4. The capacitor according to any one of claims 3 to 3, wherein the capacitor body comprises a plurality of the grounding electrodes, the DC bias applying electrode, and the capacitor obtaining electrode. A capacitor comprising: a capacitor body; the capacitor body having a laminated structure composed of a plurality of dielectric layers; the capacitor body including a second and second capacitor-acquisition electrodes, which are further configured to transmit Specifically, the dielectric layers are opposed to each other to form an electrostatic valley, and the first and second DC bias application electrodes are used to apply a DC bias voltage to the first and second capacitor acquisition electrodes. a capacitance forming region of the dielectric layer; the first DC bias applying electrode is provided on the same main surface as the main surface of the dielectric layer on which the first capacitor obtaining electrode is provided, &quot The second DC bias application electrode is provided on the same main surface as the main surface of the dielectric layer on which the second capacitance acquisition electrode is provided, and further includes: first and second DC biases The terminal conductor film for application is provided on the outer surface of the electric benefit body and electrically connected to the first and second straight electrodes, and the first and second capacitor terminal conductors. Membrane Disposed on the outside surface of the capacitor body and electrically connected to the first and second capacitor electrode made. The capacitor of the fifth aspect of the invention, wherein the first DC-acquisition-using electrode is located on the side of the first DC-bias-applied electrode, and the second DC-bias is opposite to the second capacitor-acquisition-electrode The side where the electrode for pressure application is located is the opposite side. 7. The capacitor of claim 5, wherein the capacitor body has a rectangular parallelepiped shape having four side faces extending in a lamination direction, and the first DC bias application terminal conductor film is disposed on the side of the second side. The second DC bias application terminal conductor film is provided on the second side opposite to the second side surface. The terminal capacitor film for obtaining the capacitance is provided adjacent to the first and second side faces. On the third side, the second capacitor-acquisition terminal conductor film is provided on the fourth side opposite to the third side surface. 8. The capacitor of claim 5, wherein at least the dielectric layer constituting the capacitance forming region is made of a material having a large DC bias dependence of dielectric characteristics. The capacitor according to any one of claims 5 to 8, wherein the capacitor body includes the plurality of the second capacitor obtaining electrodes, the second capacitor obtaining electrode, and the second DC bias voltage The application electrode and the second DC bias application electrode. 10. A capacitor comprising: a capacitor body having a laminated structure comprising a plurality of dielectric bodies 49 1331759; the capacitor body including first and second capacitor obtaining electrodes; And forming a static capacitance through the specific dielectric layers facing each other; and the first and second DC bias applying electrodes for applying a DC bias voltage to the second and second capacitors a region in which the dielectric layer of the dielectric layer is formed between the electrodes; and the first and second DC bias application electrodes are provided in the same dielectric layer sandwiched between the first and second capacitor-acquisition electrodes. Further, the first and second DC bias application terminal conductor films are provided on the outer surface of the capacitor body, and are electrically connected to the second and second DC biases, respectively. The electrode and the first and second capacitor-acquisition terminal conductor films are provided on the outer surface of the capacitor body, and are electrically connected to the first and second capacitor-acquisition electrodes, respectively. 11. The capacitor of the first aspect of the invention, wherein the j-th and second DC bias application electrodes are disposed so as not to overlap the capacitance formation region in the main surface direction of the dielectric layer. 12. The capacitor according to the first aspect of the invention, wherein the first and second DC bias application electrodes are disposed to overlap the capacitance formation region at a position in a direction of a main surface of the dielectric layer. 13. The capacitor according to claim 10, wherein the first and second DC bias application electrodes are comb-shaped teeth forming a plurality of parallel electrode fingers, and the first DC bias is applied. Each of the 50 丄川/59 series portions of the electrode is inserted between the respective electrode fingers of the instrument represented by the second DC bias application electrode. Eight . . 14. The capacitor of claim 1, wherein the capacitive body is a rectangular parallelepiped having four sides extending in the lamination direction, and the terminal conductor film for applying a DC bias voltage is provided on the side of the first side. On, The second DC bias application terminal conductor film is provided on the second side opposite to the first side surface, and the second capacitor-acquisition terminal conductor film is provided adjacent to the first and second side faces. On the third side, the second capacitor-acquisition terminal conductor film is provided on the fourth side opposite to the third side surface. 15. The capacitor of claim 1, wherein at least the dielectric layer constituting the capacitance forming region is made of a material having a large DC bias dependence of dielectric characteristics. 16. The capacitor of any one of clauses 1 to 15, wherein the capacitor body includes the first capacitor acquisition electrode, the second capacitor acquisition electrode, and the first capacitor The DC bias application electrode and the second DC bias application electrode. Η , Schema: as the next page 51