WO2007113764A1 - Procédé et système de gestion du signal - Google Patents

Procédé et système de gestion du signal Download PDF

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Publication number
WO2007113764A1
WO2007113764A1 PCT/IB2007/051161 IB2007051161W WO2007113764A1 WO 2007113764 A1 WO2007113764 A1 WO 2007113764A1 IB 2007051161 W IB2007051161 W IB 2007051161W WO 2007113764 A1 WO2007113764 A1 WO 2007113764A1
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WO
WIPO (PCT)
Prior art keywords
voltage
current
transistor
gate
output signal
Prior art date
Application number
PCT/IB2007/051161
Other languages
English (en)
Inventor
Joseph Rutkowski
Original Assignee
Nxp B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp B.V. filed Critical Nxp B.V.
Publication of WO2007113764A1 publication Critical patent/WO2007113764A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/042—Modifications for accelerating switching by feedback from the output circuit to the control circuit
    • H03K17/04206—Modifications for accelerating switching by feedback from the output circuit to the control circuit in field-effect transistor switches

Definitions

  • the present invention relates generally to a method and system for controlling an output signal and, more particularly, to the implementation of a circuit for controlling the signal-driving characteristics of an output signal.
  • Interconnections to transmit information between components of the system.
  • Such interconnections generally consist of one or more signal lines that taken together are also know as bus.
  • To transmit the information the components of the system must drive the voltage level of the bus line to the appropriate level.
  • bus specifications that limit how fast or slow the voltage can change in a particular system.
  • some systems use a bus protocol known as the Inter-Integrated Circuit bus, or I 2 C bus.
  • the I 2 C bus is a control bus that provides the communications link between integrated circuits in a system.
  • This simple two- wire bus with a software-defined protocol has evolved to become the de facto worldwide standard for system control, finding its way into everything from temperature sensors and voltage level translators to EEPROMs, general-purpose I/O, A/D and D/A converters, CODECs, and microprocessors of all kinds.
  • titled, "Two-Wire Bus-System Comprising a Clock Wire and a Data Wire for Interconnecting a Number of Stations” describes a computer system that comprises a number of station which are interconnected by means of a clock bus wire and a data bus wire that form a wired logic bus that is a function of the signals generated thereon by the stations, and is incorporated by reference in its entirety.
  • the I 2 C -bus also saves space and lowers overall cost. Using I 2 C specification, designers can move quickly from a block diagram to final hardware, simplifying the addition of new devices and functions to an existing bus interface. As the system evolves over several generations, I 2 C devices can easily be added or removed without impacting the rest of the system.
  • the two-line structure means fewer trace lines, so the PCB can be much smaller. Debug and test are easier, too, since there are fewer trace lines and a relatively simple protocol.
  • Standard mode up to 400 KHz in Fast mode, up to 1 Mhz in Fast mode plus and up to 3.4 MHz in High-Speed mode.
  • the on-chip I 2 C interface includes an open drain n-channel metal-oxide-semiconductor field-effect transistor (NMOS) pull-down device while a single pull-up resistor is common to all devices on the I 2 C bus.
  • NMOS metal-oxide-semiconductor field-effect transistor
  • the specification requires maximum edge transitions for the bus signals. The maximum rising edge transition can be met be selecting a suitably small pull-up resistor.
  • the Fast Mode Plus specification requires the maximum falling-edge transition (70%-30%) to not exceed 120ns.
  • the minimum falling edge transition (70%-30%) cannot occur in less than 20ns.
  • the NMOS pull-down device must be capable of controlling the edge rate to provide a falling-edge transition within the maximum and minimum requirements. This requirement is further complicated because the pull-up resistor values and bus capacitance values vary from one I 2 C mode to another and also from one I 2 C bus application to another.
  • One method used to control the edge rate of an NMOS pull-down device is to control the current supplied to the gate of the NMOS device.
  • some conventional edge rate limited techniques require a continuously available current source, which comes at the cost of chip supply current.
  • continuously available current sources do not scale well with changes in supply voltage. This presents problems with the I C (and other) bus specification, which allows the user to define the part voltage as well as the bus voltage.
  • Another slew rate limiting technique uses a resistor network.
  • the classical resistor limited current approach has little static current once the transition is complete; however, it produces a nonlinear, RC falling edge with a slow turn-on.
  • Various aspects of the present invention are directed to methods and arrangements for output signal control in a manner that addresses and overcomes the above-mentioned issues.
  • an output signal is controlled using a circuit arrangement.
  • the circuit arrangement has a transistor with a gate coupled to a capacitor and with an output coupled to the output bus signal and the capacitor.
  • a current source is coupled to the gate of the transistor.
  • the current source is configured to selectively provide an amount of current in response to an input signal and to vary the amount current provided in response to a feedback signal.
  • a feedback circuit provides the feedback signal to the current source and varies the feedback signal in response to a voltage at the gate of the transistor.
  • a method for controlling an output signal is implemented.
  • a first current amount is provided to a gate of a transistor.
  • the gate is coupled to a capacitor and an output of the transistor is coupled to the output signal and to the capacitor.
  • a second current amount is provided in response to a voltage at the gate of the transistor reaching a reference voltage.
  • FIG. 1 is a block diagram of an output-signal control system, according to an example embodiment of the present invention.
  • FIG. 2 is a circuit schematic diagram of an output-signal control system, according to an example embodiment of the present invention.
  • the present invention is believed to be applicable to a variety of edge-rate control devices and approaches. While the present invention is not necessarily limited to such applications, an appreciation of various aspects of the invention is best gained through a discussion of examples in such an environment.
  • a circuit arrangement for controlling the edge-rate of a signal.
  • the circuit arrangement includes a transistor for driving an output signal and a capacitor connected between the output signal and the gate of the transistor.
  • a current source is coupled to the input of the pull-down transistor and is configured to supply current to the gate of the pull-down transistor in response to an enabling input signal. When enabled, the current source varies the amount of current supplied in response to a feedback signal provided by a feedback circuit.
  • the feedback circuit varies the feedback signal in response to a voltage at the gate of the pull-down transistor.
  • an I 2 C bus interface is implemented using device having an N-channel metal-oxide semiconductor field-effect transistor (NMOS) pull-down.
  • NMOS metal-oxide semiconductor field-effect transistor
  • a current source charges a feedback capacitor that is coupled between the output and the gate of the NMOS pull-down.
  • This configuration is particularly useful for ensuring that the edge rate for a high-to-low transition on the I C bus meets the minimum edge rate requirements.
  • the current source increases the amount of current supplied to the gate of the NMOS pull-down. This current increase is implemented only after the voltage on the gate of the NMOS pull-down reaches a certain voltage or 'trip point'. This configuration is particularly useful for ensuring that the edge rate is between a minimum and maximum rates.
  • the increased current amount can be selected based upon maximum expected load conditions as well as the drive capabilities of the NMOS pull-down. In applications having a low load, if the trip point is not carefully selected, the increased current level could cause the edge rate to violate the minimum required timing.
  • the time required to reach the trip point is a direct function of the feedback capacitor and the current provided. Thus, the selection of the trip point voltage can be selected to avoid too fast of an edge rate by guaranteeing the current will not be increased until after a minimum charge time.
  • the current source is implemented using a variable resistor or a resistor network.
  • the current is varied by changing the effective resistance of the variable resistor or resistor network.
  • an NMOS or similar transistor device can be electrically connected in parallel with one or more resistors in the resistor network.
  • the parallel resistor is bypassed effectively reducing the resistance of the resistor network.
  • the circuit controls the voltage applied to the resistor network independent of the supply voltage. For example, the voltage drop of a diode, transistor or similar device can be electrically connected in parallel with the resistor network thereby maintaining a relatively constant voltage regardless of the supplied voltage.
  • FIG. 1 shows a block diagram of an edge rate control circuit according to an example embodiment of the present invention.
  • the diagram contains input 101, current source 102, feedback control 104, capacitive feedback 106, signal driver 108 and load 110.
  • the circuit drives a signal connected to load 110 in response to input 101.
  • Load 110 represents the resistive, capacitive and inductive components related to the output signal connected to signal driver 108.
  • the load is affected by the pull-up resistor value, the pull-up voltage, the capacitance of the various devices connected to the system and the interconnections between the devices of the system.
  • the pull-up resistor value and voltage can vary from application to application.
  • the pull-up resistor values are sometimes stronger (less resistance) for a fast mode plus system than for a standard mode system.
  • the number of devices in the system as well as the devices' individual load characteristics can vary significantly from system to system.
  • the edge rate control circuit is configured to accommodate different loads on signal driver 108 and different I 2 C modes. For instance, the edge rate control circuit is configured to handle two load situations, a small load and a large load. Where load 110 is relatively small, signal driver 108 is capable of producing an edge rate that may be too fast for the specification. For such a load, signal driver 108 is limited by capacitive feedback 106.
  • Current source 102 provides a current that creates a voltage on the input of signal driver 108 by charging capacitive feedback 106. Once the voltage reaches a threshold voltage (e.g., the gate voltage necessary for the device to conduct electricity), signal driver 108 becomes active and continues to increase its drive capabilities as the input voltage increases.
  • a threshold voltage e.g., the gate voltage necessary for the device to conduct electricity
  • the resulting change in the output voltage (dv/dt) affects the gate voltage by reducing the gate voltage as a function of dv/dt through capacitive feedback 106.
  • the change in output voltage counteracts increased input voltage due to current source 102.
  • the edge-rate control circuit maintains a minimum edge rate based upon the current provided by the current source and the capacitance of the capacitive feedback 106.
  • the current source 102 begins charging the capacitive feedback 106 and the voltage differential increases across the input and output of the signal driver 108. Due to the large load, the change in voltage on the output signal slow, causing the gate voltage to continually increase. Where the load is sufficiently large, the rate at which the output voltage changes may be insufficient to meet the maximum edge rate. Thus, feedback control 104 senses such a condition (e.g., by monitoring the gate voltage) and provides feedback to the current source 102. In response to the feedback, current source 102 increases the current provided to the signal driver 108. The increased current results in an increased edge rate allowing the edge rate control circuit to meet the maximum edge rate requirement.
  • the current source 102 uses a resistor network and a voltage regulator to control the current supplied. For example, a voltage is applied to the resistor network resulting in a current I. In response to the feedback control 104, the resistance of the resistor network is changed resulting in a change in current I.
  • a voltage regulator determines the voltage applied to the resistor network, such as using one or more diodes and/or transistors to produce the voltage. This can be particularly useful for implementing an edge control circuit that works using variable supply voltages.
  • the current source can modify the current supplied by changing the resistance of the resistor network and the voltage applied to the resistor network.
  • the current from current source 102 is provided using a voltage drop or threshold voltage of a diode, transistor, or similar device, and the feedback control is configured to detect when the voltage at the gate nears the supply voltage. In response to detecting such a voltage, feedback control 104 provides a feedback signal to current source 102.
  • Current source 102 reduces the effective resistance of a resistor network used (in conjunction with the voltage drop) to generate the supplied current. This can be particularly useful to counteract the effects of the diode or transistor operating near its threshold voltage due to the voltage at the gate of signal driver 108 approaching the supply voltage of the device.
  • FIG. 2 shows a schematic diagram of a specific edge rate control circuit, according to an example embodiment of the present invention.
  • FIG. 2 contains device M5 for driving the output, feedback capacitor CO, resistor network (Rl and R2), and feedback switch Mil.
  • Device MlO and the resistor pair Rl and R2 are used to create a current source independent of the voltage supply.
  • device MlO When active, device MlO provides exhibits a voltage from source to gate equal to a threshold voltage.
  • the resistor network consisting of series resistor pair Rl and R2, is connected between the source and gate of device MlO. Accordingly, the effective charging current is VtZ(R 1+R2) as device MlO shunts current, which would otherwise cause the gate voltage to exceed the threshold voltage, to ground through device M4.
  • the gate of device M4 is coupled to the output voltage, and thus, this path is disabled once the output voltage is within a threshold voltage of ground.
  • the gate of device Mil is connected to the supply voltage of the circuit through resistor R3.
  • Resistor R4 is connected to the drain of device M2.
  • the inverted input signal created by devices M6 and MO ensures that device M2 is active when the input is low.
  • resistors R3 and R4 create a voltage divider that is used to detect when the gate- source voltage of the output device M5 (node n5) is sufficiently above the threshold voltage of the output device. For example, where R3 is equal to R4, device Mi l will remain active until the voltage at node n5 is approximately one-half of the supply voltage. Once the voltage at node n5 reaches this point, device Mi l becomes inactive and node n6 is pulled to ground through resistor R4. Buffer 202 applies the voltage of node n6 to node n7.
  • the output of buffer 202 is either high or low based upon the input at node n6. More specifically, the output is high when node n6 is at or above the voltage determined by R3 and R4 and low when pulled low through R4.
  • the source and drain of device M9 is connected across resistor R2 allowing device M9 to effectively remove resistor R2 from the resistor network by raising the voltage of node N8 to a threshold voltage above node N5.
  • Capacitor CO is used to throttle the output device M5 back when a light load is applied to the output (i.e. large external pull-up resistor and small bus capacitance).
  • Vt_M10 internal pull-up current
  • Rl voltage change from feedback capacitor CO
  • device M8 When the input signal is high, device M8 is inactive and the current draw of the resistor network is at or near zero. Moreover, once the voltage at node n5 reaches a voltage near the supply voltage (e.g., supply voltage - (RO * (MlO threshold voltage * (Rl +R2)) - MlO threshold voltage - M8 threshold voltage), the current draw of the resistor network is near zero. This is particularly useful for minimizing the current draw of the circuit when the output signal driver needs little or no current.
  • supply voltage - (RO * (MlO threshold voltage * (Rl +R2) - MlO threshold voltage - M8 threshold voltage
  • the resistor network contains additional resistors. Moreover, these additional resistors can be selectively enabled to produce additional levels of current draw.
  • a second reference voltage circuit is provided similar to the circuit containing resistors R3 and R4, devices Mil and buffer 202.
  • a second device similar to device M9 can be implemented to effectively remove one or more additional resistors from the resistive network.
  • the second reference voltage circuit can have a different reference voltage so as to allow successive increases in the current provided. In this manner, any number of additional reference voltage circuits can be implemented. This can be useful for providing additional granularity in the control of the supplied current.

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  • Logic Circuits (AREA)

Abstract

La présente invention concerne la gestion d'un signal de sortie mise en oeuvre par divers procédés et dispositifs. En utilisant un tel dispositif, un signal de sortie est géré en utilisant un dispositif de circuit. Le dispositif de circuit comporte un transistor (108) dont une grille est couplée à un condensateur (106) et dont une sortie est couplée au signal de sortie et au condensateur. Une source de courant (102) est couplée à la grille du transistor (108). La source de courant (102) est configurée pour fournir sélectivement une quantité de courant en réaction à un signal d'entrée (101) et pour faire varier la quantité de courant fournie en réaction à un signal de rétroaction. Un circuit de rétroaction (104) fournit le signal de rétroaction à la source de courant (102) et fait varier le signal de rétroaction en réaction à une tension à la grille du transistor (108).
PCT/IB2007/051161 2006-03-31 2007-03-31 Procédé et système de gestion du signal WO2007113764A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US78821106P 2006-03-31 2006-03-31
US60/788,211 2006-03-31
US83027006P 2006-07-11 2006-07-11
US60/830,270 2006-07-11

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WO2007113764A1 true WO2007113764A1 (fr) 2007-10-11

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0596475A2 (fr) * 1992-11-03 1994-05-11 Texas Instruments Deutschland Gmbh Montage servant à commander un transistor à effet de champ du type MOS
JPH09148909A (ja) * 1995-11-17 1997-06-06 Hitachi Ltd 半導体集積回路装置
US5841297A (en) * 1995-07-28 1998-11-24 Texas Instruments Deutschland Gmbh Circuit arrangement for driving an MOS field-effect transistor allocated to the supply circuit of an electrical load
EP0963044A2 (fr) * 1998-06-02 1999-12-08 Nec Corporation Circuit à pente de transition de sortie définie pour commander un transistor de sortie à effet de champ du type MOS
WO2005057788A2 (fr) * 2003-12-11 2005-06-23 Conti Temic Microelectronic Gmbh Procede et dispositif de commutation pour commander un element de charge au moyen d'un element de commutation electronique dans le circuit electrique de charge

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0596475A2 (fr) * 1992-11-03 1994-05-11 Texas Instruments Deutschland Gmbh Montage servant à commander un transistor à effet de champ du type MOS
US5841297A (en) * 1995-07-28 1998-11-24 Texas Instruments Deutschland Gmbh Circuit arrangement for driving an MOS field-effect transistor allocated to the supply circuit of an electrical load
JPH09148909A (ja) * 1995-11-17 1997-06-06 Hitachi Ltd 半導体集積回路装置
EP0963044A2 (fr) * 1998-06-02 1999-12-08 Nec Corporation Circuit à pente de transition de sortie définie pour commander un transistor de sortie à effet de champ du type MOS
WO2005057788A2 (fr) * 2003-12-11 2005-06-23 Conti Temic Microelectronic Gmbh Procede et dispositif de commutation pour commander un element de charge au moyen d'un element de commutation electronique dans le circuit electrique de charge

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TW200820609A (en) 2008-05-01

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