200820609 九、發明說明： 【考务明所屬之技彳，奸領域】— 相關之美國申請案資料 此申請案係主張2006年三月31日提交之較早提交的臨 5日守專利申明案弟60/788，211號標題為“improved Drive Capability in a Zero-Power dissipation Edge Rate Control Circuit,”(零功率耗散邊緣率控制電路中改善之驅動能力）。 發明領域 本發明一般係論及一種用以控制輸出信號之方法和系 10統，以及更明確地說，其係論及一種用以控制輸出信號之 信號驅動特徵的電路之實現體。 【先前技術3 發明背景 電氣系統經常係使用配線在此系統之組件間傳輸資 15訊。此類配線通常係包含有一條或多條信號線，彼等合起 來亦名為匯流排。為傳輸該資訊，上述系統之組件，勢必 要將上述匯流排線之電壓位準，驅動至適當之位準。經常 存在有的匯流排規格，在一個特定之系統中·，限制了電壓 之改變究可多快或多慢。舉例而言，某些系統係使用積體 20電路間匯流排或I2C匯流排之匯流排通訊協定。 I2C匯流排為一種控制匯流排，其可在一個系統内的積 體電路之間提供通訊鏈路。此種1980年初由飛利浦公司所 開發之單純雙金屬線匯流排，係具有一種軟體界定式通訊 協定，且業已演變成系統控制有關之業界世界標準，而自 200820609 溫度感應器和電壓位準轉換器，一路至EEPROMs、通用型 I/O、A/D和D/A轉換器、C0DEG-、和所有種類之微處理器。 Moelands et al之美國專利第4,689,740號標題為“Two-Wire Bus-System Comprising a Clock Wire and a Data Wire for 5 Interconnecting a Number of Stations”（由一條時鐘信號金屬 線和一條資料金屬線所組成用以使許多工作站互連之雙金 屬線匯流排系統），說明了 一種電腦系統，其係包含有許多 工作站，彼等係以一條時鐘信號金屬線和一條資料金屬線 互連，而形成一條線結邏輯匯流排，其為該等工作站在其 10上所產生之信號的一個函數，以及其全文係籍由參照而使 合併。 I2C匯流排亦可節省空間並降低整體成本。使用fc規 格，設計師可迅速自一個方塊圖轉移而找出硬體，以致簡 化了新裝置和功能至一個已有之匯流排界面的添加。隨著 以系、、先、、二過；產代之凟進，〗2C裝置可輕易使增加或移除， 而不傷及該系統之其餘部分。此種雙線結構係意謂較少之 跡線，故其電路板可使小甚多。偵錯和測試亦較容易，因 為其中有的是較少之跡線和相當簡單之通訊協定。 I C匯流排何以已持續超過2〇年，係具有幾項理由。首 20先近年來引進之集線器、匯流排中繼器、雙向開關、和 夕工益，業已增加了該匯流排可支援之裝置的數目，而擴 大了原來文限400 PF之最大匯流排電容的裝置之數目。而 且土叙肢控制式衝突偵測和仲裁，可避免資料毀損並確保 可菲之It處，即使是在複雜之系統中。不過，除性能外， 200820609 其使用很容易。兩條單純線路可使一個系統之所有積體電 -路相連接。任何一個此裝置，可使裝接至_個普通之^ 匯流排，以及任何一個主裝置，可使與任何一個從裝置交 換貧訊。上述之軟體控制式定址方案，可免除對定址解碼 5，體有關之要求，以及在此不㈣要設収除錯外部控制 邏輯，因為其早已由i2c通訊協定提供。此外，該匯流排一 直保持與性能同步，以及爾今提供了使用加增之時鐘信號 速率所實現的四階資料率轉移。舉例而言，該等時鐘信號 速率可使在樣準模態中高達100 kHz，在快速模態中高逹 10 400 kHz，在加快模態中高達i Mhz，以及在高速模態中高 達3·4 Mhz 〇 依據該加快模態規格，晶片級j2c界面，係包含有一個 開路③祕通道金屬氧化物半導體場效f晶體(應沉)下 拉式裝置’同時有-個單-上拉電阻器供該此匯流排上面 15之所有裝置共用。為補償上述加快模態加增之匯流排速 率，其規格要求該等匯流排信號有最大之邊緣變遷。此種 最大之上昇緣變遷，可藉由選擇一個適當之小上拉電阻器 而使滿足。該加快模態規格，要求該最大之下降緣變遷 (70%-3Q%)不超過120nw匕外，為避免對電磁干擾(歷） 2〇和信號反射之敏感，其最小下降緣變遷(7〇%_3〇%)不得在小 於20 ns内發生。θ此，該NM0ST抵裝置，勢必要有能力 控制該邊緣率’藉以在該等最大與最小需求内，提供一個 下降緣變換。此需求進一步被複雜化，是由於該等上拉電 阻器值和匯流排電容值，係相對各種此模態及相對各種此 200820609 匯流排應用而有變化。 一有一種被用來〜控制一個NM〇s下拉裝置之邊緣率的方 法疋控制供應到上述NMOS裝置之閘極的電流。舉例而 口某些傳統式邊緣率限制技術，係需要一個連續可用之 5電流源，其係來自晶片供應電流之代價。而且，連續可用 之電流源，在尺度上係難以跟上供應電壓中之變化。此呈 現出I2C(和其他）匯流排規格之相關問題，後者係容許使用 者界定零件電壓和匯流排電壓。另一種轉移率限制技術， ‘使用了一個電阻器網絡。此種古典電阻器限流解決方案， 10在變遷一旦完全時，係具有些許之靜電流；然而，其會產 生一種緩慢啟通之非線性!^：下降緣。 此等和其他議題，在控制信號驅動器電路之邊緣率方 面會呈現出問題。因此，在控制一個輸出信號驅動器方面， 係留有改善之空間。 15 【韻^明内溶1】 發明概要 本發明之各種特徵，係針對一些用以控制輸出信號之 方法和裝置，其方式可應付及克服上述諸議題。 … 依據一個範例性實施例，一姻輸出信號係使用一種電 20路裝置來控制。該電路裝置係具有一個電晶體，其閘極係 耦合至一個電容器，以及其輸出係耦合至該輸出匯流排信 號和該電容器。有一個電流源，耦合至該電晶體之閘極。 该電流源係被配置來選擇響應一個輸入信號’而提供某一 數量之電流，以及使響應一個回授信號，而改變其所提供 200820609 之電流量。一個回授電路，可提供該回授信號給上述之電 流澡-，以及可響應上述·電晶體之閘極處的〜電壓，來改變該 回授信號。 依據另一個範例性實施例，有一個用以控制輸出信號 5 之方法被實現。響應一個輸入信號，會有一個第一電流量， 提供給一個電晶體之閘極。此閘極係耦合至一個電容器， 以及該電晶體之輸出，係耦合至該輸出信號和該電容器。 響應上述電晶體之閘極處的電壓之達至一個參考電壓，便 會有一個第二電流量被提供。 10 本發明之以上總結，並非意圖說明本發明之每個實施 例或實現體。彼等優點和成就，配合本發明更完全之理解， 將可藉由下文之詳細說明及配合所附諸圖所舉之專利請求 項，而變得明顯及被理解。 圖式簡單說明 15 本發明可藉由考慮所附諸圖有關本發明之各種實施例 的以下詳細說明，而有更加完全之暸解，其中： 第1圖係一個依據本發明之範例性實施例的輸出信號 控制系統之方塊圖；而… 第2圖則係一個依據本發明之範例性實施例的輸出信 20 號控制系統之電路示意圖。 雖然本發明可按照各種修飾體和變更形式處理，彼等 之特定細節已藉由範例顯示在諸圖中，以及將做更詳細之 說明。然而，理應瞭解的是，本發明不應受限於此等說明 之特定實施例。相反的是，本發明應涵蓋所有在所附申請 200820609 等價體、和變 專利範圍所界定之發明的範圍内之修飾體 更形式— 【實施冷式】 杈佳實施例之詳細說明 5 本發明被認為係可應用在多種邊緣率控制裝置和方法 t °雖然本發明並非必然受限於此類應用例，透過此種環 境中之範例的討論，將可使本發明之各種特徵得到最好的 理解。 依據本發明之一個範例性實施例，有一種電路裝置被 10實現來控制一個信號之邊緣率。此種電路裝置，係包含有 個用以驅動輸出信號之電晶體’和―個連接在該輸出信 號與該電晶體的閘極之間的電容器。有一個電流源耦合至 上述下拉電晶體之輸入端，以及係酉己置來響應一個致能輸 入信號，而供應電流給該下拉電晶體之閘極。當被致能時， 15該電流源可響應一個回授電路所提供之回授致能，來改變 所供應之電流量。該回授電路可響應上述下拉電晶體之閘 極處的電壓，來改變該回授信號。 依據本發明之另一範例性實施例，一個Pc匯流排界 面，是使用一個N-通道金屬氧化物半導體場效電晶體 20 (NM0S)下拉裝置來實現。就一條具有一個低負载(例如， 低上拉電流和匯流排電容)之i2c匯流排而言，一個電流源可 使一個耦合在該輸出端與該ΝΜΟS下拉裝置的閉極之間的 回授電容器充電。此種結構特別有用的是，可確保上述 匯流排上面之高至低變換有關的邊緣率，滿足該等最小真 10 200820609 緣率需求。就一條具有一個高負載(例如，高上拉電流和匯 流排電容)之I c匯流排而吕-’該電流源可使供應至上述 NMOS下拉裝置之閘極的電流量增加。此電流之增加，唯 有在上述NMOS下拉裝置之閘極上面的電壓，達至某一定 5 電壓或“跳脫點”之後方會實現。此種結構特別有用的是， 可確保該邊緣率在一個最小與最大速率之間。 上述加增之電流量，可基於一些最大之預期負載條件 加上該NMOS下拉裝置之驅動能力，來加以選擇。在一些 具有一個低負載之應用例中，若該跳脫點未細心加以選 10 擇，上述加增之電流位準，會使得該邊緣率違反上述最小 之需求時序。上述達至跳脫點所需之時間，係該回授電容 器和所提供之電流的一個直接函數。因此，上述跳脫點電 壓之選擇，可選擇使避免過快之邊緣率，其係藉由保証該 電流不會被增加，直至一個最小之充電時間過後為止。 15 在一個特定之實施例中，該電流源係使用一個可變電 阻器或電阻器網絡來實現。該電流在變化上，係藉由改變 上述可變電阻器或電阻器網絡之有效電阻值。舉例而言， 一個NMOS或類似之電晶體裝置，可以電氣方式使與上述 電阻器網絡之一個或多個電阻器並聯連接。當該電晶體在 20 活動時，該並聯電阻器係有效地使旁路，藉以降低該電阻 器網絡之電阻值。在一個實例中，該電路係獨立於供應電 壓，來控制供應至上述電·阻器網絡之電壓。舉例而言，一 個二極體、電晶體、或類似裝置之電壓降，可以電氣方式 使與該電阻器網絡並聯連接，藉以維持一個無關乎供應電 11 200820609 壓之相當穩定的電壓。 在一個實制中，使用多重泰士 夕更哲屢位準或一些可響應達至 幾種電壓位準中的一個之間士 3極龟壓而改變的電阻器網絡 值，係有可能實現數種位準之 + 干心1、給電流。此可容許該電流 源，響應上述回授電容器之_，漸進地增加（或降低)該電 •在此料巾任何數目之電流位準均可被實現，准 有受限於該電路所希望之粒度和複雜性。200820609 IX. Description of invention: [Technology of the examination, the field of rape] - Related US application information This application is an earlier application filed on March 31, 2006. 60/788, 211 entitled "Improved Drive Capability in a Zero-Power dissipation Edge Rate Control Circuit," (improved drive capability in a zero power dissipation edge rate control circuit). FIELD OF THE INVENTION The present invention generally relates to a method and system for controlling an output signal, and more particularly to an implementation of a circuit for controlling signal driving characteristics of an output signal. [Prior Art 3 BACKGROUND OF THE INVENTION Electrical systems often use wiring to transmit information between components of the system. Such wiring usually consists of one or more signal lines, which together are also referred to as bus bars. In order to transmit this information, the components of the above system are bound to drive the voltage level of the bus bar to the appropriate level. There are often busbar specifications that, in a particular system, limit how fast or how slow the voltage change can be. For example, some systems use busses for integrated circuit 20 busses or I2C bus bars. The I2C bus is a control bus that provides a communication link between the integrated circuits within a system. This simple dual-wire busbar developed by Philips in early 1980 has a software-defined communication protocol and has evolved into an industry-standard world standard for system control, and since 200820609 temperature sensors and voltage level converters All the way to EEPROMs, general purpose I/O, A/D and D/A converters, C0DEG-, and all kinds of microprocessors. U.S. Patent No. 4,689,740 to Moelands et al., entitled "Two-Wire Bus-System Comprising a Clock Wire and a Data Wire for 5 Interconnecting a Number of Stations" (consisting of a clock signal metal wire and a data wire) A two-wire busbar system interconnecting many workstations, illustrating a computer system that includes a number of workstations that are interconnected by a clock signal metal wire and a data metal wire to form a wire junction logic A bus, which is a function of the signals generated by the workstations on its 10, and whose full-text quotations are merged by reference. I2C busbars also save space and reduce overall costs. Using the fc specification, designers can quickly move from a block diagram to find hardware, simplifying the addition of new devices and features to an existing bus interface. With the system, the first, the second, and the second generation; the 2C device can be easily added or removed without harming the rest of the system. This two-wire structure means fewer traces, so the board can be much smaller. It is also easier to debug and test, as there are fewer traces and fairly simple communication protocols. There are several reasons why the I C bus has been going on for more than 2 years. The first 20 first introduced hubs, bus repeaters, bidirectional switches, and Xigongyi in recent years have increased the number of devices that the busbar can support, and expanded the maximum busbar capacitance of 400 PF. The number of devices. And the ground-based conflict detection and arbitration can avoid data corruption and ensure that it is in the complex system. However, in addition to performance, 200820609 is easy to use. Two simple lines connect all the integrated circuits of a system. Any one of these devices can be attached to a conventional bus, and any one of the master devices can be exchanged with any one of the slave devices. The above-mentioned software-controlled addressing scheme can eliminate the requirement for addressing decoding, and does not (4) set up and debug external control logic, because it has already been provided by the i2c communication protocol. In addition, the bus is always synchronized with performance, and the fourth-order data rate transfer using the increased clock rate is provided. For example, these clock signal rates can be as high as 100 kHz in the sample mode, up to 10 400 kHz in the fast mode, up to i Mhz in the accelerated mode, and up to 3·4 in the high speed mode. Mhz 〇 is based on the accelerated modal specification, the wafer level j2c interface, which includes an open circuit 3 MOSFET metal oxide semiconductor field effect f crystal (sink) pull-down device 'with a single-pull resistor for the All devices on top 15 of this bus are shared. In order to compensate for the above-mentioned accelerated modal addition bus rate, the specifications require that the bus signals have the largest edge transition. This maximum rising edge transition can be satisfied by selecting an appropriate small pull-up resistor. The accelerated modal specification requires that the maximum falling edge transition (70%-3Q%) does not exceed 120nw ,, in order to avoid sensitivity to electromagnetic interference (2) and signal reflection, the minimum falling edge transition (7〇 %_3〇%) must not occur within less than 20 ns. θ, the NM0ST abuts the device and must have the ability to control the edge rate' to provide a falling edge transition within the maximum and minimum requirements. This requirement is further complicated by the fact that these pull-up resistor values and busbar capacitance values vary with respect to various modalities and relative to various 200820609 busbar applications. There is a method of controlling the edge rate of an NM〇s pulldown device to control the current supplied to the gate of the above NMOS device. For example, some conventional edge rate limiting techniques require a continuously available 5 current source that is at the cost of supplying current from the wafer. Moreover, continuously available current sources are difficult to keep up with changes in supply voltage on a scale. This presents issues related to I2C (and other) busbar specifications, which allow the user to define the part voltage and busbar voltage. Another transfer rate limiting technique, ‘uses a resistor network. This classical resistor current limiting solution, 10 has a slight electrostatic current once the transition is complete; however, it produces a slow-starting nonlinearity! ^: falling edge. These and other issues present problems in controlling the edge rate of the signal driver circuit. Therefore, there is room for improvement in controlling an output signal driver. 15 [Yun ^ Ming Internal Dissolution 1] SUMMARY OF THE INVENTION The various features of the present invention are directed to methods and apparatus for controlling output signals in a manner that addresses and overcomes the above-discussed aspects. According to an exemplary embodiment, a marriage output signal is controlled using an electrical 20-way device. The circuit arrangement has a transistor whose gate is coupled to a capacitor and whose output is coupled to the output bus signal and the capacitor. There is a current source coupled to the gate of the transistor. The current source is configured to selectively provide a certain amount of current in response to an input signal &, and to vary the amount of current provided by the 200820609 in response to a feedback signal. A feedback circuit is provided for supplying the feedback signal to the current bath, and the feedback voltage can be changed in response to the voltage at the gate of the transistor. According to another exemplary embodiment, a method for controlling the output signal 5 is implemented. In response to an input signal, there is a first amount of current that is supplied to the gate of a transistor. The gate is coupled to a capacitor, and the output of the transistor is coupled to the output signal and the capacitor. In response to the voltage at the gate of the transistor reaching a reference voltage, a second amount of current is supplied. The above summary of the present invention is not intended to describe each embodiment or implementation of the invention. The advantages and accomplishments of the present invention will become more apparent from the understanding of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS The present invention may be more fully understood by the following detailed description of the embodiments of the invention, A block diagram of the output signal control system; and Fig. 2 is a circuit diagram of an output signal No. 20 control system in accordance with an exemplary embodiment of the present invention. While the invention has been described in terms of various modifications and modifications, the specific details are shown in the drawings and However, it should be understood that the invention is not to be limited to the particular embodiments illustrated. On the contrary, the present invention is intended to cover all modifications of the scope of the invention as defined in the appended claims. It is believed that it can be applied to a variety of edge rate control devices and methods. Although the present invention is not necessarily limited to such applications, the various features of the present invention will be best achieved through the discussion of examples in such environments. understanding. In accordance with an exemplary embodiment of the present invention, a circuit arrangement is implemented 10 to control the edge rate of a signal. Such a circuit arrangement includes a transistor ' for driving an output signal' and a capacitor connected between the output signal and a gate of the transistor. A current source is coupled to the input of the pull-down transistor, and the system is configured to respond to an enable input signal and supply current to the gate of the pull-down transistor. When enabled, the current source can change the amount of current supplied in response to the feedback enable provided by a feedback circuit. The feedback circuit can change the feedback signal in response to the voltage at the gate of the pull-down transistor. In accordance with another exemplary embodiment of the present invention, a Pc bus interface is implemented using an N-channel metal oxide semiconductor field effect transistor 20 (NMOS) pull down device. For an i2c bus with a low load (eg, low pull-up current and busbar capacitance), a current source can have a feedback capacitor coupled between the output and the closed-pole of the ΝΜΟS pull-down device Charging. This configuration is particularly useful in ensuring the edge rate associated with the high to low transitions above the busbars to meet these minimum requirements. For an Ic bus with a high load (e.g., high pull-up current and busbar capacitance), the current source can increase the amount of current supplied to the gate of the NMOS pull-down device. This increase in current is achieved only after the voltage across the gate of the NMOS pull-down device reaches a certain 5 voltage or "trip point". This configuration is particularly useful to ensure that the edge rate is between a minimum and maximum rate. The amount of current added above can be selected based on some of the maximum expected load conditions plus the driving capability of the NMOS pull-down device. In some applications with a low load, if the trip point is not carefully selected, the above-mentioned increased current level causes the edge rate to violate the minimum required timing. The time required to reach the trip point is a direct function of the feedback capacitor and the current supplied. Therefore, the selection of the above-mentioned trip point voltage can be selected to avoid an excessively fast edge rate by ensuring that the current is not increased until a minimum charging time has elapsed. In a particular embodiment, the current source is implemented using a variable resistor or resistor network. The current is varied by varying the effective resistance of the variable resistor or resistor network. For example, an NMOS or similar transistor device can electrically connect one or more resistors of the resistor network in parallel. When the transistor is active 20, the shunt resistor is effectively bypassed to reduce the resistance of the resistor network. In one example, the circuit is independent of the supply voltage to control the voltage supplied to the electrical resistor network. For example, the voltage drop of a diode, transistor, or the like can be electrically connected in parallel with the resistor network to maintain a relatively constant voltage that is independent of the supply voltage. In a real system, it is possible to implement several kinds of resistor network values that can be changed by using multiple Texan yue or some responding to one of several voltage levels. Level + dry heart 1, give current. This allows the current source to progressively increase (or decrease) the current in response to the feedback capacitor. Any number of current levels in the wipe can be achieved, subject to the circuit's desire. Granularity and complexity.
10 兹轉至諸圖，第1圖係顯干伽乂十換丄々 口你4不一個依據本發明之範例性實 施例的邊緣率控制電路的太诒 格旳方塊圖。此間圖係包含有輸入 101、電流源102、回授批告、μ ^ _ 扠匕制104、電容回授106、信號驅動 為108、和負載11〇。此電路可變 包崎」专應該輸入1〇1，而驅動連接 至負載110之信號。 該負載削係代表與連接至信號驅動器108之輸出信號 相關聯的電阻性、電容性、和電感性組件。在一個此匯流 排系、、先中，舉例而言，該負荷係受制於該上拉電阻器值、 上拉電壓、各種與此系統相連接之裝置的電容值、和此系 統的裝置之間的配線。在上述I2c規格之情況中，該等上拉 電阻器值和電壓，可因應用例而有不同。舉例而言，該上 拉電阻器值，就-個加快模態而言，比起_個標準模態系 2〇統，有時係較強（較小之電阻值）。此外，該系統中之裝置的 數目，加上該等裝置之個別負載特性，會隨著系統之不同 而有顯著之變化。 在本發明之一個實施例中，該邊緣率控制電路，係配 置使容納信號驅動器1〇8上面之不同負载和不同之〗2c模 12 200820609 態。舉例而言，該邊緣率控制電路，係被配置來操控兩種 一一負載情況-一種小負载和一種大負載-。在負載110相當斗之 个月況下，該信號驅動器108，可能會產生一種就該規格而言 過快之邊緣率。就此種負載而言，該信號驅動器，會受 5到電谷回授106之限制。該電流源102可藉由使該電容回授 106充電，而提供一種可在上述信號驅動器1〇8之輸入端上 面建立電壓的電流。一旦該電壓達至一個臨界電壓（例如， 該裝置傳導電流所需之閘極電壓），該信號驅動器1〇8將會 變成活動狀，以及會隨著輸入電壓之增加，繼續增加其驅 10動能力。該輸出電壓中所成之變化(dv/dt)，將會影響到該 閘極電壓，而透過電容回授106，使該閘極電壓依(dv/dt)之 一個函數而降低。因此，該輸出電壓中之變化，可反制上 述電流源102所致加增之輸入電壓。在此方式中，該邊緣率 控制電路’可基於該電流源所提供之電流和上述電容回授 15 106之電容值，而維持一個最小之邊緣率。 在該負載110為一種相當大之負載的情況中，該電流源 102便會開始使上述之電容回授106充電，以及橫跨上述信 號驅動器丨⑽的輸入與輸出之間的電壓差將會增加。由於該 大負載所致，上述輸出信號上面之電壓中的變化會趨缓， 20而使得該閘極電壓繼續增加。在該負載充份大之情況中， 該輸出電壓變化之速率，可能不足以滿足該最大之邊緣 率。因此，該回授控制104，可感測到此種條件（例如，藉 由監控該閘極電壓），以及可提供回授給該電流源1〇2。響 應該項回授，該電流源102將會使提供給上述信號驅動器 .13 200820609 5 10 15 20 ⑽之電流增加。此加增之電流可產生__個加增之邊緣率， 而容許該祕率㈣.電路，滿足上述最大雜率之需求〇 在本發明之一個實施例中，該電流源1〇2係使用一個電 阻器網絡和-個電壓調節器，來控制上述供應之電流。舉 例而吕，-個電麼係使施加至該電阻器網矣各，而產生一個 電流I。響應該回授控制1G4,上述電阻器網絡之電阻值會 被改變，而造成電流砰之變化。在一個實例中，有一個電 壓調節器，可決定施加至上述電阻器網絡之電壓，諸如使 用-個或多個二極體和/或電晶體，來產生該電壓。此可 使特別有用於實現-種使科變式供應電壓來卫作之邊緣 控制電路。該電流源可藉由改變上述電阻器網絡之電阻值 和施加至上述電阻器網路之電壓，來修改其所供應之電流。 在本發明之另—個實施例中，來自上述電流源102之電 流，係使用—個二極體、電晶體、或類似裝置之電壓降或 臨界電壓來提供，叹制授㈣顧配置來_該間極 處之電壓何時接近該供應電壓。響應此種電壓之偵測，該 口授控制104’可提供__伽授錢給該電㈣⑽。該 流源102可降低—烟以（配合該電壓降)倾上述供應w 之電阻器網絡的有效電阻值。此可能是特财用於 極體或由於信號驅動器⑽之閘極處趨近該裝置的供鹿: 昼之^壓所致而運作於其臨界電壓附近的電晶體之效應。电 弟2圖係顯示一個依據 明之 〜 邊緣率控制電路之亍音„ a例的特定 出、回授電”動該輪 電阻器網絡(則和啤、和回授開關_ 14 200820609 之裝置M5。 裝置M10和電阻器配對R1*R2，係被甩來建立一個獨 立於電壓供應器之電流源。在活動中時，該裝置“忉所展 現自源極至閘極之電壓，係等於一個臨界電壓。上述由串 5聯電阻器配對幻和112所組成之電阻器網絡，係連接在上述 裝置M10的源極與閘極之間。因此，該有效之充電電流係10 Turning to the figures, Figure 1 shows the singularity of the edge rate control circuit in accordance with an exemplary embodiment of the present invention. The diagram here includes an input 101, a current source 102, a feedback grant, a μ^_fork 104, a capacitor feedback 106, a signal drive of 108, and a load of 11 〇. This circuit is versatile and should be input to 1〇1 and drive the signal connected to load 110. The load cut represents the resistive, capacitive, and inductive components associated with the output signal coupled to signal driver 108. In one such busbar system, first, for example, the load is subject to the pull-up resistor value, the pull-up voltage, the capacitance of various devices connected to the system, and the device of the system. Wiring. In the case of the above I2c specification, the values of the pull-up resistors and voltages may vary depending on the application. For example, the pull-up resistor value, in terms of an accelerated mode, is sometimes stronger (smaller resistance value) than a standard mode system. In addition, the number of devices in the system, plus the individual load characteristics of the devices, can vary significantly from system to system. In one embodiment of the invention, the edge rate control circuit is configured to accommodate different loads on the signal drivers 1 〇 8 and different states. For example, the edge rate control circuit is configured to handle two load cases - a small load and a large load -. Under the condition that the load 110 is quite versatile, the signal driver 108 may produce an edge rate that is too fast for the specification. For this type of load, the signal driver is limited by the 5 to the valley feedback 106. The current source 102 can provide a current that can establish a voltage across the input of the signal driver 1A8 by charging the capacitor 106. Once the voltage reaches a threshold voltage (for example, the gate voltage required for the device to conduct current), the signal driver 1〇8 will become active and will continue to increase its drive 10 as the input voltage increases. ability. The change in the output voltage (dv/dt) will affect the gate voltage, and the feedback capacitor 106 will cause the gate voltage to decrease as a function of (dv/dt). Therefore, the change in the output voltage can counteract the increased input voltage caused by the current source 102. In this manner, the edge rate control circuit' maintains a minimum edge rate based on the current supplied by the current source and the capacitance value of the capacitance feedback 15106. In the event that the load 110 is a relatively large load, the current source 102 will begin to charge the capacitor 106 described above, and the voltage difference between the input and output across the signal driver 丨 (10) will increase. . Due to this large load, the change in the voltage above the output signal will be slowed down, 20 causing the gate voltage to continue to increase. In the case where the load is sufficiently large, the rate at which the output voltage changes may not be sufficient to satisfy the maximum edge rate. Thus, the feedback control 104 can sense such conditions (e.g., by monitoring the gate voltage) and can provide feedback to the current source 1〇2. In response to the feedback, the current source 102 will increase the current supplied to the signal driver .13 200820609 5 10 15 20 (10). The increased current can produce __increased edge rate, and allows the secret rate (4). The circuit satisfies the above-mentioned maximum noise requirement. In one embodiment of the present invention, the current source 1 〇 2 is used. A resistor network and a voltage regulator are used to control the current supplied. For example, an electric system is applied to the resistor mesh to generate a current I. In response to the feedback control 1G4, the resistance value of the above resistor network is changed to cause a change in current 砰. In one example, there is a voltage regulator that determines the voltage applied to the resistor network described above, such as using one or more diodes and/or transistors to generate the voltage. This makes it particularly useful for implementing edge control circuits that enable the supply voltage to be supplied. The current source can modify the current supplied by changing the resistance of the resistor network and the voltage applied to the resistor network. In another embodiment of the present invention, the current from the current source 102 is provided by using a voltage drop or a threshold voltage of a diode, a transistor, or the like, and the singer is given a configuration. When is the voltage at the pole close to the supply voltage? In response to detection of such voltage, the dictation control 104' may provide __ gamma grants to the electricity (four) (10). The flow source 102 can reduce the effective resistance value of the resistor network to which the smoke supply is supplied (in conjunction with the voltage drop). This may be the effect of a special crystal for the polar body or the transistor that is approaching the device due to the gate of the signal driver (10): the transistor operating near its critical voltage due to the pressure of the device. The electric brother 2 shows a device based on the ambiguity of the edge-to-edge control circuit „ a specific case, feedback power” of the wheel resistor network (and beer, and feedback switch _ 14 200820609 device M5. Device M10 and resistor pair R1*R2 are tied to establish a current source independent of the voltage supply. When active, the device "shows the voltage from the source to the gate, which is equal to a threshold voltage. The resistor network consisting of a series of five-connected resistors paired with a magical sum 112 is connected between the source and the gate of the device M10. Therefore, the effective charging current system is
Vt/(R1+R2)’因為該裝置M1〇使上述否則會使閘極電壓超過 該臨界電壓之電流，係使分流通過裝置M4而至接地端。上 述裝置M4之閘極，係耦合至該輸出電壓，以及因而一旦該 10輸出電壓係在接地端之臨界電壓範圍内，該路徑便會被解 能。 上述裝置Mil之閘極，係透過電阻器化3使連接至上述 電路之供應電壓。該電阻器R4係連接至上述裝置M2之汲 極。裝置M6和M3所建立之反相輸入信號，可在該輸入為低 15邏輯位準時，確保該裝置M2在活動中。當該裝置M2在活動 中時，該等電阻器R3和R4,便會建立一個分壓器，其可被 用來檢測’上述輸出裝置M5(節點n5)之閘極-源極電壓，何 日守充份超過上述輸出裝置之臨界電壓。舉例而言，在汉3和 R4相等之情況下，該裝置M11將停留在活動中，直至節點 20 n5處之電壓，大約為上述供應電壓的一半為止。一旦節點 n5處之電壓達至此點，該裝置Mn便會變為不在活動中， 以及節點n6便會透過電阻器反4被拉至接地電壓。有一個緩 衝儲存器202，可將節點沾之電壓施加至節點n7。在一個實 例中，該緩衝儲存器202之輸出，係基於節點沾處之輸入1 15 200820609 而為咼邏輯位準或低邏輯位準。更明確地說，該輸出在節 點n6處於或超過R3和R4所—決定之電壓時，係.為高邏輯位 準，以及在透過R4被拉至低邏輯位準時，係為低邏輯位準。 上述裝置M9之源極和汲極，係橫跨電阻器义2而連接，而容 5許該裝置M9，有效地自該電阻器網絡移除電阻器R2，藉以 使節點n8之電壓，提昇超過節點“之一個臨界電壓。 當一個輕負載（亦即，大外在上拉電阻器和小匯流排電 容)施加至該輸出時，電容器C0便會被用來使該輸出裝置 M5節制回來。當一個外在匯流排電容值極大，或者該外在 10上拉電阻器極小時，該節點!^便會被該内在上拉電流 (Vt—M10)/(R1+R2)充電，而比來自上述回授電容器c〇之電 壓變化(dv/dt)更快速。因此，節點n5處之電壓將會繼續增 加。一旦節點n5達至Vdd*(R3/(R3+R4))+Vt—Mll，該裝置 Mil便會被關閉，以及節點n6會被電阻器R4拉至接地電 15壓。此將會使節點n7下跌至接地電壓，而使該裝置M9能夠 ^短路掉電阻器R2。上述新的内在充電電流，係被增加至 Vt—M 10/R1。此加增之充電電流’可使節點n5上面之電壓 上昇更迅速，其可更強硬地驅動該輸出裝置M5。因此，上 述輸出之邊緣率，係藉由增加通過該裝置之動態電流來增 20 加。 當該輸入信號為咼缝輯位準時，該裝置]\48係不在活動 中，以及抽取自該電阻器網絡之電流，將為零或接近零。 此外，一旦節點n5處之電壓，達至一個接近供應電壓之電 壓(例如，供應電壓-(R0*(M10臨界電壓*(R1+R2))_M10臨界 16 200820609 =侧臨界電壓），抽取自該電阻器網絡之電流將接斤 令此在該輪出信號驅動器需要狼小甚至無電流時 別有用於極小化抽取自該電路之電流。 ’、寸 5Vt / (R1 + R2)' because the device M1 causes the above-mentioned current which would otherwise cause the gate voltage to exceed the threshold voltage, so that the current is shunted through the device M4 to the ground. The gate of device M4 described above is coupled to the output voltage, and thus the path is de-energized once the 10 output voltage is within the threshold voltage range of the ground. The gate of the above device Mil is connected to the supply voltage of the above-mentioned circuit through the resistor 3. The resistor R4 is connected to the anode of the above device M2. The inverting input signal established by devices M6 and M3 ensures that device M2 is active when the input is at a low logic level. When the device M2 is active, the resistors R3 and R4 establish a voltage divider which can be used to detect the gate-source voltage of the output device M5 (node n5). The sufficiency exceeds the threshold voltage of the above output device. For example, in the case where Han 3 and R 4 are equal, the device M11 will remain active until the voltage at node 20 n5 is approximately half of the supply voltage. Once the voltage at node n5 reaches this point, the device Mn becomes inactive and node n6 is pulled to ground through the resistor. There is a buffer memory 202 that applies a voltage applied to the node to node n7. In one embodiment, the output of the buffer memory 202 is based on the input of the node 1 15 200820609 and is a logical level or a low logic level. More specifically, the output is at a high logic level when node n6 is at or above the voltage determined by R3 and R4, and is at a low logic level when pulled through R4 to a low logic level. The source and the drain of the above device M9 are connected across the resistor 2, and the device M9 is enabled to effectively remove the resistor R2 from the resistor network, so that the voltage of the node n8 is increased more than A threshold voltage of the node. When a light load (ie, a large external pull-up resistor and a small busbar capacitor) is applied to the output, capacitor C0 is used to throttle the output device M5 back. If an external busbar capacitor is extremely large, or if the external 10 pull-up resistor is extremely small, the node will be charged by the internal pull-up current (Vt-M10)/(R1+R2), and the ratio is from The voltage change (dv/dt) of the feedback capacitor c〇 is faster. Therefore, the voltage at the node n5 will continue to increase. Once the node n5 reaches Vdd*(R3/(R3+R4))+Vt_Mll, The device Mil will be turned off, and the node n6 will be pulled to the grounding voltage 15 by the resistor R4. This will cause the node n7 to fall to the ground voltage, so that the device M9 can short-circuit the resistor R2. The above new internal The charging current is increased to Vt_M 10/R1. This increased charging current 'can make node n5 above The voltage rises more rapidly, which can drive the output device M5 more strongly. Therefore, the edge rate of the output is increased by 20 by increasing the dynamic current through the device. When the input signal is a quilting level, The device]\48 is not active, and the current drawn from the resistor network will be zero or close to zero. In addition, once the voltage at node n5 reaches a voltage close to the supply voltage (eg, supply voltage - (R0*(M10 Threshold Voltage*(R1+R2))_M10 Critical 16 200820609 = Side Threshold Voltage), the current drawn from the resistor network will be used to make the driver need less or no current when the turn signal driver There is no current used to minimize the extraction from the circuit. ', inch 5
10 在本發明之實施例中，該電阻器網絡，係包 之電阻m外，此等額外之電阻器可被選擇致能，使 ^抽取電流之額外位準。在—個實例中，有—個第二 电[电路提供’其係類似於上述包含有電阻器幻和如、壯 侧、和緩衝儲存器202之電路。有一個類似於上卿： 9之第—u ’可被貫現來有效地自該電阻器網絡，移除 们或夕個額外之電阻器。在—個實例中，該第二參考電 壓電路，可具有—個不同之參考電壓，藉以容許所提供: 電流的連續性增加。以此_方式巾，任·目之額外參考 電£電路均可被貫現。此在上述供應電流之控制中，可能 有用於提供額外之粒狀。 μ 中所脑及職明之各種實施例，在提供上係僅 為例示計，以及不應被詮釋為限制本發明。基於上文之討 論和圖例’本技藝之專業人員將可輕易認清的是，針對本 發明係可能完成各種修飾體和變更形式，而不必嚴格遵循 本說明書關示及說明之範例性實施例和應關^舉例而 20 5，一些不同於l2C裝置之應用例，可能使用類似之解決方 案按照貫現體來處理。此類修飾體和變更形式，並不違離 本發明闡明在以下申請專利範圍中之真實界定範圍。 【圖式簡單說明】 第1圖係一個依據本發明之範例性實施例的輸出信號 17 200820609 控制糸統之方塊圖，而 第2圖則係一個依據本發明之〜範例性實施例的輸-出信 號控制系統之電路示意圖。 【主要元件符號說明】 101…輸入信號 102.. .電流源 104.. .回授電路 106.. .電容器 108.. .電晶體 110…負載 202.. .缓衝儲存器 C0…回授電容器 M2…裝置 M4…裝置 ) M5...輸出裝置 M6，M3···裝置 M9…裝置 M10...裝置 Mil…回授開關 R1，R2·.·電阻器網絡 R3…電阻器 R4...電阻器 18In an embodiment of the invention, the resistor network, in addition to the resistance m of the package, these additional resistors can be selectively enabled to enable an additional level of current draw. In one example, there is a second electrical circuit provided similar to the circuitry described above including the resistor phantom and the side, and the buffer reservoir 202. There is a similarity to the upper: 9th - u ' can be effectively used to effectively remove the resistors or the extra resistors from the resistor network. In one example, the second reference voltage circuit can have a different reference voltage to allow for the supply: the continuity of the current is increased. With this method, the extra reference circuit can be used. This may be used to provide additional granularity in the control of the supply current described above. The various embodiments of the present invention are provided by way of example only and should not be construed as limiting the invention. It will be readily apparent to those skilled in the art of the present invention that the present invention may be practiced with various modifications and variations without departing from the exemplary embodiments and It should be closed, for example, 20 5, some application examples different from the l2C device, may be processed in a consistent manner using a similar solution. Such modifications and variations are not to be construed as a departure from the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an output signal 17 200820609 according to an exemplary embodiment of the present invention, and FIG. 2 is a transmission according to an exemplary embodiment of the present invention - A schematic diagram of the circuit of the signal control system. [Main component symbol description] 101... Input signal 102.. Current source 104.. Feedback circuit 106.. Capacitor 108.. Transistor 110... Load 202.. Buffer memory C0... Feedback capacitor M2...device M4...device) M5...output device M6,M3···device M9...device M10...device Mil...return switch R1,R2·.·resistor network R3...resistor R4... Resistor 18