WO2007109117A3 - Procede d'arret de gravure a sec pour eliminer un court-circuit electrique dans des structures de dispositif mram - Google Patents

Procede d'arret de gravure a sec pour eliminer un court-circuit electrique dans des structures de dispositif mram Download PDF

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Publication number
WO2007109117A3
WO2007109117A3 PCT/US2007/006607 US2007006607W WO2007109117A3 WO 2007109117 A3 WO2007109117 A3 WO 2007109117A3 US 2007006607 W US2007006607 W US 2007006607W WO 2007109117 A3 WO2007109117 A3 WO 2007109117A3
Authority
WO
WIPO (PCT)
Prior art keywords
etch stop
electrical shorting
stop process
dry etch
device structures
Prior art date
Application number
PCT/US2007/006607
Other languages
English (en)
Other versions
WO2007109117A2 (fr
Inventor
Robert Ditizio
Original Assignee
Tegal Corp
Robert Ditizio
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/724,556 external-priority patent/US7645618B2/en
Application filed by Tegal Corp, Robert Ditizio filed Critical Tegal Corp
Priority to EP07753250A priority Critical patent/EP1999781A2/fr
Priority to JP2009500499A priority patent/JP5085637B2/ja
Publication of WO2007109117A2 publication Critical patent/WO2007109117A2/fr
Publication of WO2007109117A3 publication Critical patent/WO2007109117A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N52/00—Hall-effect devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Hall/Mr Elements (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Drying Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)

Abstract

La présente invention concerne en général la fabrication de semi-conducteurs et, en particulier, la fabrication de dispositifs de jonction à effet tunnel magnétique. Cette invention concerne notamment un procédé permettant d'utiliser la couche diélectrique de jonctions à effet tunnel en tant que couche d'arrêt de gravure pour éliminer un court-circuit électrique pouvant résulter d'un procédé de formation de motifs.
PCT/US2007/006607 2006-03-16 2007-03-16 Procede d'arret de gravure a sec pour eliminer un court-circuit electrique dans des structures de dispositif mram WO2007109117A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP07753250A EP1999781A2 (fr) 2006-03-16 2007-03-16 Procede d'arret de gravure a sec pour eliminer un court-circuit electrique dans des structures de dispositif mram
JP2009500499A JP5085637B2 (ja) 2006-03-16 2007-03-16 Ｍｒａｍデバイス構造内の電気的短絡を排除するドライエッチング停止処理

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US78315706P 2006-03-16 2006-03-16
US60/783,157 2006-03-16
US11/724,556 US7645618B2 (en) 2004-09-09 2007-03-14 Dry etch stop process for eliminating electrical shorting in MRAM device structures
US11/724,556 2007-03-14

Publications (2)

Publication Number Publication Date
WO2007109117A2 WO2007109117A2 (fr) 2007-09-27
WO2007109117A3 true WO2007109117A3 (fr) 2007-12-13

Family

ID=38522964

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/006607 WO2007109117A2 (fr) 2006-03-16 2007-03-16 Procede d'arret de gravure a sec pour eliminer un court-circuit electrique dans des structures de dispositif mram

Country Status (4)

Country Link
EP (1) EP1999781A2 (fr)
JP (1) JP5085637B2 (fr)
KR (1) KR20090008240A (fr)
WO (1) WO2007109117A2 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100304504A1 (en) * 2009-05-27 2010-12-02 Canon Anelva Corporation Process and apparatus for fabricating magnetic device
JP6096762B2 (ja) * 2012-04-26 2017-03-15 東京エレクトロン株式会社 プラズマ処理方法及びプラズマ処理装置
JP5918108B2 (ja) * 2012-11-16 2016-05-18 東京エレクトロン株式会社 プラズマ処理方法及びプラズマ処理装置
JP6160903B2 (ja) * 2013-03-13 2017-07-12 株式会社東芝 磁気記憶素子及び不揮発性記憶装置
JP6134611B2 (ja) * 2013-08-29 2017-05-24 株式会社アルバック 磁気抵抗素子の製造方法
EP3572549A1 (fr) 2018-05-24 2019-11-27 Richemont International S.A. Article de joaillerie
CN111146336A (zh) * 2018-11-02 2020-05-12 江苏鲁汶仪器有限公司 一种单隔离层磁隧道结刻蚀方法
CN111162164B (zh) * 2018-11-08 2023-06-13 江苏鲁汶仪器股份有限公司 一种半导体器件制作方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3911579A (en) * 1971-05-18 1975-10-14 Warner Lambert Co Cutting instruments and methods of making same
US5980686A (en) * 1998-04-15 1999-11-09 Applied Komatsu Technology, Inc. System and method for gas distribution in a dry etch process
US6114719A (en) * 1998-05-29 2000-09-05 International Business Machines Corporation Magnetic tunnel junction memory cell with in-stack biasing of the free ferromagnetic layer and memory array using the cell
US6139702A (en) * 1999-03-05 2000-10-31 United Microelectronics Corp. Seasoning process for etcher
US6281538B1 (en) * 2000-03-22 2001-08-28 Motorola, Inc. Multi-layer tunneling device with a graded stoichiometry insulating layer
US6326637B1 (en) * 1999-10-18 2001-12-04 International Business Machines Corporation Antiferromagnetically exchange-coupled structure for magnetic tunnel junction device
US6531404B1 (en) * 2000-08-04 2003-03-11 Applied Materials Inc. Method of etching titanium nitride
US20040242005A1 (en) * 2003-04-14 2004-12-02 Chentsau Ying Method of etching metal layers
US20050051820A1 (en) * 2003-09-10 2005-03-10 George Stojakovic Fabrication process for a magnetic tunnel junction device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19728472A1 (de) * 1997-07-03 1999-01-07 Siemens Ag Strukturierungsverfahren
JP4809991B2 (ja) * 2001-04-17 2011-11-09 キヤノン株式会社 トンネル磁気抵抗素子の加工方法
JP2003324187A (ja) * 2002-05-01 2003-11-14 Sony Corp 磁気メモリ装置の製造方法および磁気メモリ装置
JP4111274B2 (ja) * 2003-07-24 2008-07-02 キヤノンアネルバ株式会社 磁性材料のドライエッチング方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3911579A (en) * 1971-05-18 1975-10-14 Warner Lambert Co Cutting instruments and methods of making same
US5980686A (en) * 1998-04-15 1999-11-09 Applied Komatsu Technology, Inc. System and method for gas distribution in a dry etch process
US6114719A (en) * 1998-05-29 2000-09-05 International Business Machines Corporation Magnetic tunnel junction memory cell with in-stack biasing of the free ferromagnetic layer and memory array using the cell
US6139702A (en) * 1999-03-05 2000-10-31 United Microelectronics Corp. Seasoning process for etcher
US6326637B1 (en) * 1999-10-18 2001-12-04 International Business Machines Corporation Antiferromagnetically exchange-coupled structure for magnetic tunnel junction device
US6281538B1 (en) * 2000-03-22 2001-08-28 Motorola, Inc. Multi-layer tunneling device with a graded stoichiometry insulating layer
US6531404B1 (en) * 2000-08-04 2003-03-11 Applied Materials Inc. Method of etching titanium nitride
US20040242005A1 (en) * 2003-04-14 2004-12-02 Chentsau Ying Method of etching metal layers
US20050051820A1 (en) * 2003-09-10 2005-03-10 George Stojakovic Fabrication process for a magnetic tunnel junction device

Also Published As

Publication number Publication date
EP1999781A2 (fr) 2008-12-10
JP5085637B2 (ja) 2012-11-28
JP2009530825A (ja) 2009-08-27
KR20090008240A (ko) 2009-01-21
WO2007109117A2 (fr) 2007-09-27

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