WO2007105716A1

WO2007105716A1 - Substrate and device

Info

Publication number: WO2007105716A1
Application number: PCT/JP2007/054924
Authority: WO
Inventors: Takashi Okano
Original assignee: Daikin Industries, Ltd.
Priority date: 2006-03-14
Filing date: 2007-03-13
Publication date: 2007-09-20
Also published as: JP2007250645A

Abstract

A substrate in which noise generated by a return current flowing through a multilayer substrate is reduced. The substrate has an insulation substrate (2), wirings (311, 312), signal lines (321, 322, 331, 332) and vias (323, 333, 341, 342). The wirings (311, 312) are laminated, between a surface (21a) and a surface (21b), through an insulating plate (202) which is a part of the insulation substrate (2) in a predetermined direction (90). The signal lines (321, 331) are arranged on the surface (21a) and provided oppositely to the wiring (311). The signal lines (322, 332) are arranged on the surface (21b) and provided oppositely to the wiring (312). A via (323) interconnects the signal lines (321, 322). A via (333) interconnects the signal lines (331, 332). Vias (341, 342) are provided in the insulating plate (202) and interconnect the wiring (311, 312). The via (341) is provided in proximity to the via (323), and the via (342) is provided in proximity to the via (333).

Description

Specification

Substrate and equipment

Technical field

[0001] The present invention relates to a substrate and an apparatus, and more particularly to a multilayer laminated substrate.

Background art

As a substrate on which an integrated circuit is provided, for example, a multilayer laminated substrate is employed. In a multilayer substrate, a ground plane and a power plane are stacked on the inner layer. Signal lines are arranged on the surface of the multilayer laminated substrate in the lamination direction.

[0003] The integrated circuit is provided on the surface of the multilayer laminated substrate. The power supply terminal of the integrated circuit is connected to the power supply plane via one signal line, and the ground terminal of the integrated circuit is connected to the ground plane via the other signal line.

[0004] Further, in the case where the signal line is arranged on both of the surfaces, and when the signal line arranged on one side of the surface and the signal line arranged on the other side are connected, For example, a via that penetrates a multilayer substrate from one of the surfaces to the other is employed.

[0005] Technologies related to noise countermeasures are shown below.

[0006] Patent Document 1: Japanese Patent No. 3170797

Patent Document 2: Japanese Patent No. 3327714

Non-Patent Document 1: Yue Ie, “Optimum EMC Design of Printed Circuit Boards in the High Speed and High Density Packaging Age 1 Basics of EMC Design in Printed Circuit Boards”, EMC, Mimatsu Corporation, January 2005, No. 201, p. 69- 80

Disclosure of the invention

Problems to be solved by the invention

[0007] When a current flows through the signal line from one side of the surface to the other via a connection line, a return current flows through a portion of the power plane and the ground plane facing the signal line.

[0008] However, since the power plane and the ground plane are stacked via an insulating plate, the return current cannot flow along the current flowing through the via. Therefore, return power The current once flows through one of the power plane and the ground plane to a position where there is a capacitor connected between the power plane and the ground plane. Then, the return current flows through the capacitor to the other of the power plane and the ground plane, and then flows along the signal line along the other side.

[0009] For this reason, when the capacitor is not in the vicinity of the via, the path from one of the return current force power supply plane and the ground plane to the other becomes longer, and noise is likely to occur.

The present invention has been made in view of the above-described circumstances, and an object thereof is to reduce noise generated by a return current flowing in a multilayer laminated substrate.

Means for solving the problem

[0011] A first aspect of the present invention that works on the substrate is that the insulating substrate (2) and one of the surfaces (21a) and the other (21b) of the insulating substrate in a predetermined direction (90). Between the first and second wirings (311, 312) stacked in a predetermined direction via a part (202) of the insulating substrate, and on each of the one and the other of the surface First and second signal lines (321, 322; 331, 332) arranged without being connected to the first and second wirings, and the first and second signal lines A plurality of first vias (323; 333) that connect each other, and the first and second wirings are connected to each other and provided close to each of the plurality of first vias A plurality of second vias (341; 342).

[0012] The second aspect of the present invention is a substrate that exerts a force on the substrate according to the first aspect, wherein the surface (21a) is not connected to the first and second wirings. , 21b) is further provided with a third wiring (35) arranged on at least one of them.

[0013] The third aspect of the present invention is a substrate that exerts a force on the substrate according to the first or second aspect, wherein the plurality of second vias (343) are in the predetermined direction. They are arranged in a grid as seen from (90).

[0014] A first aspect of the apparatus of the present invention is provided on at least one of the substrate according to any one of the first to third aspects and the surface (21a, 21b) of the substrate. An integrated circuit (11), and the integrated circuit is connected to one of the first and second wirings (311, 312) on the integrated circuit side, and the integrated circuit and the one wiring The distance (d) in the predetermined direction (90) is lmm or less.

[0015] A second aspect of the apparatus of the present invention is provided on at least one of the substrate according to any one of the first to third aspects and the surface (21a, 21b) of the substrate. Integrated circuit (11), and a fourth wiring that is provided on the same surface as the integrated circuit and surrounds the integrated circuit.

The invention's effect

[0016] According to the first aspect of the present invention, the current flows from one of the first and second signal lines to the other through the first via, and the first Even if a return current is generated in the wiring and the second wiring, the return current passes between the first wiring and the second wiring through the second via closest to the first via. Therefore, the path through which the return current flows is shortened, and noise generation is reduced.

[0017] According to the second aspect of the present invention, the power supply potential different from the power supply potential applied to the first and second wirings can be applied to the third wiring.

[0018] According to the third aspect of the present invention, the second vias are arranged in a grid pattern, so that the first vias are connected to the first and second wirings at positions other than the grid position. There is a second via close to the first via wherever it is not in contact.

[0019] According to the first aspect of the present invention, since the distance between the integrated circuit and the wiring is reduced, the electric field flowing from one of the integrated circuit and the wiring to the other is It is easy to flow between the integrated circuit and the wiring. Therefore, noise leakage due to the electric field can be reduced.

[0020] According to the second aspect of the present invention, leakage of noise to the outside can be reduced by flowing noise generated in the integrated circuit through the fourth wiring. However, since the area of the fourth wiring can be increased around the integrated circuit, it is possible to further reduce the leakage of noise to the outside.

[0021] The objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.

Brief Description of Drawings

FIG. 1 is a top view conceptually showing a substrate according to the present invention. FIG. 2 is a diagram conceptually showing a cross section at a position AA shown in FIG.

FIG. 3 is a perspective view conceptually showing a substrate.

FIG. 4 is a view of the boundary surface 22 as viewed from a predetermined direction 90.

FIG. 5 is a diagram conceptually showing a cross section at a position BB shown in FIG. 1.

FIG. 6 is a top view conceptually showing an integrated circuit 11 provided on a surface 21a of a substrate. BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 is a top view conceptually showing a substrate that is useful in the present invention. FIG. 2 shows a cross section at the position AA shown in FIG. FIG. 3 is a perspective view of the substrate, showing each layer described later separately in the stacking direction.

The substrate has an insulating substrate 2, self-insulating lines 311, 312, signal lines 321, 322, 331, 332 and vias 323, 333, 341, 342. For example, an integrated circuit 11 can be provided on the substrate. FIG. 1 and FIG. 2 show the case where the element 1 having the integrated circuit 11 and the terminals P11 to P14 connected thereto is provided on the surface 21a of the substrate.

The insulating substrate 2 includes insulating plates 201 to 203. The insulating plates 203, 202, 201 are laminated in the predetermined direction 90 in this order. Of the surface of the insulating substrate 2 in the predetermined direction 90, the insulating plate 201 side is indicated by reference numeral 21a, and the insulating plate 203 side is indicated by reference numeral 21b. In addition, a boundary surface 22 between the insulating plate 201 and the insulating plate 202 and a boundary surface 23 between the insulating plate 202 and the insulating plate 203 are indicated by broken lines, respectively. In FIG. 3, the surfaces 21a and 21b and the boundary surfaces 22 and 23 are schematically shown as layers.

[0026] The selfish wire 311 is provided between the insulating plate 201 and the insulating plate 202. The self-insulating wire 312 is provided between the insulating plate 202 and the insulating plate 203 and is connected. This content can be understood that the selfish wires 311 and 312 are laminated between the surface 21a and the surface 21b via the insulating plate 202 which is a part of the insulating substrate 2 in a predetermined direction 90. it can. For example, a ground plane can be adopted as the wirings 311 and 312.

The signal line 321 is disposed on the surface 21 a and is provided to face the wiring 311. The signal line 3 22 is disposed on the surface 21 b and is provided to face the wiring 312. In FIG .:! To 3, the signal line 321 is connected to the integrated circuit 11 via the terminal PI1.

The via 323 connects the signal lines 321 and 322 to each other. Specifically, via 323 is isolated The substrate 2 penetrates from one of the surfaces 21a and 21b to the other in a predetermined direction 90, and both ends of the via 323 are connected to signal lines 321 and 322, respectively. However, the via 323 is not connected to the wirings 311 and 312. For example, when the wirings 311 and 312 are plain, gaps 31 la and 312ba for passing vias 323 are provided in the wirings 311 and 312 as shown in FIGS.

Similarly, the signal lines 331 and 332 are disposed on the surfaces 21a and 21b, respectively. The via 333 connects the signal lines 331 and 332 to each other without being connected to the wirings 311 and 312. In FIG. 1 to FIG. 3, the wirings 311 and 312 are provided with gaps 311b and 312b for passing the via 333, respectively. Further, the signal line 331 is connected to the integrated circuit 11 via the terminal P12.

The vias 341 and 342 are provided on the insulating plate 202 and connect the wirings 311 and 312 to each other. The via 341 is provided close to the via 323, and the via 342 is provided close to the via 333.

[0031] According to the power board, current flows through the via 323 (333) to one of the signal lines 321 and 322 (331 and 332) and the other, and a return current is generated in the wiring 311 and 312. However, since the return current flows between the wirings 31 1 and 312 through the via 341 (342) located closest to the via 323 (333), the return current path is shortened, and noise is generated. Is reduced.

[0032] The above effect will be specifically described with reference to FIG. Note that the path and direction in which the current and return current flow are indicated by arrows in FIG. When the current flows through the signal line 321, the via 323 and the signal line 322 in this order, the return current flows through the wirings 311 and 312 and the via 341 accordingly. That is, the return current flows through the portion of the wiring 312 facing the signal line 322 in the opposite direction to the current of the signal line 322 to the position rl near the via 323, and then flows toward the via 341. . The return current that has reached one end 341 a on the wiring 312 side of the via 341 flows in the via 341 to the wiring 311 side. The return current that has reached the wiring 311 flows from the other end 341b of the via 341 to the position r2 in the vicinity of the via 323, which is opposite to the signal line 321 of the wiring 311. It flows in the opposite direction. At this time, since the via 341 in which the return current flows is in the vicinity of the via 323, the The length to position rl force position r2 in the path through which the turn current flows is shortened. Therefore, the generation of noise is reduced.

[0033] When a current flows through the signal line 331, the via 333, and the signal line 332 in this order, a return current is also generated. However, as described above, the return current flows through the via 342 in the vicinity of the via 333, so the path through which the return current flows is shortened, and noise generation is reduced.

FIG. 4 is a view of the boundary surface 22 as viewed from a predetermined direction 90. In FIG. 4, a plurality of forces S of vias 343 connecting the wirings 31 1 and 312 to each other are provided on the insulating plate 202 in a lattice shape.

In such a substrate, since the vias 343 are arranged in a grid pattern, the vias 323 and 333 can be provided at any position other than the grid position so as not to contact the wirings 31 1 and 312 with respect to the vias 323 and 333. There is a nearby via 343, which shortens the return current path.

Returning to FIG. 1, the substrate further includes wirings 35 and 36. The wiring 35 is connected to the integrated circuit 11 through the terminal P13. One end of the wiring 36 is connected to the integrated circuit 11 via the terminal P14, and the other end is connected to the wiring 311 via the via 335 provided in the insulating plate 201. Note that FIG. 5 shows a cross-section at position BB shown in FIG.

According to the powerful substrate, a power supply potential different from the power supply potential applied to the wirings 31 1 and 312 connected to each other by the vias 341 to 343 can be applied to the wiring 35. For example, if the wiring 35 is a power line and the wirings 31 1 and 312 are ground planes, a voltage applied between the power line and the ground plane can be supplied to the integrated circuit 11.

In FIG. 1, the wiring 35 is further arranged adjacent to and in parallel with the signal line 321. In this case, the parasitic capacitance C 1 per unit length generated between the signal line 321 and the wiring 35 is smaller than the parasitic capacitance C2 per unit length generated between the signal line 321 and the wiring 31 1. desirable. This is because the influence of noise on the signal line 321 on the wiring 35 is reduced because the electrostatic coupling between the wiring 321 and the wiring 35 is small. If the wiring 311 is a ground plane, even if the noise is placed on the wiring 311, the wiring 311 is connected to the ground that has a large power capacity. small. Here, the parasitic capacitance C1 is the dielectric constant ε 1 of the material filling the space between the signal line 321 and the wiring 35, the thickness dl of the signal line 321 in the predetermined direction 90 (FIG. 2), and the signal line 321 and the wiring 35. The distance between δ 2 Using (Fig. 1), it is expressed as ε l 'dl / δ 2. In addition, the parasitic capacitance C2 is the dielectric constant ε 2 of the insulating plate 201, the width hi (FIG. 1) with respect to the extending direction of the signal line 321 when viewed from the predetermined direction 90, and Using the distance δ 1 (Fig. 2), it is expressed as ε 2 'hl / δ 1.

[0039] As shown in FIG. 5, when the wiring 311 is connected to the ground, the distance d between the integrated circuit 11 and the wiring 311 in the predetermined direction 90 is preferably 1 mm or less. This is because the distance d between the integrated circuit 11 and the wiring 311 is small, so that the electric field flowing from one side of the integrated circuit 11 and the wiring 311 to the other side is between the integrated circuit 11 and the wiring 311. This is because the noise leakage due to the electric field can be reduced as soon as the current flows.

FIG. 6 is a top view conceptually showing the integrated circuit 11 provided on the surface 21 a of the substrate.

The substrate includes a ground pattern 313 provided on the same surface 21 a as the integrated circuit 11. The ground pattern 313 surrounds the integrated circuit 11.

[0041] According to the above-described aspect, the noise generated in the integrated circuit 11 is caused to flow through the ground pattern 313, so that noise leakage to the outside can be reduced. In addition, since the area of the ground pattern 313 can be increased around the integrated circuit 11, it is possible to further reduce the leakage of noise to the outside. More preferably, the width h2 and h3 of the ground pattern is 4 mm or more.

The present invention has been described in detail. The above description is illustrative in all aspects, and the present invention is not limited thereto. It is understood that countless variations that are not illustrated can be envisaged without departing from the scope of the present invention.

Claims

The scope of the claims

[1] Insulating substrate (2);

Laminated between one surface (21a) and the other surface (21b) of the insulating substrate in a predetermined direction (90) of the insulating substrate via a part (202) of the insulating substrate in the predetermined direction First and second wires (311, 312) to be

First and second signal lines (321, 322; 331, 332) disposed on each of the one and the other of the surface;

A first via (323; 333) that connects the first and second signal lines to each other without being connected to the first and second wirings;

A second via (341; 342) connected to the first and second wirings and provided close to the first via;

Comprising a substrate.

[2] Third wiring (35) arranged on at least one of the surfaces (21a, 21b) without being connected to the first and second wirings

The substrate according to claim 1, further comprising:

[3] There are a plurality of the first vias and the second vias,

The substrate according to claim 1, wherein the plurality (343) of the second vias are arranged in a lattice pattern when viewed from the predetermined direction (90).

[4] There are a plurality of the first vias and the second vias,

The substrate according to claim 2, wherein the plurality (343) of the second vias are arranged in a lattice shape when viewed from the predetermined direction (90).

[5] The substrate according to any one of claims 1 to 4, and

An integrated circuit (11) provided on at least one of the surfaces (21a, 21b) of the substrate;

With

The integrated circuit is connected to one of the first and second wirings (311, 31 2) on the integrated circuit side,

The distance (d) between the integrated circuit and the one wiring in the predetermined direction (90) is An apparatus that is lmm or less.

A substrate according to any one of claims 1 to 4, and

A fourth wiring (313) provided on the same surface as the integrated circuit and surrounding the integrated circuit;

An apparatus comprising: