WO2007102644A1

WO2007102644A1 - Method of forming triple palladium- palladium-gold plating layer on high-density printed circuit board for solving the thickness deviation of plating and printed circuit board produced thereby

Info

Publication number: WO2007102644A1
Application number: PCT/KR2006/003644
Authority: WO
Inventors: Sung Wook Chun
Original assignee: Ymt Co., Ltd
Priority date: 2006-03-09
Filing date: 2006-09-13
Publication date: 2007-09-13
Also published as: KR100712033B1

Abstract

The present invention relates to a plating method for solving the thickness deviation of plating, which occurs in a high-density printed circuit board, and a printed circuit board produced thereby. This invention features that a first porous palladium (Pd) plating layer is formed on an exposed soldering portion and a wire-bonding portion of the printed circuit board, which is made of copper or copper alloy, by means of a substitution plating method, a secondary palladium or palladium alloy plating layer is formed on the first plating layer by means of an electroless reduction plating method, and then a gold (Au) or gold alloy plating layer is precipitated and formed on the second plating layer by means of the substitution plating method using the difference of ionization tendency.

Description

[DESCRIPTIONl [invention Title]

METHOD OF FORMING TRIPLE PALLADIUM-PALLADIUM-GOLD PLATING LAYER ON HIGH-DENSITY PRINTED CIRCUIT BOARD FOR SOLVING THE THICKNESS DEVIATION OF PLATING AND PRIINTED CIRCUIT BOARD PRODUCED THEREBY [Technical Field]

The present invention relates to a method of forming a plating layer for solving the thickness deviation of plating, which occurs in the application of palladium plating to a high-density printed circuit board by means of an electroless reduction plating method, and a printed circuit board produced thereby.

More particularly, this invention relates to a method of forming a triple palladium-palladium-gold plating layer on a high-density printed circuit board for solving the thickness deviation of plating, and a printed circuit board produced thereby, in which a first porous palladium (Pd) plating layer is formed on an exposed soldering portion and a wire-bonding portion of the printed circuit board, which is made of copper or copper alloy, by means of a substitution plating method, a secondary palladium or palladium alloy plating layer is formed on the first porous plating layer by means of an electroless reduction plating method, and then a gold (Au) or gold alloy plating layer is precipitated and formed on the second plating layer by means of the substitution plating method, thereby solving the thickness deviation of plating, which occurs from the difference of the potential due to the density difference of the pattern, thereby providing a high-density and high- reliability printed circuit board. [Background Art]

In general, a rigid printed circuit board, a flexible printed circuit board, and a rigid and flexible printed circuit board include a wire-bonding portion in order to surface mount a semi-conductor, and a soldering portion for mounting parts such as an IC chip, a RAM, and the like on the semi-conductor. In this regard, there is shown a planar photograph of a ball grid array (BGA) and a multi chip module (MCM) , which is a representative model of a strip type printed circuit board, and a camera module, in FIG. 1. The wire-bonding portion 23 and the soldering portion shown in FIG. 1 are typically formed of copper material. However, a copper layer exposed to the outside may be oxidized and abraded according to the lapse of time so that it is not possible to expect the special solderability and wire- bonding property. Accordingly, according to a widely known plating method, it is necessary to perform a nickel electroplating or an electroless nickel plating on the exposed copper layer, so as to provide the solderability and the wire-bonding property, thereby protecting the copper from an abrasion atmosphere, protecting the copper at a long storage conditions, and functioning as an interface plating between the copper and the gold to prevent inter-diffusion, and then providing conditions for enabling the wire-bonding by carrying out a gold electroplating or the electroless gold plating to a thickness within 0.5R

The plating method described above has been well known in the field to which the present invention pertains. In this regard, Korean Patent Laid-Open Publication No.2000-53621 disclosed a method of manufacturing a printed circuit board using a plating solution comprising at least one water-soluble gold compound, at least one conductive salt, at least one reducing agent, and water, after forming an electroless nickel phase on a copper exposed portion intended to be performed of the gold plating by using a photo-solder-resist (PSR) .

In addition, in Korean Patent Laid-Open Publication No. 2003-0080547, there was disclosed a method of forming an alloy plating layer comprising gold (Au) and silver (Ag) by using a gold-silver alloy plating solution, after performing an electroless nickel plating. Also, Japanese Patent Laid-Open Publication No. Hei 07-7243 disclosed the electroless plating method using a substitution reaction method as a principal reaction, in which a first amorphous electroless nickel film was formed on a copper portion intended to be performed of gold plating, and then a second crystalline electroless nickel film was formed thereon. Moreover, an improved technology of forming a nickel-gold plating layer on a copper layer was disclosed in US Patent No. 5,235,139 and NO. 6,733,823.

The reason of performing the thickness gold plating after performing the nickel or nickel alloy plating on the printed circuit board is as follows.

When a thin gold plating (flash gold plating, generally below 0.1 μm) is performed after the nickel or nickel alloy plating, the wire-bonding property is reduced so that it cannot reach a reference value. Accordingly, the thickness plating layer is required to satisfy the wire- bonding property. In this regard, if the gold thickness becomes above 0.5 μm in general, the force becomes above 5gf thereby satisfying the wire-bonding property. In this regard, a concrete example of the gold plating process of the conventional printed circuit board is shown in FIG. 2.

Referring now to FIG. 2, at first, a patterned circuit (not shown) and copper foil exposed portions 2, 3 are formed on a board 1 by a method well known to the field of art of the invention, and a photo solder resist layer 4 is formed on a remaining portion except a portion for the gold plating. An electrolytic nickel layer having a thickness about 0.5 μxa is formed on a copper foil exposed portion 2 of a CSP (not shown) , a BGA, or a camera module printed circuit board by using an electrolytic nickel plating solution, and then a gold plating layer 7 having a thickness above 0.5 μm is formed thereon by using an electrolytic gold plating. In this instance, a lead line is required for conducting electricity because the electroplating is used. In this regard, the lead line causes a noise phenomenon after the assembly of the semiconductor, because it is provided with a function of an antenna. Accordingly, the lead line may be removed by etching after the electroplating recently, however, it is difficult to remove it completely.

Meanwhile, as the MCM printed circuit board is not provided with a lead line, a gold plating layer 8 having a thickness above 0.5 μm is obtained by forming a nickel- phosphorus alloy layer 6 containing 5 to 9 wt% of phosphorus on the copper foil exposed portion 3 by treating at 85 ^°C for about 20 minutes by using the electroless nickel plating solution, and then passing through a flash gold plating solution (primary gold plating) containing a citric acid as a main component, and passing through a thickness gold plating solution (secondary gold plating) comprising sodium thiosulfate and sodium sulfite as reducing agent. The reason of performing the gold plating in sequence as a primary, and a secondary process is because the durability of the secondary gold plating solution is substantially reduced due to pollution of the copper, so that a buffering operation such as the primary plating is provided to protect the secondary gold plating solution. Thus, it is required for about 100 minutes at 85^°C to obtain the thickness of plating layer above 0.5 μm through the primary and secondary plating. Also, there is a disadvantage that production expense becomes high because the durability of the solution is too short.

In addition, when a part is surface mounted on a printed circuit board on which electroless nickel and electroless gold are plated, it was very difficult to solve the problem of black pad, in which parts are separated from the printed circuit board unexpectedly due to several causes such as the distribution of phosphorus (P) in a nickel-phosphorus alloy plating layer, stress of the plating layer produced in the plating process, and the like. Meanwhile, in a rigid-flexible, and a flexible printed circuit board which are used increasingly according to the compactness and multi-functions of the portable device, severe manufacturing processes such as a bending, a twisting, and the like have been employed. However, there occurred a serious problem that the printed circuit board manufactured through the electroless nickel plating and the electroless gold plating cannot be used for the flexible printed circuit board because bending cracks are produced due to the structure transformation arising from the thermal treatment and the inherent high hardness of the nickel Ni) - phosphorous (P) alloy.

Moreover, as the high density printed circuit board is principally used in products for low current, high frequency, it should be good at electric conductivity, however, the nickel-phosphorous alloy plating layer containing phosphorous (P) has a resistance of about 50 to 80Ω/cm and a plating thickness of 3 to 6 μm according to the content of phosphorous, so that it is not appropriate as material for low current and high frequency due to "skin effect", in which current flows along the surface of the plating layer.

Although a method of plating gold directly on a copper foil has been introduced because of the problems of nickel-phosphorous alloy plating layer, the solderability and the wire-bonding property are reduced because copper oxide was produced on the surface of the plating due to inter-diffusion between the copper and the gold. In this regard, attempt was performed to solve by electro-plating gold thicker than 0.5 μm, however, it was difficult to introduce and remove the lead line for the electroplating, and the productivity was very low thereby becoming a big trouble in the commercialization. Palladium (Pd) is good at several physical properties such as malleability, corrosion resistant property, and the like, so that it has been studied in respect of surface mounting technology, however, it was difficult to obtain uniform plating layer because thickness deviation of plating was produced due to potential difference arising from the density difference of the pattern, in case of the high density printed circuit board. [Disclosure] [Technical Problem] Accordingly, a wide range of studies have been repeated to solve such conventional problems, and it was found that uniform plating layer could be obtained by forming a very thin porous primary palladium plating layer by means of a substitution plating method, forming a palladium or a palladium alloy plating layer by means of an electroless reduction method, and then forming a very thin gold or gold alloy plating layer thereon, thereby showing special property sufficient to substitute the gold plating having an existing thickness, and removing the thickness deviation of plating. As a result, the present invention was accomplished based on above discoveries.

Accordingly, an object of the present invention is to provide a method of forming a triple palladium-palladium- gold plating layer for solving the thickness deviation of plating and printed circuit board produced thereby, which can solve the thickness deviation of the plating, which occurs from the potential difference due to the density difference of the pattern, and satisfy the solderability and the wire-bonding property required for the high density printed circuit board.

Another object of the present invention is to provide a method of forming a triple palladium-palladium-gold plating layer for solving the thickness deviation of plating and printed circuit board produced thereby, which can solve several technological problems arising from the existing surface treating technology for the surface mounting, such as bending cracks of the printed circuit board, and the production of the oxide on the surface of the plating due to inter-diffusion, reduce expenses for the resource materials, and increase the productivity drastically.

Still another object of the present invention is to provide a method of forming a triple palladium-palladium- gold plating layer for solving the thickness deviation of plating in the high density and high reliability printed circuit board and printed circuit board produced thereby, in which a plating layer is formed by an electroless plating method without a lead line in the entire process. [Technical Solution]

To achieve the above objects, the present invention provides a method of forming a triple palladium-palladium- gold plating layer for solving the thickness deviation of plating, which occurs in a high-density printed circuit board, the method comprising the steps of (a) providing a printed circuit board formed with a predetermined pattern, and including a wire-bonding portion for the surface mounting of a semiconductor and a soldering portion for the engagement with external parts/ (b) forming a photo solder resist layer on the remaining portion except the wire- bonding portion and the soldering portion of the printed circuit board; (c) forming a porous primary palladium plating layer on the wire-bonding portion and the soldering portion by means of a substitution plating method; (d) forming a secondary palladium or palladium alloy plating layer on the porous primary palladium plating layer by means of an electroless reduction plating method; and (e) forming an electroless gold or gold alloy plating layer on the secondary palladium or palladium alloy plating layer by means of contacting with a substitution type immersion plating solution, which comprises a water-soluble gold compound. In addition, the present invention provides a printed circuit board with a triple palladium-palladium alloy-gold plating layer for solving the thickness deviation of plating occurring in the printed circuit board, which is formed with a predetermined pattern and includes a wire- bonding portion for surface mounting a semiconductor and a soldering portion for the engagement with external parts, the printed circuit board comprising a copper or copper alloy layer for defining the wire-bonding portion and the soldering portion; a porous primary palladium plating layer formed on the copper layer or the copper alloy layer; an electroless secondary palladium or palladium alloy plating layer formed on the porous primary palladium plating layer; and an electroless gold or gold alloy plating layer formed on the secondary palladium or palladium alloy plating layer. [Description of Drawings]

FIG. 1 is a planar photograph schematically showing a structure of a printed circuit board of a general strip shape; FIG. 2 is a view schematically showing a plating process of a conventional printed circuit board;

FIG. 3 is a view schematically showing a plating method of a plating layer of a printed circuit board according to one concrete embodiment of the present invention;

FIG. 4 is a view showing s stacking structure of a plating layer according to one concrete embodiment of the printed circuit board of the present invention;

FIG. 5 is a planar photograph showing a testpiece of a flexible printed circuit board used in the measurement of the thickness deviation of plating of the present invention. [Mode for Invention]

The present invention is similar to the conventional art that it is related to a method for forming a plating layer of a high density printed circuit board and the printed circuit board produced thereby. However, the present invention is characterized by forming a palladium plating layer twice, and further performing a gold plating thereon, so that the present invention will be described in detail with reference to FIGs. 3 through 5.

To accomplish the object and other object of the present invention, the method of forming a plating layer of a printed circuit board of the present invention comprises the steps of (a) providing a printed circuit board 11 formed with a predetermined pattern, and including a wire- bonding portion for the surface mounting of a semiconductor and a soldering portion for the engagement with external parts, and (b) forming a photo solder resist layer 14 on the remaining portion except the wire-bonding portion and the soldering portion of the printed circuit board.

Also, it comprises the steps of (c) forming a porous primary palladium plating layer 15 on the wire-bonding portion and the soldering portion by means of a substitution plating method, and (d) forming a secondary palladium or palladium alloy plating layer 16 on the porous primary palladium plating layer 15 by means of an electroless reduction plating method.

In addition, it further comprises the steps of (e) forming an electroless gold or gold alloy plating layer 17 on the secondary palladium or palladium alloy plating layer 16 by contacting the secondary palladium or palladium alloy plating layer with a substitution type immersion plating solution, which comprises a water-soluble gold compound. Here, the primary palladium plating layer 15 is characterized by the palladium layer formed by means of a substitution reaction, and the secondary palladium or palladium alloy plating layer 16 formed by means of an electroless reduction plating method, is determined whether it is a pure palladium layer or a palladium alloy plating layer containing alloy element according to the kind of the reducing agent used in the electroless palladium plating solution. The secondary palladium alloy plating layer 16 is preferably composed of 94 to 99.9 wt% of palladium (pd) and 0.1 to 6 wt% of phosphorous (P) or boron (B) .

The gold alloy plating layer 17 is preferably composed of 99 to 99.99 wt% of gold and 0.01 to 1.0 wt% of any one of thallium (Tl) , selenium (Se) , and a combination thereof. The thickness of the porous primary palladium plating layer 15 is preferable to be in a range of 0.01 to 1.0 fM, the thickness of the secondary palladium or palladium alloy plating layer 16 is preferable to be in a range of 0.05 to 5.0 (M, and the thickness of gold or gold alloy plating layer 17 is preferable to be in a range of 0.01 to 0.25 μm.

Moreover, it is preferable that the step [c] is performed at 30 to 60 ^"C for 30 seconds to five minutes, the step (d) is preferable to be performed at 60 to 80°C for one minute to thirty minutes, and the step (e) is preferable to be performed at 70 to 90 ^°C for one minute to thirty minutes.

In addition, the printed circuit board 11 may be any one selected from a rigid printed circuit board, a flexible printed circuit board, and a rigid and flexible printed circuit board.

To accomplish the object of the present invention, there is also provided a printed circuit board with a triple palladium-palladium alloy-gold plating layer for solving the thickness deviation of plating occurring in the printed circuit board, which is formed with a predetermined pattern and includes a wire-bonding portion for surface mounting a semiconductor and a soldering portion for engagement with external parts, the printed circuit board comprising a copper or copper alloy layer for forming the wire-bonding portion and the soldering portion 12, 13; a porous primary palladium plating layer 15 formed on the copper layer or the copper alloy layer; an electroless secondary palladium or palladium alloy plating layer 16 formed on the porous primary palladium plating layer 15; and an electroless gold or gold alloy plating layer 17 formed on the secondary palladium or palladium alloy plating layer 16.

Hereinafter, the preferred embodiment of the present invention will be described in detail with reference to the appended drawings.

As described above, according to the present invention, there is provided a rigid printed circuit board, a flexible printed circuit board, and a rigid and flexible printed circuit board 11 for a high density and high reliability ball grid array (BGA) , a chip scale package (CSP) , or a camera module, and the like, by a simple and economic process, such as forming a primary porous palladium plating layer 15 on an exposed soldering portion and wire-bonding portion composed of copper or copper alloy of the printed circuit board, by means of a substitution plating method, and a secondary palladium or palladium alloy plating layer 16 by means of an electroless reduction plating method, and then precipitating a gold or gold alloy plating layer 17 by means of the electroless substitution plating method, thereby achieving the solderability and the wire-bonding property, obtaining a uniform plating layer without a thickness deviation, and forming the plating layer without a separate lead line for the electroplating.

In FIG. 3, there is shown a method of forming a plating layer of a high density printed circuit board according to one concrete embodiment of the present invention. According to the method of forming the plating layer of the present invention, a predetermined circuit pattern

(not shown), a wire-bonding portion 12, 13 for surface mounting the semiconductor, and a soldering portion (not shown) for engagement with external parts are primary formed on a rigid printed circuit board, a flexible printed circuit board, or rigid and flexible printed circuit board.

The above process is typically performed by a well known photolithography . Then, a solder resist layer 14 is formed by coating photo solder resist PSR on the printed circuit board 11, and the solder resist layer 14 functions as a resist for the plating. The solder resist layer 14 is coated by applying a film, and performed of exposing and developing, thereby selectively detaching the solder resist layer on from the wire-bonding portions 12, 13 and the soldering portion (not shown) .

After the completion of the above process, the wire- bonding portions 12, 13 and the soldering portion (not shown) are exposed to the outside, and a primary porous palladium plating layer 15 is formed thereon by means of a substitution plating method. The formation reaction of the primary palladium plating layer 15 is progressed as indicated by a reaction scheme (1) by means of the substitution plating method: [Reaction Scheme l]

Cu > Cu ²⁺ + 2e ^"

Pd ²⁺ + 2e ^" —→ Pd ° Pd ²⁺ (aq) + Cu (s) > Pd (s) + Cu ²⁺ (aq)

The porous primary palladium plating layer 15 is formed according to a substitution reaction represented by the reaction scheme 1. In this regard, palladium sulfuric acid (PdSO₄), palladium nitric acid (Pd(NO₃J₂), and palladium chloride (PdCl₂) are employed as a source for the palladium, and a palladium substitution plating solution (produced by Yuil Materials Technology Co. Ltd. ; product name, Pallamerse) can be used, in which boric acid is employed as a buffering agent, polyethylene glycol system anionic surfactant of 5 to 10 mol is employed as a wetting agent, and sulfuric acid, nitric acid, hydrochloric acid, and the like are used as a pH regulator to precipitate palladium on the copper, however, the present invention is not restricted to it.

The substitution palladium plating is performed at 30 to 60 ^°C for thirty seconds to five minutes thereby obtaining the porous palladium plating layer 15 having a thickness of 0.01 to l.Oμm. In this instance, when the plating temperature is below 30 ^°C or the plating time is shorter than thirty seconds, the thickness of the porous palladium plating layer becomes too thin, so that it is not effective to solve the problem of thickness deviation. Also, when the plating temperature is above 60 ^°C or the plating time is longer than five minutes, the effect of solving the thickness deviation is small and uneconomic in comparison with the increase of the thickness.

Then, the secondary electroless palladium or palladium alloy plating layer 16 is formed on the obtained primary porous palladium plating layer by means of the electroless reduction plating method. The method of forming the electroless palladium or palladium alloy plating layer 16 is as follows. As an example, the principle of plating the palladium on the copper by using sodium hypophosphite as a reducing agent is as represented by the following reaction schemes 2, 3:

[Reaction Scheme 2]

H₂PO₂ ^" + H₂O > H₃PO₃ ^" + H⁺ + e^" [Reaction Scheme 3] Pd²⁺ + 2e^" > Pd⁰

As for another example, the principle of plating the electroless palladium on the copper by using dimethyl amine borane (DMAB) as a reducing agent is as represented by the following reaction schemes 4, 5: [Reaction Scheme 4]

(CH₃) ₂NHBH₃ + 4OH^" -> (CH₃) ₂NH + BO₂ ^" + 3/2H₂ + 2H₂O + 3e^" [Reaction Scheme 5] Pd²⁺ + 2e^" > Pd⁰

The palladium plating layer is precipitated on the copper by means of the electroless reduction plating reaction as represented by the reaction schemes 2 to 5.

It is preferable in obtaining a dense palladium plating layer to perform the plating at a pH range of 4 to 10 by using an electoless palladium plating solution, in which palladium sulfuric acid (PdSO₄) , palladium nitric acid (Pd(NO₃J₂), and palladium ammonium chloride (Pd (NH₄) ₂C1) are employed as a palladium source, ethylene diamine tetra acetic acid and sodium salt thereof are used as a chelator, sodium hypophosphite and formic acid, and the like are used as a reducing agent, glucose is used as an assistant reducing agent, a thio-compound such as mercaptobenzothiazole, thiouranium, sodium thiosulfate, and the like are used as a stabilizer for the plating solution, sulfuric acid (H2SO4), ammonium hydroxide (NH4OH) , sodium hydroxide (NaOH) are used as a pH regulator. The electroless palladium plating is performed at about 60 to 80 ^°C for one to thirty minutes thereby obtaining the thickness of palladium plating layer of 0.05 to 5.0//m. In this instance, when the plating temperature is below 60 ^°C or the plating time is shorter than one minute, it is not possible to obtain the plating thickness sufficient to satisfy the solderability and the wire- bonding property, and when the plating temperature is above 80^°C or the plating time is longer than thirty minutes, as excessively thick plating layer is formed, it is not economic, and there is a possibility that uniform gold plating may not be accomplished at the following substitution reaction process.

As for the electroless palladium layer formed according to the electroless reduction plating method of the present invention, the pure palladium or palladium alloy plating layer 16 can be obtained depending on the reducing agent in the plating solution.

The palladium alloy plating layer 16 is preferably an alloy layer composed of 94 to 99.9 wt% Pd, and 0.1 to 6 wt% P or B.

When the palladium alloy plating layer 16 comprises palladium (Pd) - phosphorous (P) alloy layer, the content of phosphorous (P) is preferably 1 to 6 wt%. When the content of phosphorous is below 1 wt%, the solderability becomes increased but the corrosion resistant property and the wire-bonding property become decreased. On the contrary, when the content of phosphorous is above 6 wt%, the corrosion resistant property and the wire-bonding property are improved but the solderability becomes decreased.

Then, when the palladium alloy plating layer 16 comprises palladium (Pd) - boron (B) alloy layer, it is preferable to contain boron in an amount of 0.1 to 4 wt%. When the content of boron is below 0.1 wt%, the solderability becomes increased but the corrosion resistant property becomes decreased. On the contrary, when the content of boron is above 4 wt%, materials become weak due to increase of the hardness, and the solderability becomes decreased.

Next, the electroless gold or gold alloy plating layer 17 is formed on the electroless palladium or palladium alloy plating layer 16 so as to provide the solderability and the wire-bonding property by making the substitution type immersion gold plating solution containing water- soluble gold compound contacted with the electroless palladium or palladium alloy plating layer.

The plating layer 17 is formed as follows. The method of forming the gold or gold alloy plating layer 17 on the palladium or palladium alloy plating layer 16 is achieved according to a substitution reaction depending on an ionization tendency as represented by the reaction scheme 6. [Reaction Scheme β]

Pd (solid) + Au (liquid) -> Au (solid) + Pd (liquid)

The gold or gold alloy plating layer 17 is formed according to the reaction represented as above. As an example for the preferable electroless substitution gold plating solution used in the present invention, the electroless substitution gold plating solution prepared by Yuil Materials Technology Co. Ltd. (product name: PAGODA- gold) can be provided, in which potassium cyanic gold is used as a gold source, nitriloacetic sodium is used as a kilate, citric acid is used as a chelator, however, it is not particularly restricted. It is preferable that the pH of the electroless substitution gold plating solution is preferable to be 4 to 7. The plating is performed at 70 to 90 ^°C temperature for one to thirty minutes thereby obtaining the thickness of 0.01 to 0.25/ΛΠ of the gold or gold alloy plating layer 17. In this instance, when the plating temperature is below 70^°C or the plating time is shorter than one minute, it is difficult to obtain uniform outer appearance, and when the plating temperature is above 90 ^°C or the plating time is longer than thirty minutes, there occurs a disadvantage that a solder resist ink is apt to get loose and the gold or gold alloy plating layer becomes weak.

Especially, the gold alloy plating layer 17 formed according to the above described electroless gold plating, is preferably composed of Au of 99 to 99.99wt%, and at least one of Se or Tl of 0.01 to 1 wt% . In this regard, while the pure gold plating provides good solderability and wire-bonding property, there occurs an advantage that Tl (thallium) and/or Se (Selenium), which are used in the formation of the gold plating layer, are often functioned as a under-potential thereby accelerating a plating speed, and the precipitated texture becomes a granular texture so that it is adapted to the wire-bonding property. In FIG. 4, there is shown a preferred embodiment of a stacking structure of a plating layer of a printed circuit board of the present invention formed according to the above method.

Referring to FIG. 4, the printed circuit board of the present invention has a sequentially stacked structure that a porous primary palladium plating layer 200 is formed on an exposed copper foil 100 by means of the substitution plating method so as to form a wire-bonding portion and a soldering portion, an electroless palladium or palladium alloy plating layer 300 composed of palladium or palladium alloy is formed thereon by means of the electroless reduction plating method, and a gold or gold alloy plating layer 400 is formed on the electroless palladium or palladium alloy plating layer respectively. The electroless palladium or palladium alloy plating layer 300 is very good at solderability and the wire-bonding property. Thus, it becomes good at wettability at the time of soldering thereby realizing the good surface mounting property. Also, the porous primary palladium plating layer 200 is formed by the substitution plating method, and functions as a seed layer to remove the thickness deviation of plating caused by the potential difference due to the density difference of the pattern of the high density printed circuit board.

The thickness of the porous primary palladium plating layer 200 is preferably to be 0.01 to 1[M. When the thickness of the palladium plating layer is below O.Olμm, the function as the seed layer becomes weak so that it is not possible to solve the problem of thickness deviation of plating, and when the plating thickness is above l.Oμm, the contribution effect of solving the thickness deviation in comparison with the increase of the thickness is small and uneconomic.

The electroless palladium or palladium alloy plating layer 300 prevents the diffusion of the copper or copper alloy to the outside plating layer and functions as a support at the time of the soldering and the wire-bonding. In this instance, the thickness of the electroless palladium or palladium alloy plating layer 300 is 0.05 to 5.0μm, more preferably to be 0.1 to ljCffli. When the thickness of the palladium or palladium alloy plating layer 300 is O.lμm, the corrosion resistant property of the copper or copper alloy is not good, and when the thickness of the palladium or palladium alloy plating layer 300 is above

1. Oμm, it becomes brittle due to the increase of the stress.

The thickness of the gold or gold alloy plating layer 400 formed on the palladium or palladium alloy plating layer 300 is preferably 0.01 to 0.25μm. When the thickness of the gold or gold alloy plating layer 400 is below O.Olμm, it is difficult to prevent the corrosion of the electroless palladium or palladium alloy plating layer, and when it is above 0.25j«m, it is uneconomic because it does not greatly contribute to the improvement of the quality in comparison with the increase of the thickness, and the texture becomes brittle. Accordingly, the printed circuit board of the present invention, which is formed by sequentially stacking a copper or copper alloy layer, a porous primary palladium plating layer, a secondary palladium or palladium alloy plating layer formed by means of the electroless reduction plating method, and an electroless gold or gold alloy plating layer, has following advantages.

First; it is possible to prepare a high density printed circuit board requiring a solderability and a wire- bonding property because it is possible to solve thickness deviation of plating, which occurs from the potential difference due to the density difference of the pattern of the high density printed circuit board, thereby providing the uniform electroless palladium plating.

Second; it is possible to prepare a high density rigid, a flexible, or a rigid and flexible printed circuit board because it is possible to produce the BGA, CSP, and camera module without a lead line in case of the printed circuit board for the BGA, CSP, and camera module, thereby drastically removing noise and increasing the circuitry as the number of the lead line increases. Third; a separate removing process (for instance, etching back) of the lead line is not required, so that the process can be simplified.

Fourth; it is possible to substitute the thickness gold plating (0.5μm) with a flash gold plating of about 0.1//m, thereby enabling the reduction of the production expense by above 60%.

Fifth; since the plating process is similar to the widely applied electroless nickel/gold plating process, it is possible to use a present production facility with only substituting a simple plating bath thereby reducing the novel facility investment expense.

Sixth; electric power supply is not required for all the processes. As described above, the method of forming the plating layer of the printed circuit board 11 according to the present invention can solve the thickness deviation of plating occurring from the potential difference due to the density difference of the pattern of the high density printed circuit board 11, and satisfy several physical properties such as a solderability, a wire-bonding property, and a flexibility, and the like required for the high density and high reliability printed circuit board with thin plating thickness, thereby greatly reducing the production expense. Also, it is possible to drastically intercept the noise occurrence due to the lead line because it is possible to manufacture the printed circuit board without a lead line by a simple process, in case of a printed circuit board for the CSP, BGA, or the camera module, so that it is possible to manufacture the high density BGA, CSP, and camera module having more circuitry lines than before.

In addition, palladium has a high hardness, a good malleability, and an excellent corrosion resistant property so that it can be adapted for a connector and a printed circuit board. Accordingly, it can prevent a problem of black pad frequently originating at the surface mounting of the printed circuit board, which is performed of the conventional electroless nickel and the electroless gold plating, and prevent the deadly bending cracks occurring at the time of manufacturing the rigid-flexible, and the flexible printed circuit board, which have been widely used in the portable device such as a portable telephone with reduced size and gradually complicating functions, because it represents good physical property with thin thickness. In particular, the method of forming the plating layer of the present invention can be applied to all kinds of printed circuit board. The present invention will be understood in more detail by the embodiments described below, and the embodiments are only illustrative object, and are not intended to restrict the scope of the present invention. In the below embodiment, a printed circuit board (size 400 X 505mm, thickness 0.2 ± 0.02mm, thickness of the copper layer is 10 to 3OjUm) , in which a photo solder resist layer produced from Daiyo Inc. as product name of AS-303, is applied to a portion except the soldering portion requiring the solderability with the solder ball, and the wire- bonding portion made of copper material, is fat-removed (product name of PAGODA Cleaner produced from Yuil Materials Technology Co., Ltd.) at 45^°C for three minutes and etched (product name of PAGODA Microetchant produced from Yuil Materials Technology Co., Ltd.) by 0.5 to 1. OJEM to remove oxides on the copper layer, thereby accomplishing the pre-treatment .

Then, the porous primary palladium plating layer is formed on the printed circuit board completed of the pretreatment by means of the substitution plating method. The substitution palladium plating process comprises basically performing a preliminary immersion treatment, a substitution palladium main bath treatment, and a pickling treatment. The preliminary immersion treatment is performed using a substitution palladium preliminary immersion solution (product name of Pallamerse pre-dip produced from Yuil Materials Technology Co., Ltd.), and the pickling treatment after the plating is performed by immersing into a 5% sulfuric acid at room temperature for one minute. After the preliminary immersion, a substitution palladium treatment (product name of Pallamerse produced from Yuil Materials Technology Co., Ltd.) is performed with changing the conditions as described in the Examples to form a porous primary palladium plating layer, and performs the pickling in 5% sulfuric acid solution, and then performs the water pickling. Then, the electroless palladium or palladium alloy plating and the gold or gold alloy plating are sequentially performed by using an electroless palladium plating solution (product name of PDR produced from Yuil Materials Technology Co., Ltd.).

When the gold or gold alloy plating is completed, a post-treatment is selectively performed by using chemicals

(product name of POST PAGODA produced from Yuil Materials Technology Co., Ltd.) containing materials pertaining to triazole to intensify hydrophile property of the plating layer, and performing the water pickling, and drying, and comparing the results of the post-treatment. Example 1 A porous primary palladium plating layer was formed on a copper layer of a printed circuit board accomplished of the pretreatment as described above by performing the plating of the substitution palladium at 50 ^°C for one minute, a palladium (Pd) - phosphorus (P) alloy plating layer containing palladium and phosphorus in a content ratio of 97.7 : 2.3 (wt%) was formed thereon to an average thickness of 0.2μm by means of the electroless palladium plating method, and then a gold plating layer having a thickness of 0.05jUm was formed thereon.

Example 2

The plating layer was formed by a method identical with that of Example 1 except that the palladium (Pd) boron (B) alloy plating layer containing palladium and boron in a content ratio of 99.5:0.5 (wt%) is formed in place of palladium (Pd) and phosphorus (P).

Example 3

The plating layer was formed by a method identical with that of Example 1 except that a pure palladium plating layer is formed in place of the palladium alloy plating layer.

Example 4

The plating layer was formed by a method identical with that of Example 1 except that an average thickness of the gold plating layer is 0.15μm.

Example 5

The plating layer was formed by a method identical with that of Example 1 except that an average thickness of the gold plating layer is 0.25j«m. Example 6

The plating layer was formed by a method identical with that of Example 1 except that the substitution palladium plating process is performed at 60^°C for one minute to form the porous primary palladium plating layer.

Example 7

A porous primary palladium plating layer was formed on a copper layer of the printed circuit board accomplished of the pretreatment as described above by performing the plating of the substitution palladium at 50°C for one minute, a palladium-phosphorus alloy plating layer containing palladium and phosphorus in a content ratio of

97.7 : 2.3 (wt%) was formed thereon to an average thickness of 0.4μm by means of the electroless palladium plating method, and then a gold plating layer having a thickness of

0. lμm was formed thereon.

Example 8

The plating layer was formed by a method identical with that of Example 7 except that an average thickness of the palladium-phosphorus alloy plating layer is 0.9μm.

Example 9

The plating layer was formed by a method identical with that of Example 1 except that an average thickness of the gold alloy plating layer containing 99.98wt% of gold and 0.02 wt% of thallium, respectively was is 15μm.

Example 10

The plating layer was formed by a method identical with that of Example 1, and post-treatment was performed by immersing the plating layer into a post-treatment solution at 50°C for two minutes, and then the resultant product was dried.

Comparative Example 1

The printed circuit board sample was manufactured by performing a catalyst treatment of the printed circuit board completed of the above described pretreatment, instead of the substitution palladium plating, forming a palladium plating layer having an average thickness of

0.2//m by an electroless palladium plating, and then forming a gold plating layer having an average thickness of 0.08μm.

Comparative example 2

The printed circuit board sample was manufactured by performing catalyst treatment of the printed circuit board completed of the above described pretreatment, forming a nickel-phosphorus alloy plating layer having a thickness of 5jt/m and containing nickel and phosphorus by a content ratio of 91,3:8.7 (wt%) by the electroless palladium plating, and then forming a gold plating layer having a thickness of 0. lμm by means of the electroless substitution gold plating method.

Comparative example 3

The printed circuit board sample was manufactured by forming a tin plating layer completed of the pretreatment as described above and having a thickness of 1.2/zm by means of the substitution reaction, and forming a gold plating layer having a thickness of 0.05μm by means of the electroless gold plating method after performing the catalyst treatment. %■ The substitution palladium plating solution used in the formation of the porous primary palladium plating layer in the above Examples is represented in Table 1. [Table l]

Palladium source (unit: g/ & )

The plating method and conditions used in the above described Examples in the formation of the secondary palladium or palladium alloy plating layer by means of the electroless reduction plating method is as follows. Plating is performed at 70^°C with using solutions having components represented in tables 2a, 2b, and 2c to obtain a palladium alloy plating layer composed of a palladium-phosphorus or a palladium-boron or a pure palladium plating layer by means of the electroless reduction plating method.

The principle of the palladium plating performed on the copper layer is as follows. The plating time ranging from about one to thirty minutes is required to obtain a plating thickness included in the present invention. [Table 2a]

- Electroless palladium plating solution composition: pure palladium plating solution composition

[Table 2b]

- Electroless palladium plating solution composition: palladium-phosphorus alloy plating solution composition

[Table 2c]

- Electroless palladium plating solution composition: palladium-boron alloy plating solution composition

The thickness change of the palladium alloy according to the lapse of time obtained by plating with using a plating solution as described above is represented in table 3.

[Table 3]

Thickness change of the palladium or palladium alloy plating layer according to the lapse of time

Plating solutions having a composition represented in table 4 are used so as to form the electroless gold or gold alloy plating layer on the above obtained electroless palladium alloy plating layer. [Table 4]

Gold plating or gold alloy plating solution composition

Plating is performed at 85 ^°C temperature and in the range of pH 4.5 to 5.0 (pH is regulated by the sulfuric acid) with the plating solution as described above thereby obtaining the thickness change of the gold or gold alloy plating layer according to the lapse of time as represented in table 5.

[Table 5]

Thickness change of the gold or gold alloy plating layer according to the lapse of time

The method of forming the gold or gold alloy plating layer on the electroless palladium or palladium alloy plating layer is described above. It is required to perform the plating for about one to thirty minutes to obtain the plating thickness pertained to the present invention.

After forming the plating layer according to the method and conditions described above, water pickling was performed, the obtained plating layer was dried at 80 ^°C for fifteen minutes, and then a solderability and a wire- bonding property were measured according to the conditions and the method described below. In table 7, property evaluation results such as thickness deviation of plating, solderability, wire-bonding property, bending property, and ion migration, and the like are represented. <Thickness of the plating layer>

To confirm the solving of the thickness deviation of plating, which is one of the important object of the present invention, plating is performed for each Example by using a flexible printed circuit board having a pattern shown in FIG. 5 as a sample, and then the thickness deviation between the maximum thickness and the minimum thickness of the palladium or palladium alloy plating layer and gold or gold alloy plating layer is measured and compared. %. Evaluation device:

Measuring device of plating thickness: CMI 900 produced from CMI company limited.

<Solderability> The solderability is evaluated by performing a solder ball shear test and a solder ball malleability test.

1) Solder ball test

^ Conditions:

Bonding Tester: DAGE 4000 Location: 5μm

Shear speed: 200μm/sec

Ball size: 0.35mmΦ (Alpha Metal Co.)

Ball material: Sn/Ag/Cu (96.5/3/0.5) wt%

Flux (RMA type): EF-9301 (Alpha Metal co . ) Reflow Machine: KOKI

Reflow Conditions: 250°C (Peak Temperature)

^ Evaluation method:

This is to evaluate a connection strength between a soldering pad portion and a solder ball, when a ball shear test is performed by securing a test-piece formed with a solder bump at conditions described above and defining a predetermined load and a shear height, the stylus pushes the bump thereby producing the fracture, and then the value of fracture is measured. %i Evaluation standard:

When the ball shear strength exceeds 200gf, it is determined to be normal.

2) Malleability test of the solder ball ^ Conditions:

Solder ball size: 0.35mmΦ (Alpha Metal Co.)

Ball material: Sn/Ag/Cu (96.5/3/0.5) wt%

Flux (RMA type): EF-9301 (Alpha Metal Co.)

Reflow Machine: KOKI Reflow conditions: 250^°C (Peak temperature)

^ Evaluation method:

The size of the solder ball is measured after the ball having a diameter of 0.35mmΦ is located and passed through the reflow machine, after performing the flux treatment of the soldering pad portion. If the solder ball spreads farther, in other words, if the ball size becomes larger, the solderability is determined to be good.

%. Evaluation standard:

When the ball spread more than three times the solder ball grain size (that is, more than 1.05mmΦ), it is determined that the shear strength exceeds 200gf, and the solderability is determined to be normal.

<Wire-bonding property>

This is to test adhesion force of a bonding wire and a wire-bonding portion. K&S 1484 was used as a wire-bonding test machine. Bonding conditions represented in table 6 are given after performing thermal aging at 175^°C for one hour.

[Table β] Bonding conditions

In the table, minimum and average forces (unit: gf) required for the separation of the bonding from the wire- bonding were represented, and if the minimum force was above 3g/f and the maximum force was above 5g/f, they are determined to be good.

^ Evaluation Method:

Test pieces having a shape regulated by IPC 9201 were prepared, a porous primary palladium plating layer was formed thereon, a secondary palladium or palladium alloy plating layer was formed thereon by means of the electroless plating, and the electroless gold plating layer was formed thereon, and then they were charged into a constant temperature and humidity chamber of an Ion Migration Measuring Device (SIR system) , and then the change of the surface insulation resistance values were measured for 500 hours with applying a high temperature and high humidity environment. The test conditions were applied of relative humidity of 85%, temperature of 85^°C, direct voltage of 50V, and the resistivity of the water used at this instance was 10~18MΩ/cm.

%. Evaluation standard: When the ion migration was produced at the plating layer, the surface insulation resistance value was reduced, and when the surface insulation resistance value of the test piece was reduced below 1X1O⁶Ω, it was determined that the migration was produced and it was not good. <Bending Cracks>

%. Evaluation method: Bending Radius [R] = 2.0mm Test piece width: 1 cm Balance Weight: lOOg Bending angle: 180^°

RPM = 25

Number of the test piece: 10 pes

%. Evaluation standard: When the test pieces were performed of bending more than 10 times according to the evaluation method, if a bending crack was not produced on the surface of the test piece, it was determined to pass the test.

Example 11 Reliability evaluations were performed as follows about the printed circuit boards obtained from Example 1 to Example 9.

It was confirmed by means of naked eye whether porosity was produced due to the corrosion of the structure of the palladium or palladium alloy plating layer and the gold or gold alloy plating layer after immersing the high- density printed circuit board performed of the plating into the nitric acid. [Table 7] Evaluation of the special properties

%■ The values of the ball malleability test and the wire-bonding test are average values obtained by measuring twenty times.

^A: Average plating layer (jtffli) ; B: Solderability, C: Wire-bonding property, D: Surface insulation resistance ( Ω ), E: Bending crack, F: Plating thickness (μm) , G: Ball shear strength (gf) , H: Ball malleability (mmφ), I: Number of initiating occurrence of cracks

<Heat resistant property test> It was confirmed that, after passing through three times at the temperature conditions as represented in table 8 by using a reflow, whether the surface color of the palladium or gold plating layer was changed, and whether the palladium or palladium alloy plating layer and the gold or gold plating layer was separated by using an adhesion tape.

It was confirmed whether the palladium or palladium alloy plating layer was separated, and whether the gold or gold alloy plating layer was separated from the solder, when the test piece was pulled by a predetermined force after performing the welding on the soldering portion with an aluminum wire by using the solder, and passing the test piece at a temperature condition represented in table 8 by using a reflow.

According to the test results, it is shown that the plating layers manufactured according to the Examples of the present invention satisfy the property required for the above items.

[Table 8] Evaluation of the special property

O : Meets the standard, as a result of the test.

As tested above, according to the present invention, several physical properties of the high-density printed circuit board solve completely the thickness deviation of plating, which occurs from the potential difference due to the density difference of the pattern and indicated as technical problems in the application of the palladium plating with good several properties.

Also, it is possible to manufacture a rigid printed circuit board, in which the BGA, the CSP, and the camera module, and the like are surface mounted thereon because a separate lead line is not required for the electroplating thereby increasing the density of the circuit, and a rigid and flexible, and flexible printed circuit boards, in which the BGA, the CSP, the camera module, and the like are surface mounted thereon, and the soldering and the wire- bonding are instantly applied.

Accordingly, it is possible to omit an etching back process to remove the unnecessary lead line by means of an etching process thereby simplifying the work.

Also, it is possible to drastically reduce the production expense and improve the productivity by substituting the wire-bonding, which could be performed by the thickness gold plating, with the plating layer composed of the gold or gold alloy plating layer formed on the thin palladium or palladium alloy plating layer.

In addition, it is possible to completely solve the problem of black pad, which occurs frequently at the time of the surface mounting of the printed circuit board, on which the electroless nickel and the electroless gold were plated, since palladium is a metal appropriate for a connector and a printed circuit board because it has a high hardness, it is good at malleability and excellent for the corrosion resistant property, and it can satisfy the required properties with only a thin plating thickness thereby enabling the substitution of the conventional electroless nickel plating and the electroless gold plating process.

Especially, it is possible to prevent the deadly bending cracks occurring at the time of manufacturing the rigid and flexible, and the flexible printed circuit board, which are widely used for the portable devices such as a portable phone, whose functions become gradually complex and whose size become compact recently.

Above all, the method of forming the plating layer of the present invention has an advantage that it can be applied to all kinds of printed circuit boards. As described above, the present invention has been explained in connection with the concrete Examples, however, this is performed only in view of the illustrative purpose. The method of forming a plating layer of a high density printed circuit board, and the printed circuit board produced thereby of the present invention are not limited to the Examples, and it is apparent that the present invention can be changed and modified by those skilled in the art within the scope of the spirit of the present invention. [industrial Applicability]

As described above, according to the present invention, a porous palladium plating layer is formed primarily on a copper layer of a rigid, a flexible, or a rigid and flexible printed circuit board by means of the substitution plating method, an electroless palladium alloy plating layer composed of pure palladium, palladium-phosphorus, or palladium-boron is formed thereon by means of the electroless reduction plating method, and a gold or gold alloy plating layer is formed on the pure palladium or electroless palladium alloy plating layer by means of the electroless immersion plating method, thereby forming the plating layer of the printed circuit board.

Thus, it is possible to solve an unequal plating problem produced from the thickness deviation of plating, which frequently occurs in the high density printed circuit board, to protect the pure palladium or palladium alloy plating layer from an outside corrosion atmosphere, and to improve a packaging reliability with the semiconductor because it is good at solderability and the wire-bonding property.

Also, the present invention has an advantage that the process can be simplified because the lead line is not necessary so that it is possible to omit the etching process, in case of the printed circuit board with leads such as for the BGA, the CSP, and the camera module, because all of the plating layers are formed by means of the electroless reduction plating method or the immersion plating method. In addition, it is possible to increase the density of the circuitry drastically so that it is possible to manufacture the high density PCB for the BGA, the CSP, and the camera module.

Moreover, in case of the rigid, flexible, and rigid and flexible printed circuit board without a lead line, such as the MCM, and the camera module, it is possible to ensure the wire-bonding property with a thin thickness at the time of the gold plating after the palladium plating, and reduce the time necessary for the process, thereby bringing about the drastic reduction of the production expense .

While the present invention has been explained with reference to the embodiments, they are only illustrative purposes, and it is understood by those skilled in the art to which the present invention pertains, that the present invention can be variously modified and changed without departing from the scope of the present invention. Accordingly, the substantial technical protection scope of the present invention will be defined by the appending claims .

Claims

[CLAIMS] [Claim l]

A method of forming a triple palladium-palladium-gold plating layer for solving the thickness deviation of plating, which occurs in a high-density printed circuit board, the method comprising the steps of:

(a) providing a printed circuit board 11 formed with a predetermined pattern, and including a wire-bonding portion for the surface mounting of a semiconductor and a soldering portion for engagement with external parts;

(b) forming a photo solder resist layer 14 on the remaining portion except the wire-bonding portion and the soldering portion of the printed circuit board;

(c) forming a porous primary palladium plating layer 15 on the wire-bonding portion and the soldering portion by means of a substitution plating method;

(d) forming a secondary palladium or palladium alloy plating layer 16 on the porous primary palladium plating layer 15 by means of an electroless reduction plating method; and

(e) forming an electroless gold or gold alloy plating layer 17 on the secondary palladium or palladium alloy plating layer 16 by contacting the secondary palladium or palladium alloy plating layer with a substitution type immersion plating solution, which comprises a water-soluble gold compound. [Claim 2]

The method of forming a plating layer according to claim 1, wherein the porous primary palladium plating layer 15 is a pure palladium layer formed by means of a substitution reaction. [Claim 3]

The method of forming a plating layer according to claim 1, wherein the secondary electroless palladium alloy plating layer 16 comprises 94 to 99.9 wt% of palladium (Pd) and 0.1 to 6 wt% of phosphorous (P) or boron (B) . [Claim 4]

The method of forming a plating layer according to claim 1, wherein the gold alloy plating layer 17 comprises 99 to 99.99 wt% of gold (Au) and 0.01 to 1.0 wt% of any one of thallium (Tl), selenium (Se) and a combination thereof. [Claim 5]

The method of forming a plating layer according to claim 1, wherein the porous primary palladium plating layer 15 has a thickness ranging from 0.01 to lμm. [Claim 6]

The method of forming a plating layer according to claim 1, wherein the secondary electroless palladium or palladium alloy plating layer 16 has a thickness ranging from 0.05 to 5.0μm. [Claim 7]

The method of forming a plating layer according to claim 1, wherein the gold or gold alloy plating layer 17 has a thickness ranging from 0.01 to 0.25//m. [Claim 8]

The method of forming a plating layer according to claim 1, wherein the step (c) is performed at 30 to 60^°C for thirty seconds to five minutes. [Claim 9]

The method of forming a plating layer according to claim 1, wherein the step (d) is performed at 60 to 80^°C for three to thirty minutes. [Claim lθ]

The method of forming a plating layer according to claim 1, wherein the step (e) is performed at 70 to 90°C for one to thirty minutes.

[Claim 11] The method of forming a plating layer according to claim 1, wherein the printed circuit board 11 is selected from any one of a rigid printed circuit board, a flexible printed circuit board, and a rigid and flexible printed circuit board. [Claim 12 ]

A printed circuit board with a triple palladium- palladium alloy-gold plating layer for solving the thickness deviation of plating, occurring in the printed circuit board, which is formed with a predetermined pattern and includes a wire-bonding portion for surface mounting a semiconductor and a soldering portion for engagement with external parts, the printed circuit board comprising: a copper or copper alloy layer for forming the wire- bonding portion and the soldering portions 12, 13; a porous primary palladium plating layer 15 formed on the copper or the copper alloy layer; an electroless secondary palladium or palladium alloy plating layer 16 formed on the porous primary palladium plating layer 15; and an electroless gold or gold alloy plating layer 17 formed on the secondary palladium or palladium alloy plating layer 16.

[Claim 13] The printed circuit board according to claim 12, wherein the porous primary palladium plating layer 15 is a pure palladium layer formed by means of a substitution reaction. [Claim 14] The printed circuit board according to claim 12, wherein the secondary palladium alloy plating layer 16 comprises 94 to 99.9 wt% of palladium (Pd) and 0.1 to 6 wt% of phosphorous (P) or boron (B) . [Claim 15]

The printed circuit board according to claim 12, wherein the gold alloy plating layer 17 comprises 99 to 99.99 wt% of gold (Au) and 0.01 to 1.0 wt% of any one of thallium (Tl), selenium (Se) and a combination thereof. [Claim 16]

The printed circuit board according to claim 12, wherein the porous primary palladium plating layer 15 has a thickness ranging from 0.01 to lμm.

[Claim 17] The printed circuit board according to claim 12, wherein the secondary electroless palladium or palladium alloy plating layer 16 has a thickness ranging from 0.05 to 5.0/ffli.

[Claim 18] The printed circuit board according to claim 12, wherein the gold or gold alloy plating layer 17 has a thickness ranging from 0.01 to 0.25μm. [Claim 19]

The printed circuit board according to claim 12, wherein the printed circuit board 11 is any one selected from a rigid printed circuit board, a flexible printed circuit board, and a rigid and flexible printed circuit board.