KR100712033B1 - Palladium-gold plating process to solve a large thickness distribution on high density printed circuit board and printed circuit board produced therefrom - Google Patents

Abstract

The present invention relates to a plating method and a printed circuit board manufactured therefrom for eliminating the variation in plating thickness appearing in a high density printed circuit board, the soldering portion and the wire bonding portion exposed to copper (Cu) or copper alloy of the printed circuit board After forming a porous primary palladium (Pd) plating layer by substitution plating on the secondary layer, and again forming a secondary palladium (Pd) or palladium alloy plating layer by electroless reduction plating on the plating layer, and then on the substitution plating method using the difference in ionization tendency By depositing a plating layer made of gold (Au) or a gold alloy to form a plating layer.

According to the present invention, high hardness, good electrical conductivity and excellent corrosion resistance can satisfy the required properties even with a thin plating thickness by using a plating of palladium metal suitable for a connector and a printed circuit board. Can be saved.

In addition, it is possible to completely solve the black pad problem that occurs frequently in the surface mount technology of the conventional electroless nickel and electroless gold plated printed circuit boards, and in particular, a rigid and flexible printed circuit board It is possible to prevent the fatal bending crack (cending crack) that occurs during the manufacturing of.

In spite of these advantages, palladium (Pd) plating by electroless reduction does not have uniform thickness due to the potential difference due to the potential difference due to the density difference of the pattern in high density printed circuit board. There was a limit to the application because it requires or another plating method must be used.

In the present invention, first, a porous palladium (Pd) plating layer is thinly formed by substitution plating, and a secondary palladium (Pd) or palladium alloy plating layer is formed by electroless reduction plating, and finally gold (Au) is substituted by substitution plating. ) Or the gold (Au) alloy plating layer to solve the thickness variation problem in the palladium (Pd) plating.

Printed Circuit Board, Plating Thickness Variation, Soldering, Wire Bonding, Palladium Plating, Gold Plating, BGA, MCM, CSP, Hard, Rigid, Flexible Printed Circuit Board

Description

Palladium-gold plating process to solve a large thickness distribution on high density printed circuit board and printed circuit board produced therefrom}

1 is a planar photo schematically illustrating a structure of a printed circuit board in a general strip form;

2 is a view schematically showing a plating process of a conventional printed circuit board,

3 is a view schematically showing a plating layer forming method of a printed circuit board according to an embodiment of the present invention;

4 is a view showing a laminated structure of a plating layer according to an embodiment of the printed circuit board of the present invention;

5 is a planar photograph showing a flexible printed circuit board specimen used for measuring the thickness variation of the present invention.

※ Explanation of code about main part of drawing ※

1, 11 printed circuit board

2, 12 BGA or copper exposed area of camera module

3, 13 MCM or copper exposed areas of camera module

4, 14 photosolder layer

5 Electrolytic nickel plated layer of BGA or camera module

6 Electroless Nickel Alloy Plating Layer on MCM or Camera Module

7 Electrolytic gold plated layer of BGA or camera module

8 Electroless Gold Plated Layer on MCM or Camera Module

15 Porous Primary Palladium Plating Layer

16 Electroless Palladium or Palladium Alloy Plating Layer

17 Gold Plating or Gold Alloy Plating Layer

100 copper plating or copper alloy plating layer

200 porous palladium plated layers

300 electroless palladium or palladium alloy plating layer

400 Electroless Gold or Gold Alloy Plating Layer

The present invention relates to a plating layer forming method and a printed circuit board manufactured therefrom to solve the plating thickness variation which remains a great challenge in applying palladium plating by electroless reduction plating to a high density printed circuit board. More specifically, the present invention forms a porous palladium plating layer first by substitution plating on the copper exposed portion of the high-density printed circuit board, and the second palladium by plating palladium or palladium alloy by electroless reduction plating on the porous primary palladium plating layer Alternatively, a palladium alloy plating layer is formed, and a gold plating or gold alloy plating layer is formed by electroless substitution plating thereon to eliminate the plating thickness variation caused by the potential difference due to the density difference of the pattern, thereby achieving a high density and high reliability printed circuit board. The present invention relates to a triple palladium-palladium-gold plated layer formation method and a printed circuit board manufactured therefrom, which solve the plating thickness variation.

In general, a rigid, flexible or rigid printed circuit board includes a portion where wire bonding is required for mounting with a semiconductor, and there are other soldering portions for mounting a printed circuit board with components such as an IC chip and a RAM. . In this regard, a planar photograph of a BGA, a multi chip module (hereinafter referred to as MCM), and a camera module, which are typical models of a strip-shaped printed circuit board, is illustrated in FIG. 1. The portions 2 and 3 and the soldering portions (not shown) that require wire bonding shown in FIG. 1 are typically made of copper. However, this externally exposed copper layer is oxidized and corroded over time, so soldering and wirebonding characteristics cannot be expected. Therefore, to provide soldering and wirebonding properties, electronickel plating or electroless nickel plating is applied on the exposed copper layer to protect copper from corrosive atmospheres, and to protect copper even under long-term storage conditions while interfacing between copper and gold. It is a widely used method to provide a condition for wire bonding by acting as a plating to prevent mutual diffusion and then electroplating or electroless gold plating to about 0.5㎛.

In general, such a plating process is widely known in the art, for example, Korean Patent Publication No. 2000-53621 forms an electroless nickel phase on a copper exposed portion to be gold plated using photosolder resist (PSR). Next, a method of manufacturing a printed circuit board using a plating solution including at least one water-soluble gold compound, at least one conductive salt, at least one reducing agent, and water is provided.

In addition, Korean Patent Publication No. 2003-0080547 discloses a method of providing an alloy plating layer made of gold (Au) and silver (Ag) using a gold-silver alloy plating solution after electroless nickel plating. In addition, Japanese Patent Application Laid-open No. Hei 7-7243 forms an amorphous first electroless nickel film on a copper portion to be gold plated, and forms a crystalline second electroless nickel film, followed by an electroless having a substitution reaction as a main reaction. Gold plating method is presented. In addition, improved techniques for forming a nickel-gold plated layer on a copper layer are disclosed in US Pat. Nos. 5,235,139 and 6,733,823.

The reason for the thickness gold plating after nickel or nickel alloy plating in a printed circuit board is as follows.

In the case of thin gold plating (flash gold plating, usually 0.1 μm or less) after nickel or nickel alloy plating, wire bonding property is inferior and falls short of the standard value. Therefore, a thick gold plated layer is required to satisfy the wire bonding property, and when the thickness of gold is 0.5 μm or more, a force of 5 gf or more can be obtained to obtain a satisfactory wire bonding value.

In this regard, an example of a schematic gold plating process of a conventionally known printed circuit board is shown in FIG. 2.

Referring to FIG. 2, first, a portion to be gold-plated after forming a patterned circuit (not shown) and copper-exposed portions 2 and 3 on the substrate 1 according to methods well known in the art The photosolder resist layer 4 is formed in the remaining portions except for the above.

An electrolytic nickel layer 5 of about 5 μm is formed on the copper-exposed portion 2 of the CSP (not shown), BGA, or camera module printed circuit board by using an electrolytic nickel plating solution, and then electroplated. A gold plated layer 7 of 탆 or more is formed. In this case, since the electroplating is used, there must be a lead wire that needs to be energized, and the lead wire has an antenna action, which causes noise after assembly of the semiconductor. Therefore, there is a case where the lead wire is removed by etching after the recent electroplating, in which case it is difficult to remove it completely.

On the other hand, in the case of the MCM printed circuit board, since there is no lead wire, the phosphorous (P) content is 5 to 9% by weight by using an electroless nickel plating solution on the copper exposed portion 3 for 20 minutes at 85 ° C. The nickel-phosphorus alloy layer 6 is formed to a thickness of about 5 μm, and then a flash gold plating solution (primary gold plating) mainly composed of citric acid, and a thick gold plating solution using sodium thiosulfate and sodium sulfite as reducing agents. (Secondary gold plating) to obtain a gold plated layer 8 of 0.5 µm or more. The reason why gold plating is carried out in the first and second periods is to protect the secondary gold plating solution by buffering the first plating because the life of the plating solution is significantly reduced by copper contamination in the second gold plating solution.

Thus, a processing time of about 100 minutes is required at 85 ° C. to obtain a thickness of 0.5 μm or more over the first and second steps. In addition, there is a disadvantage that the life of the liquid is too short to consume a lot of production costs.

In addition, due to various factors such as the distribution of phosphorus (P) in the nickel-phosphorus alloy plating layer and the stress of the plating layer generated during the plating process when surface mount technology is applied to the electroless nickel and electroless gold plated printed circuit boards. It is very difficult to solve the so-called black pad problem, in which parts fall unexpectedly.

Meanwhile, in rigid and flexible printed circuit boards, which are rapidly increasing in use due to the miniaturization and multifunction of portable devices, harsh manufacturing processes such as bending and torsion have been introduced, but the electroless nickel plating and electroless plating layers have been introduced. In the case of a printed circuit board, a bending crack occurs due to the high hardness of the nickel-phosphorus alloy and the texture transformation due to heat treatment, which causes a fatal problem that cannot be used in a flexible printed circuit board.

In addition, the high density printed circuit board is mainly used for low current and high frequency, so the electrical conductivity should be excellent, but the nickel-phosphorus alloy plating layer containing phosphorus (P) has a resistance of about 50 to 80 Ω / cm depending on the phosphorus content. It has a plating thickness of 3 to 6 μm and is not suitable for low current and high frequency materials due to the 'skin effect' that current flows along the surface.

Due to the problems of the nickel-phosphorus alloy plating layer, a method of plating gold directly on the copper foil has been introduced, but the soldering and wire bonding characteristics are deteriorated due to the generation of copper oxide on the plating surface due to the mutual diffusion of copper and gold. To solve this problem by plating a thicker than 0.5㎛ by electroplating, but the introduction and removal of the lead wire for electroplating is difficult and the productivity is very low, there is a big difficulty in commercialization.

Palladium (Pd) has been studied as a surface treatment technology for mounting because of its excellent physical property such as electrical conductivity and corrosion resistance.However, in the case of high density printed circuit boards, variation in plating thickness occurs due to the potential difference due to the density difference of the pattern, thereby obtaining a uniform plating layer. There is no problem.

Accordingly, in the present invention, as a result of extensive research to solve the problems of the prior art, a very thin porous palladium plating layer was formed by substitution plating, and a palladium or palladium alloy plating layer was formed by electroless reduction. Subsequently, by forming a very thin gold or gold alloy plating layer thereon, it was found to exhibit sufficient characteristics to replace the existing thickness gold plating, and at the same time eliminate the plating thickness variation to obtain a uniform plating layer. It is finished.

It is also an object of the present invention to satisfy the weldability and wire bonding properties required for high density printed circuit boards, and to provide uniform plating by eliminating the variation in plating thickness caused by the potential difference according to the density of the pattern. The present invention provides a triple palladium-palladium-gold plated layer formation method and a printed circuit board manufactured therefrom that solve the variation in plating thickness of a substrate.

Another object of the present invention is to solve various technical problems in the existing surface treatment technology such as bending cracks in printed circuit boards and oxides of the plating surface by mutual diffusion, and at the same time, significantly reduce cost and increase productivity. The present invention provides a triple palladium-palladium-gold plated layer formation method and a printed circuit board manufactured therefrom that solve the plating thickness variation of the high density printed circuit board.

It is still another object of the present invention to provide a triple palladium-palladium-gold plated layer in which a plating layer is formed through an electroless plating process without a lead wire to solve the plating thickness variation of a high density and high reliability printed circuit board. It is to provide a printed circuit board manufactured therefrom.

Accordingly, the present invention provides a method for forming a plating layer of a high density printed circuit board, comprising: (a) a wire bonding part for semiconductor mounting and a soldering part for coupling with external components, and providing a printed circuit board having a predetermined circuit pattern formed thereon; Making a step; (b) forming a photo solder resist layer on portions of the printed circuit board other than the wire bonding portion and the soldering portion; (c) forming a porous primary palladium plating layer by substitution plating on the wire bonding portion and the soldering portion; (d) forming a secondary palladium or palladium alloy plating layer on the porous primary palladium plating layer by electroless reduction plating; And (e) contacting the submerged immersion gold plating solution containing a water-soluble gold compound on the secondary palladium or palladium alloy plating layer to form an electroless gold or gold alloy plating layer. To solve the triple palladium-palladium-gold plated layer formation method.

The present invention also includes a wire bonding part for semiconductor mounting and a soldering part for coupling with external components, and in a printed circuit board having a predetermined circuit pattern, a copper or copper alloy layer forming the wire bonding part and a soldering part; ; A porous primary palladium plating layer formed on the copper layer or the copper alloy layer; An electroless secondary palladium or palladium alloy plating layer formed on the porous primary palladium plating layer; An electroless gold or gold alloy plating layer formed on the secondary palladium or palladium alloy plating layer; to provide a printed circuit board having a triple palladium-palladium-gold plating layer to solve the plating thickness variation of the high-density printed circuit board formed by plating .

The present invention is similar to the conventional one in that it is a method of forming a plated layer of a high density printed circuit board and the printed circuit board.

However, palladium plating is made over a second time, and the gold plating on the upper part of the present invention will be described in detail with reference to FIGS. 3 to 5.

Method for forming a plating layer of a printed circuit board according to the present invention for achieving the above object and other objects, (a) including a wire bonding portion for the semiconductor mounting and a soldering portion for coupling with external components, a constant circuit pattern is formed The step of providing the printed circuit board 11, and (b) the step of forming the photo solder resist layer 14 in the portion other than the wire bonding portion and the soldering portion of the printed circuit board.

In addition, (c) forming a porous primary palladium plating layer 15 by substitution reaction of the wire bonding portion and the soldering portion, and (d) by electroless reduction plating on the porous primary palladium plating layer 15. The second palladium or palladium alloy plating layer 16 is formed.

In addition, (e) the second palladium or palladium alloy plating layer 16 is finished by contacting the substitution type immersion gold plating solution containing a water-soluble gold compound to form the electroless gold or gold alloy plating layer (17).

Here, the primary palladium plating layer 15 is a palladium layer formed by a substitution reaction, and the secondary palladium or palladium alloy plating layer 16 formed by electroless reduction plating is a reducing agent used in an electroless palladium plating solution. It is determined whether it is a pure palladium layer or the palladium alloy plating layer containing an alloying element according to the kind of. The secondary palladium alloy plating layer 16 is preferably made of 94 to 99.9% by weight of palladium (Pd), and 0.1 to 6% by weight of phosphorus (P) or boron (B).

The gold alloy plating layer 17 is preferably made of 99 to 99.99% by weight of gold (Au), and 0.01 to 1.0% by weight of thallium (Tl), selenium (Se), or a combination thereof.

Preferably, the porous primary palladium plating layer 15 has a thickness of 0.01 to 1.0 μm, and the secondary palladium or palladium alloy plating layer 16 preferably has a thickness of 0.05 to 5.0 μm, and a thickness of the gold plating or gold alloy plating layer 17. It is preferable that it is 0.01-0.25 micrometer.

On the other hand, step (c) is preferably carried out for 30 seconds to 5 minutes at a temperature of 30 to 60 ℃, step (d) is preferably performed for 1 to 30 minutes at a temperature of 60 to 80 ℃. And, step (e) is preferably performed for 1 to 30 minutes at a temperature of 70 to 90 ℃.

The printed circuit board 11 may be a rigid, flexible or rigid printed circuit board 11.

Printed circuit board according to the present invention for achieving the above and other objects,

In a printed circuit board including a wire bonding part for semiconductor mounting and a soldering part for coupling with external components, and having a predetermined circuit pattern, copper or a copper alloy forming the wire bonding part and the soldering parts 12 and 13. A layer; A porous primary palladium plating layer 15 formed by substitution reaction on the copper layer or the copper alloy layer; A second electroless palladium or palladium alloy plating layer 16 formed by electroless reduction plating on the porous primary palladium plating layer 15; An electroless gold or gold alloy plating layer 17 formed on the secondary palladium or palladium alloy plating layer 16; It is formed by plating.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

As described above, according to the present invention, the porous primary palladium plating layer 15 and the electroless reduction by the substitution reaction of the soldering portion and the wire bonding portion exposed to the copper (Cu) or copper alloy of the printed circuit board 11 The secondary palladium or palladium alloy plating layer 16 is formed by the reaction, and the plating layer 17 made of gold (Au) or gold (Au) alloy is deposited thereon by electroless substitution plating to secure weldability and wire bonding property. In addition, it is possible to obtain a uniform plating layer without variation in thickness, and to form a plating layer without a separate lead wire for electroplating.BGA (Ball Grid Array) and CSP (Chip Scale Package) having high density and high reliability through a simple and economic process ), Or a rigid, flexible or rigid printed circuit board 11, such as a camera module.

3 shows a method of forming a plating layer of a high density printed circuit board according to an embodiment of the present invention.

According to the plating layer forming method of the present invention, first, a predetermined circuit pattern (not shown) on the rigid, flexible or rigid printed circuit board 11, the wire bonding portions 12, 13 and external components for semiconductor mounting Forming a soldering portion (not shown) for bonding with the process is typically by photolithography, which is well known in the art.

Next, a photo solder resist PSR is applied to the printed circuit board 11 to form a solder resist layer 14, which serves as a resist for plating, which will be described later. The dry film is applied to the solder resist layer 14 and selectively exfoliates only the solder resist layer portions on the wire bonding portions 12 and 13 and the soldering portion (not shown) through exposure and development.

After the process is completed, the wire bonding portions 12 and 13 and the soldering portions (not shown) are exposed to the outside to form a porous primary palladium plating layer 15 by substitution plating thereon. The reaction of forming the porous primary palladium plated layer 15 by the substitution plating is as follows.

Cu ^- → Cu ²⁺ + 2e -

Pd ²⁺ + 2e ^-―― → Pd ⁰

Pd ²⁺  (aq) + Cu (s) ― → Pd (s) + Cu ²⁺  (aq)

As shown in Scheme 1, a porous primary palladium plating layer 15 is formed by a substitution reaction. Palladium sulfate (PdSO ₄ ), palladium nitrate (Pd (NO ₃ ) ₂ ) or palladium chloride (PdCl ₂ ) is formed in the substituted palladium plating. Substituted palladium plating solution using sulfuric acid, nitric acid, hydrochloric acid as a palladium source, boric acid as a buffer, polyethylene glycol nonionic surfactant (5 mol to 10 mol) as a humectant, and a pH regulator for precipitation of palladium on copper, respectively. The material technology name Pallamerse) may be used but is not particularly limited thereto.

The substituted palladium plating is performed at a temperature of about 30 to 60 ° C. for 30 seconds to 5 minutes to obtain a porous palladium plated layer 15 having a thickness of 0.01 to 1.0 μm. At this time, if the plating temperature is less than 30 ℃ or the time is shorter than 30 seconds, the thickness of the porous palladium plating layer is too thin to solve the thickness deviation, and if the temperature exceeds 60 ℃ or time exceeds 5 minutes to increase the thickness In comparison, the effect of contributing to resolving thickness variation is insignificant, which is uneconomical.

The secondary electroless palladium or palladium alloy plating layer 16 by electroless reduction plating is formed on the porous primary palladium plating layer. The method for forming the electroless palladium or palladium alloy plating layer 16 is as follows.

As an example, the principle of plating palladium on copper using sodium hypophosphite as a reducing agent is shown in Schemes 2 and 3 below.

^{_{H 2 PO 2 - + H 2}} O ----> H 3 PO 3 - + H + + e -

^{Pd 2 + + 2e - ---->} Pd 0

As another example, the principle of plating electroless palladium on copper using dimethylamine borane (DMAB) as a reducing agent is as shown in Schemes 4 and 5.

_{(CH 3) 2 NHBH 3 +} 4OH - ----> (CH 3) 2 NH + BO 2 - + 3 / 2H 2 + 2H 2 O + 3e -

^{Pd 2 + + 2e - ---->} Pd 0

Palladium (Pd) precipitates on a copper layer by the electroless reduction plating reaction shown by said Reaction Formulas 2-5.

As an electroless palladium plating solution, palladium sulfate (PdSO ₄ ), palladium chloride (PdCl ₂ ) or ammonium palladium hydrochloride (Pd (NH ₄ ) ₂ Cl) is used as a palladium source, and ethylenediaminetetraacetic acid and its sodium salt are used as a complexing agent. Thio compounds such as sodium hypophosphite, formic acid, and the like as a reducing agent, glucose (glucose) as an auxiliary reducing agent, mercaptobenzothiazole as a plating solution stabilizer, thiourea, sodium thiosulfate, using sulfuric acid pH control agent (H ₂ SO _4), ammonia water (NH ₄ OH), sodium hydroxide (NaOH) it is preferable to obtain a dense palladium plating layer working in the range of pH 4~10.

The electroless palladium plating is carried out at a temperature of about 60 to 80 ℃ 1 minute to 30 minutes to obtain a palladium or palladium alloy plating layer thickness of 0.05 to 5.0㎛. At this time, if the plating temperature is less than 60 ℃ or the time is shorter than 1 minute, the plating thickness to satisfy the required weldability and wire bonding properties can not be obtained, and if the temperature exceeds 80 ℃ or time exceeds 30 minutes, There is a fear that gold plating is not uniformly performed by the substitution process, which is an uneconomical and subsequent process, because a thick plating layer is formed.

The electroless palladium layer formed by the electroless reduction plating method of the present invention described above can obtain pure palladium or palladium alloy plating layer 16 depending on the reducing agent in the plating solution.

The palladium alloy plating layer 16 is preferably an alloy layer composed of 94 to 99.9% by weight of palladium (Pd) and 0.1 to 6% by weight of phosphorus (P) or boron (B).

When the palladium alloy plating layer 16 is made of a palladium-phosphorus alloy layer, the content of phosphorus (P) is preferably 1 to 6% by weight. If the phosphorus content is less than 1% by weight, the solderability is improved while the corrosion resistance and wire bonding resistance is lowered, and if it exceeds 6% by weight, the corrosion resistance and wire bonding resistance is improved while the solderability is inferior.

When the palladium alloy plating layer 16 is made of a palladium-boron alloy layer, the content of boron (B) is preferably 0.1 to 4% by weight. If the content is less than 0.1% by weight, the weldability is improved while the corrosion resistance is lowered, and if the content exceeds 4% by weight, the material becomes weak due to the increase in hardness (hardness) and the solderability is deteriorated.

Then, in order to impart solderability and wire bonding properties, the electroless gold or gold alloy plating layer 17 is brought into contact with the substitution type immersion gold plating solution containing a water-soluble gold compound on the electroless palladium or palladium alloy plating layer 16. ).

The method of forming the plating layer 17 is as follows.

The method of forming the gold or gold alloy plating layer 17 on the palladium or palladium alloy alloy plating layer 16 is established by a substitution reaction according to the ionization tendency as shown in Scheme 6 below.

Pd (solid) + Au (liquid) ----> Au (solid) + Pd (liquid)

According to the reaction shown above, a gold or gold alloy plating layer 17 is formed.

Examples of the preferred electroless substitution gold plating solution used in the present invention include gold cyanide as a gold source, nitriloacetic soda with chelating agent, and electroless substitution gold plating solution containing citric acid as a complexing agent. PAGODA-Gold) and the like, but are not particularly limited thereto. It is preferable that pH of the said electroless substitution gold plating solution is 4-7.

The plating is performed for 1 to 30 minutes at a temperature of 70 to 90 ℃ to obtain a gold or gold alloy plating layer 17 thickness of 0.01 to 0.25㎛. At this time, if the plating temperature is less than 70 ℃ or the time is less than 1 minute, it is difficult to obtain a uniform appearance, and if the temperature exceeds 90 ℃ or the time exceeds 30 minutes, solder resist ink is easy to be lifted and gold Or there is a disadvantage that the gold alloy plating layer is weak.

In particular, in the case of the gold alloy plating layer 17 formed according to the above-mentioned electroless gold plating, 99 to 99.99 wt% of gold (Au) and 0.01 to 1 wt% of at least one of selenium (Se) and thallium (Tl) may be used. It is preferable that it consists of a structure containing.

Pure gold plating alone is excellent in solderability and wire bonding, but thallium (Tl) and / or selenium (Se) used to form a gold alloy plated layer has an advantage of accelerating the plating speed because it acts as an under potential and precipitates. The structure becomes granular structure and is suitable for wire bonding property.

A preferred example of the laminated structure of the plating layer of the printed circuit board of the present invention formed according to the above-described method is shown in FIG.

Referring to FIG. 4, in the printed circuit board of the present invention, a porous primary palladium plating layer 200 is formed by substitution plating on the copper foil 100 exposed to form the wire bonding portion and the soldering portion, and the electroless is disposed thereon. An electroless palladium or palladium alloy plating layer 300 made of palladium or palladium alloy is formed by reduction plating, and a gold or gold alloy plating layer 400 is formed on the electroless palladium or palladium alloy plating layer, respectively. Has

The gold or gold alloy plating layer 400 formed on the electroless palladium or palladium alloy plating layer 300 has excellent soldering properties and wire bonding properties. It has good wettability during soldering and can exhibit excellent mounting characteristics.

The porous primary palladium plating layer 200 is formed by substitution plating, and serves as a seed layer to eliminate the plating thickness variation caused by the potential difference due to the pattern density difference of the high density printed circuit board. The thickness of the porous primary palladium plating layer 200 is preferably 0.01 to 1㎛. If the thickness of the palladium layer is less than 0.01㎛ the role of the seed layer is not able to solve the plating thickness variation, if it exceeds 1.0㎛ it is uneconomical because the effect of reducing the thickness variation compared to the thickness increase is insignificant .

The electroless palladium or palladium alloy plating layer 300 prevents copper and copper alloys from diffusing into the outer plating layer and serves as a support for soldering and wire bonding. At this time, the thickness of the electroless palladium or palladium alloy plating layer 300 is 0.05 to 5.0㎛, more preferably 0.1 to 1㎛. When the thickness of the electroless palladium or palladium alloy plating layer 300 is less than 0.1 μm, there is a problem in corrosion resistance of copper and copper alloys, and when it exceeds 1.0 μm, it becomes vulnerable due to an increase in stress.

The thickness of the gold or gold alloy plating layer 400 to be plated on the electroless palladium or palladium alloy plating layer 300 is preferably 0.01 to 0.25㎛. When the thickness of the gold or gold alloy plating layer 400 is less than 0.01 μm, it is difficult to prevent corrosion of the electroless palladium or palladium alloy plating layer, and when the thickness of the gold or gold alloy plating layer 400 is greater than 0.25 μm, it does not contribute significantly to quality improvement compared to the thickness increase. It has the disadvantage of being uneconomical and fragile.

As described above, the printed circuit board of the present invention is formed by sequentially laminating a copper or copper alloy layer, a porous primary palladium plating layer, a secondary palladium or palladium alloy plating layer by electroless reduction plating, and an electroless gold or gold alloy plating layer. It has the following advantages.

first ; In the high density printed circuit board, uniform electroless palladium plating can be applied by solving the variation in the plating thickness caused by the potential difference due to the difference in density of the pattern, thus making it possible to manufacture a high density printed circuit board requiring soldering and wire bonding properties.

second ; In the case of printed circuit boards such as BGA, CSP, and camera module, it is possible to produce BGA, CSP, and camera module without lead wire, which can fundamentally eliminate noise, and the circuit can be increased as much as lead wire, so that high-density rigid, flexible or rigid printing It is possible to manufacture a circuit board.

third ; A separate lead wire removal process (eg, etch back) is unnecessary, which simplifies the process.

fourth ; Thickness plating (0.5㎛) can be replaced with flash gold plating of 0.1㎛, which can reduce the cost more than 60%.

fifth ; The plating process is almost similar to the electroless nickel / gold plating process, which is widely applied in the past, so that the existing production equipment can be used as it is simply by replacing the plating tank, so the new equipment investment cost is low.

Sixth; No power is required for all processes.

As described above, the plating layer forming method of the printed circuit board 11 according to the present invention can eliminate the variation in the plating thickness caused by the potential difference due to the pattern density difference of the high density printed circuit board 11, even with a thin plating thickness As it can satisfy the characteristics such as weldability, wire bonding property and bendability required for high density and high reliability printed circuit board, there is a great cost reduction effect. In addition, in the case of CSP, BGA, or camera module printed circuit board, a printed circuit board without a lead wire can be manufactured by a simple process, thereby fundamentally preventing noise caused by the lead wire. , CSP, camera modules can be manufactured.

In addition, palladium is a metal suitable for connectors and printed circuit boards because of its high hardness, good ductility, and excellent corrosion resistance, and exhibits excellent characteristics even with a thin plating thickness, so that conventional electroless nickel and electroless gold plated printed circuits are used. In addition to the black pad problem that frequently occurs during surface mount technology, the flexible and flexible printed circuit boards are widely used in portable devices such as mobile phones, which are becoming more complicated and smaller in size. Critical bending cracks that occur during manufacturing can be prevented. In particular, the plating layer forming method of the present invention can be applied to all kinds of printed circuit boards.

The present invention can be more clearly understood by the following examples, the following examples are only for the purpose of illustrating the invention and are not intended to limit the scope of the invention.

In the following example, a printed circuit board (size 400) coated with a photosolder resist layer (trade name AS-303 manufactured by Daiyo Ink Co., Ltd.) on a portion excluding a soldering portion requiring weldability between a copper wire bonding portion and a solder ball. Decompose x505 mm, thickness 0.2 ± 0.02 mm, copper layer thickness of 10-30 μm at 45 ° C. for 3 minutes (trade name PAGODA Cleaner of Soil Materials Technology Co., Ltd.), and the thickness of 0.5 to 0.5 to remove the oxide of the copper layer. Pretreatment was performed by 1.0 micrometer etching (trade name PAGODA Microetchant of the only material technology).

Next, a porous primary palladium plating layer was formed on the printed circuit board after the pretreatment through substitution plating. The substituted palladium plating process was carried out based on three steps of preliminary dipping treatment, substituted palladium main treatment and pickling treatment. The pre-soaking treatment was performed using a substituted palladium pre-immersion liquid (trade name Pallamerse pre-dip of KK Material Technology), and the pickling treatment after plating was performed by immersion for 5 minutes at room temperature in a 5% sulfuric acid solution.

After the preliminary immersion, the conditions were changed in the same manner as in the Examples, and the substitutional palladium treatment (Pallamerse Co., Ltd.) was formed to form a porous primary palladium plated layer, followed by pickling in a 5% sulfuric acid solution and washing with water.

Thereafter, electroless palladium or palladium alloy plating and gold or gold alloy plating were sequentially performed using an electroless palladium plating solution (trade name PDR of KK Material Technology).

After finishing the plating of gold or gold alloy, after finishing treatment by using a chemical agent (trade name POST PAGODA of Only Materials Technology Co., Ltd.) containing triazole-based substances, it is optionally post-treated and washed with water and dried. The effect of the treatment was compared.

Example 1

Substituting palladium for 1 minute at 50 ° C. on the copper layer of the printed circuit board pre-processed as described above to form a porous primary palladium plating layer, and palladium: phosphate 97.7: 2.3 (wt%) by electroless palladium plating. After forming a palladium-phosphorus alloy plating layer contained in the content of c) to an average thickness of 0.2 μm, a plating layer having a gold plating thickness of 0.05 μm was formed thereon.

Example 2

A plating layer was formed in the same manner as in Example 1, except that a palladium-boron alloy plating layer including palladium-boron in an amount of 99.5: 0.5 (wt%) was formed instead of palladium-phosphorus.

Example 3

A plating layer was formed in the same manner as in Example 1 except that the pure palladium plating layer was formed instead of the palladium alloy.

Example 4

A plating layer was formed in the same manner as in Example 1 except that the gold plating thickness was 0.15 μm on average.

Example 5

A plating layer was formed in the same manner as in Example 1 except that the gold plating thickness was an average of 0.25 μm.

Example 6

A plating layer was formed in the same manner as in Example 1 except that the substituted palladium plating process for forming the porous primary palladium plating layer was performed at 60 ° C. for 1 minute.

Example 7

Substituting palladium for 1 minute at 50 ° C. on the copper layer of the printed circuit board pre-processed as described above to form a porous primary palladium plating layer, and palladium: phosphate 97.7: 2.3 (wt%) by electroless palladium plating. The palladium-phosphorus alloy plating layer included in the content of c) was formed to an average thickness of 0.4 µm, and then a gold plating layer having an average thickness of 0.1 µm was formed thereon.

Example 8

A plating layer was formed in the same manner as in Example 7, except that the palladium-phosphorus alloy plating layer had an average thickness of 0.9 μm.

Example 9

A plating layer was formed in the same manner as in Example 1, except that an average thickness of the gold alloy plating layer containing 99.98 wt% and 0.02 wt% of gold (Au) and thallium (Tl) was 0.15 μm.

Example 10

After the plating layer was formed in the same manner as in Example 1, it was immersed in a 50 ° C. post-treatment solution for 2 minutes to perform post-treatment and dried.

Comparative Example 1

After the pretreatment of the printed circuit board is subjected to catalytic treatment instead of substituted palladium plating, an electroless palladium plating layer forms an average palladium plating layer having an average thickness of 0.2 μm, and an electroless substitution plating is performed thereon, whereby an average gold plating layer having an average thickness of 0.08 μm is used. Formed.

Comparative Example 2

After the pretreatment of the printed circuit board as described above, a nickel-phosphor alloy plating layer containing nickel: phosphorus in a content of 91.3: 8.7 (wt%) by electroless nickel plating was formed to have a thickness of 5 μm, followed by electroless The gold plated layer was formed to have a thickness of 0.1 μm by dissolution plating.

Comparative Example 3

As described above, the tin plated layer was formed to a thickness of 1.2 μm by the substitution reaction of the printed circuit board after the pretreatment, and a gold plated layer having a thickness of 0.05 μm was formed by electroless gold plating after the catalyst treatment.

※ In the above embodiment, the substituted palladium plating solution used to form the porous primary palladium plating layer is as follows.

                                                      (Unit: g / ℓ)             Palladium Source Components Palladium sulfate Palladium nitrate Palladium chloride Palladium sulfate 2 Palladium nitrate 2 Palladium chloride 2 Sulfuric acid 50 nitric acid 50 Hydrochloric acid 50 Boric acid 10 10 10 Nonionic surfactant 5 5 5

In the above embodiment, the plating method and conditions used to form the secondary palladium or palladium alloy plating layer by electroless reduction plating are as follows.

In order to obtain a pure palladium plating layer or a palladium alloy plating layer made of palladium-phosphorus or palladium-boron by electroless reduction plating, plating was performed at a temperature of 70 ° C. with a solution having the composition shown in Tables 2a, 2b, and 2c.

The principle of palladium plating on a copper layer is as above-mentioned. In order to obtain the thickness of the range included in the present invention, a plating time of about 1 minute to 30 minutes is required.

-Composition of electroless palladium plating solution: Composition of pure palladium plating solution ingredient content Remarks Palladium sulfate 2g / ℓ Sulfuric acid (95%) 10 g / ℓ Ethylenediaminetetraacetic acid 10 g / ℓ Succinic acid 15 g / ℓ Formic acid 10 g / ℓ stabilizator 5 ppm Accelerator 2 ppm Caustic soda 5-7 g / ℓ pH regulator

-Composition of electroless palladium plating solution: Composition of palladium-phosphorus alloy plating solution ingredient content Remarks Palladium chloride 2 g / ℓ Ammonium chloride 10 g / ℓ Ethylenediaminetetraacetic acid 10 g / ℓ Sodium hypophosphite 10 g / ℓ Citric acid 15 g / ℓ stabilizator 5 ppm Accelerator 2 ppm  ammonia 8-10 g / ℓ pH regulator

-Composition of electroless palladium plating solution: Composition of palladium-boron alloy plating solution ingredient content Remarks Palladium chloride 4g / ℓ Trimethylamineborane 2.5 g / ℓ Mercaptobenzothiazole 3.5 mg / l ammonia 10 ~ 15g / ℓ pH regulator stabilizator 3 ppm Accelerator 1 ppm

Plating with the plating solution of the composition described above, the thickness change over time of the palladium alloy plating layer was obtained as shown in Table 3 below.

Thickness change of palladium or palladium alloy plating layer with time Time (min) Thickness (㎛) One 0.05 5 0.8 10 1.7 20 3.3 30 5

In order to form an electroless gold or gold alloy plating layer on the formed electroless palladium alloy plating layer, a plating solution having a composition as shown in Table 4 below was used.

Gold Plating or Gold Alloy Plating ingredient content Remarks Sodium Phosphate 20 ~ 50g / ℓ Nitriloacetic soda 50 ~ 100g / ℓ Citric acid ammonium 50 ~ 100g / ℓ Thallium carbonate 10-50 ppm Only used for alloy plating Selenium oxide 10-50 ppm Only used for alloy plating Cyanide 2 ~ 5g / ℓ Cyanide 1 ~ 10g / ℓ

The plating liquid of the above composition was plated within a temperature range of 85 ° C. and pH 4.5 to 5.0 (pH adjustment with sulfuric acid) to obtain a thickness change with time of the gold plating or gold alloy plating layer as shown in Table 5 below.

Thickness change of gold plating or gold alloy plating layer with time  Time (min) Thickness (㎛) One 0.01 5 0.08 10 0.15 20 0.20 30 0.25

The method of forming the gold or gold alloy plating layer on the electroless palladium or palladium alloy plating layer is as described above. In order to obtain the thickness included in the invention, a plating time of about 1 to 30 minutes is required.

After the plating layer was formed by the same method and conditions as described above, it was washed with water, dried at 80 ° C. for 15 minutes, and then weldability and wire bonding property were measured by the following conditions and methods. Table 7 shows the results of evaluation of characteristics such as plating thickness variation, weldability, wire bonding property, flexibility, and ion migration according to Examples and Comparative Examples.

<Thickness of the plating layer>

Palladium or palladium alloy plating layer and gold or gold alloy plating layer after plating according to the above embodiment using a flexible printed circuit board having a pattern as shown in FIG. The highest and lowest thickness deviations were measured and compared.

※ Evaluation Equipment:

Plating thickness gauge: CMI 900 from CMI

<Weldability>

The weldability was subjected to a solder ball shear test and a solder spread test.

1) solder ball shear test

※ Condition :

Bond Tester: DAGE 4000

Location: 5㎛

Shear Speed: 200㎛ / sec

Ball size: 0.35mmΦ (Alpha Metal Co.)

Ball Material: Sn / Ag / Cu (96.5 / 3 / 0.5) Weight%

Flux: RMA type: EF-9301 (Alpha Metal Co.)

Reflow Machine: KOKI

Reflow Conditions: 250 ° C (peak temperature)

※ Assessment Methods :

This is to measure the connection strength between soldering pad and solder ball. When the ball shear test is performed by fixing a specimen with solder bumps on the table under the above conditions and setting a constant load and shear height, the stylus The breakage occurs by pushing the bump, and the value is then measured.

※ Evaluation standard :

If the ball shear strength exceeds 200gf, no abnormality is assumed.

2) Solder Ball Spreadability Test

※ Condition :

Solder Ball Size: 0.35mmΦ (Alpha Metal Co.)

Ball Material: Sn / Ag / Cu (96.5 / 3 / 0.5) Weight%

Flux (RMA type): EF-9301 (Alpha Metal Co.)

Reflower: KOKI

Reflow Condition: 250 ° C (peak temperature)

※ Assessment Methods :

After the soldering pad flux is placed, place a ball of 0.35mmΦ and measure the size of the solder ball after passing through the reflower. The more solder balls spread, the larger the ball size, the better the weldability.

※ Evaluation standard :

If the size of the initial solder ball particle after reflow is three times or more (that is, 1.05 mm Φ or more), weldability is not abnormal.

<Wire bonding property>

It is a method for inspecting the bonding force between the bonding wire and the bonding portion. K & S 1484 was used as a wire bonding tester, and a bonding condition was given as shown in Table 6 after thermal aging at a temperature of 175 ° C. for 1 hour.

Bonding conditions Item Condition Au wire 1 mil Time (1st / 2nd) 15 m / sec, 25 m / sec Force (1st / 2nd) 70gf / 100gf Power (1st / 2nd) 16mW / 80mW Pretreatment-heat temperature 100 ℃ H / B temperature 200 ℃

The minimum and average force (unit: gf) after the wire bonding until the bond falls, the minimum spec. Is 3 or more and the average force is 5 or more is good.

<Ion Migration>

※ Assessment Methods :

A test coupon of the type specified in IPC 9201 was fabricated to form a porous primary palladium plating layer, an electroless secondary palladium or palladium alloy plating layer, and an electroless gold plating layer. Into the tank was given a high-temperature, high-humidity experimental environment to measure the change of the surface insulation resistance value for 500 hours. The test conditions were given a relative humidity of 85%, a temperature of 85 ° C, a voltage of 50 volts direct current voltage, the water used was a resistance of 10-18 MPa / cm.

※ Evaluation standard :

If ion migration occurs in the plating layer, the surface insulation resistance value is lowered. If the surface insulation resistance value of the test coupon falls below 1 × 10 ⁶ Pa, it is determined that migration has occurred and is considered defective.

<Flexion crack>

※ Assessment Methods :

Bending Radius (R) = 2.0mm

Specimen Width: 1cm

Weight: 100g

Bending Angle: 180 °

RPM = 25

Sample number: 10 pcs.

※ Evaluation standard :

According to the evaluation method described above, the bending crack does not occur on the surface of the specimen after bending 10 times or more.

Characteristic evaluation result division Example 1 Example 2 Example 3 Example 4 Example 5 Example 6 Example 7 Example 8 Example 9 Example 10 Comparative Example 1 Comparative Example 2 Comparative Example 3 Average Plating Layer (㎛) Gold (alloy) 0.05 0.05 0.05 0.15 0.25 0.05 0.1 0.1 Gold-Thallium0.15 0.05 0.08 0.1 0.05 Secondary palladium (alloy) Palladium- Phosphorus 0.2 Palladium-Boron 0.2 Palladium 0.2 Palladium-Phosphor 0.2 Palladium-Phosphor 0.2 Palladium-Phosphor 0.2 Palladium-Phosphorus 0.4 Palladium-Phosphorus 0.9 Palladium-Phosphor 0.2 Palladium-Phosphor 0.2 Palladium-phosphorus 0.2 Primary palladium 0.01 0.01 0.01 0.01 0.01 0.02 0.01 0.01 0.01 0.01 - Nickel (alloy) Nickel-phosphorus 5 Remark 1.2 Solderability Ball shear strength (gf) 390 370 375 440 450 380 500 530 450 395 430 550 490 Ball Spreadability (mmφ) 1.37 1.37 1.39 1.43 1.45 1.41 1.48 1.52 1.47 1.38 1.44 1.35 1.52 Wire bonding Minimum value (g) 9.1 8.9 9.0 9.5 9.5 9.6 10.0 10.5 9.6 9.0 9.2 4.5 3.4 Average value (g) 10.8 10.5 10.7 11.3 11.6 11.7 12.2 12.8 11.6 10.8 11.0 8.6 5.7 Surface Insulation Resistance (Ω) 2.8 x ^{10 8} 3.7 x ^{10 8} 8.2 x ^{10 8} 5.3 x ^{10 8} 6.0 x ^{10 8} 4.1 x ^{10 8} 6.3 x ^{10 8} 7.1 x ^{10 8} 4.9 x ^{10 8} 3.0 x ^{10 8} 6.1x10 ⁸ 9.8 x ^{10 8} 7.5x10 ⁸ Flexure crack phenomenon none none none none none none none none none none none Occur none Number of cracks More than 20 times More than 20 times More than 20 times More than 20 times More than 20 times More than 20 times More than 20 times More than 20 times More than 20 times More than 20 times More than 20 times 1.6times More than 20 times Plating thickness (㎛) gold lowest 0.03 0.03 0.04 0.12 0.21 0.03 0.08 0.08 0.12 0.03 0.03 Best 0.06 0.06 0.06 0.17 0.30 0.07 0.11 0.12 0.18 0.07 0.14 Palladium lowest 0.17 0.16 0.18 0.17 0.18 0.19 0.32 0.80 0.17 0.17 0.07 Best 0.28 0.26 0.26 0.27 0.29 0.25 0.47 0.97 0.28 0.26 0.56

※ The values of ball shear test and wirebonding test are the average of 20 measurements.

Example 11

The following reliability evaluation was performed on the printed circuit boards obtained in Examples 1 and 9.

<Porosity test>

By depositing a high-density printed circuit board plated in nitric acid, it was confirmed whether pores were generated by corrosion of the palladium or palladium alloy plating layer and the gold or gold alloy plating layer.

<Heat resistance test>

After passing three times under the temperature conditions shown in Table 8 by using a reflow, and whether the surface color change by the heat of the palladium and gold plated layer and the separation of the palladium or palladium alloy plating layer and the gold or gold alloy plating layer using an adhesive tape Confirmed.

<Adhesive test>

After passing three times under the temperature conditions shown in Table 8 by using a reflow, the aluminum wire is separated from the palladium or palladium alloy plating layer and the gold or gold alloy plating layer when it is pulled with a constant force after welding using solder to the soldering site with aluminum wire. It was checked whether the solder and the gold or gold alloy plating layer is separated.

Property evaluation test item standard Test content Test results Example 1 Specimen Example 9 Specimen Porosity No oxidation or peeling of gold or gold alloy plating layer Immerse in 12% nitric acid solution for 15 minutes ○ ○ Heat resistance No discoloration or peeling of the gold or gold alloy plating layer after the tape peel test Tape peeling test rate after 3 consecutive reflows Test speed: 0.7m / min Temperature: 220, 240, 250 ℃ ○ ○ Adhesion Copper layer and epoxy interface must be peeled off Pull out aluminum wire after 3 consecutive reflows ○ ○

○: It means that the test result is satisfied.

In view of the above test results, it can be seen that the plating layer according to the embodiment of the present invention satisfies all the required physical properties in relation to the aforementioned items.

As described above, according to the present invention, it is possible to completely solve the variation in the plating thickness caused by the potential difference due to the density of the pattern, which has been pointed out as a technical problem in applying palladium plating having excellent characteristics to the high density printed circuit board. have.

In addition, a rigid printed circuit board on which BGAs, CSPs, and camera modules are mounted to increase circuit density by eliminating the need for a separate lead wire for electroplating, and BGAs, CSPs, and camera modules that simultaneously apply soldering and wire bonding are mounted. It is possible to manufacture a flexible, flexible printed circuit board.

Therefore, the work can be simplified by eliminating an etch back process that requires the removal of unnecessary lead lines by etching.

In addition, wire bonding performance, which was only possible with thick plating, can be replaced by plating consisting of a gold or gold alloy plating layer on a thin palladium or palladium alloy plating layer, thereby greatly reducing cost and improving productivity.

In addition, palladium is a metal suitable for connectors and printed circuit boards due to its high hardness, good ductility, and excellent corrosion resistance, and can satisfy the characteristics required by thin plating thickness. The replacement of the gold plating process completely solves the black pad problem that frequently occurs during surface mount technology of electroless nickel and electroless gold plated printed circuit boards.

In particular, it is possible to prevent fatal bending cracks occurring in the manufacture of flexible and flexible printed circuit boards, which are widely used in portable devices such as mobile phones, which are increasingly complicated and smaller in size.

Above all, the plating layer forming method of the present invention has an advantage that can be applied to all kinds of printed circuit boards.

Although the present invention has been described in detail through specific embodiments, this is for explaining the present invention in detail, and the method of forming a plated layer of the high density printed circuit board and the printed circuit board manufactured therefrom according to the present invention are not limited thereto. It is apparent that modifications and improvements are possible by those skilled in the art within the technical idea of the present invention.

As described above, according to the present invention, a porous palladium plating layer is first formed by substitution plating on a copper layer of a rigid, flexible or rigid printed circuit board, and pure palladium or palladium is formed thereon by electroless reduction plating. After forming an electroless palladium alloy plating layer consisting of phosphorus or palladium-boron, a gold or gold alloy plating layer according to the electroless immersion plating method is formed on the pure palladium or electroless palladium alloy plating layer to form a plating layer of a printed circuit board. .

This solves the non-uniform plating caused by the variation in plating thickness, which is likely to occur in high density printed circuit boards, while protecting pure palladium or palladium alloy plating layers from external corrosive atmosphere, and excellent weldability and wire bonding, resulting in package reliability with semiconductors. To improve.

Since all plating layers are made of electroless reduction or immersion plating, in the case of a printed circuit board with leads such as BGA, CSP, and camera module, the lead wire is unnecessary and the etching process can be omitted, thereby simplifying the process. The circuit density can also be significantly increased, enabling the fabrication of high density BGA, CSP or camera modules.

Even lead-free, flexible, or rigid printed circuit boards, such as MCM and camera modules, can be guaranteed with wire bonding even at thin thicknesses after gold plating after palladium plating, and the process time can be shortened, resulting in significant cost savings.

Although the present invention has been described through the above embodiments, these are merely exemplary and those skilled in the art will understand that various modifications are possible from the present invention. Therefore, the true technical protection scope of the present invention will be cleared by the appended claims.

Claims (19)

In the method of forming a plating layer of a high density printed circuit board, (a) providing a printed circuit board 11 including a wire bonding part for semiconductor mounting and a soldering part for coupling with an external component, and having a predetermined circuit pattern formed thereon; (b) forming a photo solder resist layer 14 on portions of the printed circuit board other than the wire bonding portion and the soldering portion; (c) forming a porous primary palladium plating layer 15 by substitution plating on the wire bonding portion and the soldering portion; (d) forming a secondary palladium or palladium alloy plating layer 16 by electroless reduction plating on the porous primary palladium plating layer 15; And (e) contacting the substituted immersion gold plating solution containing a water-soluble gold compound on the secondary palladium or palladium alloy plating layer 16 to form an electroless gold or gold alloy plating layer 17; A method of forming a triple palladium-palladium-gold plated layer that solves variations in plating thickness of high density printed circuit boards. The method of claim 1, The porous primary palladium plating layer 15, A method of forming a triple palladium-palladium-gold plated layer that solves the plating thickness variation of a high density printed circuit board, characterized by being a pure palladium layer formed by a substitution reaction. The method of claim 1, The secondary electroless palladium alloy plating layer 16, Triple palladium-palladium-gold plated layer that solves the plating thickness variation of a high density printed circuit board comprising 94 to 99.9 wt% of palladium (Pd) and 0.1 to 6 wt% of phosphorus (P) or boron (B) Forming method. The method of claim 1, The gold alloy plating layer 17, Triple-solved plating thickness variation of a high density printed circuit board comprising 99 to 99.99 wt% of gold (Au) and 0.01 to 1.0 wt% of thallium (Tl), selenium (Se), or a combination thereof. Method of forming a palladium-palladium-gold plated layer. The method of claim 1, The porous primary palladium plating layer 15, A method of forming a triple palladium-palladium-gold plated layer that solves the plating thickness variation of a high density printed circuit board, the thickness of which is 0.01 to 1 µm. The method of claim 1, The secondary electroless palladium or palladium alloy plating layer 16, A method of forming a triple palladium-palladium-gold plated layer that solves the plating thickness variation of a high density printed circuit board, the thickness of which is 0.05 to 5.0 µm. The method of claim 1, The gold or gold alloy plating layer 17, A method of forming a triple palladium-palladium-gold plated layer that solves the plating thickness variation of a high-density printed circuit board having a thickness of 0.01 to 0.25 µm. The method of claim 1, In step (c), Method of forming a triple palladium-palladium-gold plating layer to solve the plating thickness variation of the high-density printed circuit board, characterized in that carried out for 30 seconds to 5 minutes at a temperature of 30 to 60 ℃. The method of claim 1, In step (d), Method of forming a triple palladium-palladium-gold plated layer to solve the plating thickness variation of the high-density printed circuit board, characterized in that performed for 3 to 30 minutes at a temperature of 60 to 80 ℃. The method of claim 1, In step (e), Method of forming a triple palladium-palladium-gold plated layer to solve the plating thickness variation of the high-density printed circuit board, characterized in that performed for 1 to 30 minutes at a temperature of 70 to 90 ℃. The method of claim 1, The printed circuit board 11, 3. A method of forming a triple palladium-palladium-gold plated layer that solves the plating thickness variation of a high density printed circuit board, which is a rigid, flexible or rigid printed circuit board. In the printed circuit board comprising a wire bonding portion for semiconductor mounting and a soldering portion for coupling with external components, the circuit pattern is formed, A copper or copper alloy layer forming the wire bonding portion and the soldering portions 12 and 13; A porous primary palladium plating layer 15 formed on the copper layer or copper alloy layer; An electroless secondary palladium or palladium alloy plating layer 16 formed on the porous primary palladium plating layer 15; Triple palladium-palladium-gold plating to solve the plating thickness variation of the high density printed circuit board, characterized in that formed by plating; the electroless gold or gold alloy plating layer 17 formed on the secondary palladium or palladium alloy plating layer 16 Printed circuit board with layers. The method of claim 12, The porous primary palladium plating layer 15, A printed circuit board having a triple palladium-palladium-gold plated layer that solves the plating thickness variation of a high-density printed circuit board, which is a pure palladium layer formed by a substitution reaction. The method of claim 12, The secondary palladium alloy plating layer 16, Triple palladium-palladium-gold plated layer that solves the plating thickness variation of a high density printed circuit board comprising 94 to 99.9 wt% of palladium (Pd) and 0.1 to 6 wt% of phosphorus (P) or boron (B) Printed circuit board with. The method of claim 12, The gold alloy plating layer 17, Triple palladium that resolves the plating thickness variation of high density printed circuit boards comprising 99 to 99.99 wt% of gold (Au) and 0.01 to 1.0 wt% of thallium (Tl), selenium (Se) or a combination thereof. -Printed circuit board with a palladium-gold plated layer. The method of claim 12, The porous primary palladium plating layer 15, A printed circuit board having a triple palladium-palladium-gold plated layer that solves the plating thickness variation of a high-density printed circuit board, wherein the thickness thereof is 0.01 to 1 μm. The method of claim 12, The electroless secondary palladium or palladium alloy plating layer 16, A printed circuit board having a triple palladium-palladium-gold plated layer that solves the plating thickness variation of a high-density printed circuit board, wherein the thickness thereof is 0.05 to 5.0 µm. The method of claim 12, The thickness of the gold or gold alloy plating layer 17, A printed circuit board having a triple palladium-palladium-gold plated layer that solves the plating thickness variation of a high density printed circuit board, characterized in that from 0.01 to 0.25㎛. The method of claim 12, The printed circuit board 11, A printed circuit board having a triple palladium-palladium-gold plated layer which solves the plating thickness variation of a high density printed circuit board, characterized in that the rigid, flexible or rigid printed circuit board.

Images