WO2007086133A1

WO2007086133A1 - Plasma display apparatus

Info

Publication number: WO2007086133A1
Application number: PCT/JP2006/301316
Authority: WO
Inventors: Yasunobu Hashimoto; Akira Otsuka
Original assignee: Fujitsu Hitachi Plasma Display Limited
Priority date: 2006-01-27
Filing date: 2006-01-27
Publication date: 2007-08-02
Also published as: JPWO2007086133A1

Abstract

The characteristic of a filter (12), which subjects display data to a filtering process, is controlled based on index information related to the power consumption of an address driver (17) that drives address electrodes (A1-AM) for selecting, based on the display data, the light emissions or no light emissions of display cells. When the power consumption of the address driver (17) is large, the characteristic of the filter (12) is so controlled as to suppress the high frequency components of the display data, thereby reducing the number of potential changes of the address electrodes (A1-AM). In this way, the power consumption of the address driver (17) can be reduced, while the degradation of the picture quality being suppressed.

Description

Specification

Plasma display device

Technical field

[0001] The present invention relates to a plasma display device.

Background art

A plasma display panel (PDP) has an electrode matrix composed of a scan electrode group for row selection and an address electrode group for column selection. A unit display area is defined at the intersection of the scan electrode and the address electrode, and one display element is arranged in each of the unit display areas. In commercialized surface discharge PDPs, only one of the two electrodes arranged in each row is used for row selection. Therefore, from the viewpoint of selecting one of the display elements, the electrode configuration of the surface discharge PDP can be regarded as a simple matrix similar to other PDPs.

[0003] The contents to be displayed are set by addressing in units of lines, that is, by performing address selection for each line. The address period of one frame in which addressing is performed is divided into the same number of line selection periods as the number of lines on the screen. Each scan electrode is exclusively biased to a predetermined potential in any one row selection period and becomes active, and display data for one row is output in parallel from all the address electrodes. In other words, the potentials of all address electrodes are controlled simultaneously according to the display data.

In such a driving method, electrostatic charge / discharge occurs between adjacent address electrodes and between address electrodes and other electrodes (for example, scan electrodes), and wasteful power is consumed. There was a problem of big! Capacitance exists between the scan electrodes, but the potential change of the scan electrodes has regularity that does not depend on the display data, so power recovery using LC resonance is possible.

[0005] Furthermore, when looking at the number of potential changes at each electrode in addressing, the potential changes only at the time of row selection in the scan electrode, whereas the potential changes many times in the address electrode. In particular, in addressing an image containing a large amount of high frequency components, the potential of the address electrode changes frequently. In such a case, charge the capacitance between the electrodes. A large amount of power is consumed to generate electricity.

[0006] Several countermeasures have been proposed for this problem.

For example, Japanese Patent Laid-Open No. 7-152341 describes masking lower bits of display data when the power consumption of an address driver for driving address electrodes becomes large. Specifically, it describes masking display data of some subframes among a plurality of subframes constituting one frame. This suppresses changes in the potential of the address electrode in the subfield where the display data is masked, thereby reducing power consumption. However, in this method, since the number of subframes for performing gradation expression is substantially reduced, gradation expression ability is reduced. Therefore, the gradation of the displayed image becomes rough and the image quality deteriorates.

[0007] Also, for example, in Japanese Patent Laid-Open No. 11-282398, when the power consumption of the address driver increases, the number of potential changes in the address electrode is referred to with reference to the display data array in the subframe. It describes changing the address scanning order (row selection order) so that the number is reduced. However, this method requires a special circuit for changing the scan order according to the display data of the subframe, and the circuit configuration becomes complicated. It is also difficult to deal with any display data.

Patent Document 1: Japanese Patent Application Laid-Open No. 7-152341

Patent Document 2: Japanese Patent Laid-Open No. 11-282398

Disclosure of the invention

An object of the present invention is to make it possible to reduce power consumption of an address driver while suppressing deterioration in image quality with a simple circuit configuration.

The plasma display device of the present invention is based on a filter that filters display data, an address electrode for selecting light emission or non-light emission of a display cell, and the filtered display data. And an address driver for driving the address electrode, and controlling characteristics of the filter based on index information relating to power consumption of the address driver.

[0011] According to the present invention, when the power consumption of the address driver is large, the filter characteristics are controlled so as to suppress the high-frequency component of the display data, thereby suppressing the image quality degradation. The number of potential changes of the loess electrode can be reduced.

Brief Description of Drawings

FIG. 1 is a diagram showing a configuration example of a plasma display device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a main part of the address driver.

FIG. 3 is a diagram showing an example of a driving sequence of the plasma display device.

FIG. 4 is a diagram showing a configuration example of a plasma display device according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a configuration example of a plasma display device according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a configuration example of a plasma display device according to a fourth embodiment of the present invention.

FIG. 7 is a diagram showing another example of the configuration of the plasma display device according to the fourth embodiment of the present invention.

FIG. 8 is a diagram showing another example of the configuration of the plasma display device according to the fourth embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0014] (First embodiment)

FIG. 1 is a diagram showing a configuration example of a plasma display device according to the first embodiment of the present invention.

[0015] The plasma display apparatus 100 includes an AC drive type (AC type) plasma display panel (PDP) 1 which is a thin color display device, and a drive unit 10 thereof. The plasma display device 100 is used, for example, as a wall-mounted television receiver or a computer system monitor.

[0016] PDP1 has a plurality of display cells arranged in a matrix that forms a screen of M columns and N rows. PDP1 has an electrode pair for generating a sustaining discharge (also referred to as a display discharge) in each display cell. X electrode (first main electrode) XI˜: XN and Y electrode (second main electrode) Pole) It has a three-electrode surface discharge structure in which Y1 to YN and address electrodes (third electrodes) A1 to AM for selecting lighting (light emission) or non-lighting (non-light emission) of the display cell intersect. Hereinafter, each of the X electrodes X1 to XN or their generic name is referred to as an X electrode Xi, each of the Y electrodes Y1 to YN or their generic name is referred to as a Y electrode Yi, and i means a subscript. Similarly, each of the address electrodes A1 to AM or their generic name is called an address electrode Aj, and j means a subscript.

[0017] The X electrodes Xi and the Y electrodes Yi are arranged alternately and in parallel, and the address electrodes Aj are arranged in a direction perpendicular to (intersecting with) these electrodes Xi, Yi. The electrodes Xi and Yi extend in the row direction (horizontal direction) of the screen, and the Y electrode Yi is used as a scan electrode for selecting a display cell for each row during addressing. The address electrode Aj extends in the column direction (vertical direction) of the screen, and is used as an electrode for selecting a display cell for each column during addressing.

[0018] Of the substrate surface, a range where the X electrode Xi and Y electrode Yi intersect the address electrode Aj is a display area (that is, a screen), and the intersection of the Y electrode Yi and address electrode Aj and adjacent to each other. Each display cell is formed by the X electrode Xi. This display cell corresponds to a pixel, and PDP1 can display a two-dimensional image.

[0019] The drive unit 10 is for selectively lighting a large number of display cells constituting a screen of M columns and N rows, and includes a controller 11, a low-pass filter 12, a data processing circuit 13, and a power calculation circuit. 14, X driver 15, Y driver 16, and address driver 17. The drive unit 10 includes frame data (display data) in units of pixels indicating the luminance level (gradation level) of each color R (red), G (green), and B (blue) of an external device such as a TV tuner or a computer. D) Df is input together with various sync signals.

The controller 11 controls the low-pass filter 12, the X driver 15, the Y driver 16, and the address driver 17 based on external input signals (frame data Df and various synchronization signals).

[0021] The low-pass filter 12 is a filter capable of suppressing high-frequency components of input data, and performs filtering processing on frame data Df input from the outside. The filter characteristic of the low-pass filter 12 is controlled by the coefficient designation data Di from the controller 11. For example, The cutoff frequency of the low-pass filter 12 is controlled according to the number designation data Di.

The data processing circuit 13 processes the frame data filtered by the low-pass filter 12 and outputs it to the power calculation circuit 14 and the address driver 17. Specifically, the data processing circuit 13 stores the frame data Df filtered by the low-pass filter 12 in the frame memory 13A and then converts it into subframe data Dsf for gradation display. Stored in the subframe memory 13B. In addition, the data processing circuit 13 serially transfers the subframe data Dsf stored in the subframe memory 13B to the address driver 17 and supplies it to the power calculation circuit 14. Here, in the subframe data Dsf obtained by converting the frame data Df, the value of each bit indicates the necessity of lighting the display cell in the subframe, strictly speaking, the necessity of address discharge.

The power calculation circuit 14 calculates the power consumption value of the address driver 17 based on the subframe data Dsf supplied from the data processing circuit 13. An arithmetic expression for calculating the power consumption value is registered in the power arithmetic circuit 14 in advance, and the power consumption value of the address driver 17 is calculated by the arithmetic expression. Further, the power calculation circuit 14 outputs data Dr indicating the power consumption value obtained as a calculation result to the controller 11. Based on this data Dr, the controller 11 determines the coefficient of the low-pass filter 12.

[0024] The X driver 15 drives the X electrode XI to control its potential. The X driver 15 is a circuit card that repeatedly discharges, and supplies a predetermined voltage to the X electrode XI. The Y driver 16 drives the Y electrode Yi to control its potential. The Y driver 16 includes a circuit that performs line sequential scanning and a circuit that repeats discharge, and supplies a predetermined voltage to the Y electrode Yi.

The address driver 17 drives the address electrode Aj and controls its potential. The address driver 17 includes a circuit that selects a column to be displayed, and supplies a predetermined voltage to the address electrode Aj. The address driver 17 includes one push-pull switching circuit 17 1 shown in FIG. 2 for each address electrode Aj. The address driver 17 can independently control the potential of each address electrode Aj in accordance with the subframe data Dsf.

For example, when the switching element Q1 of the switching circuit 171 is turned on, the address electrode Aj is biased to a predetermined power supply potential (Va). For example, when the switching element Q2 of the switching circuit 171 is turned on, the address electrode Aj becomes the ground potential. The plasma display device 100 shown in FIG. 1 is driven and controlled according to a drive sequence (described later) shown in FIG. 3, and is displayed with a display image power PDP1 based on frame data Df input from an external device force. The In the operation, the plasma display device 100 performs filtering on the input frame data Df and appropriately suppresses the high-frequency components based on the amount of power consumed by the address driver 17. . From this, power consumption is reduced by charging / discharging the capacitance between the address electrodes Aj in addressing and between the address electrodes Aj and the main electrodes Xi, Yi.

[0028] In the plasma display device 100 of the present embodiment, as an index of power consumed by the address driver 17, it is calculated from subframe data Ds; f obtained by converting input frame data Df. The power consumption value of the address driver 17 is used. Therefore, the suppression amount of the high frequency component of the frame data Df can be changed according to the subframe data Dsf.

Specifically, the power calculation circuit 14 calculates the power consumption value of the address driver 17 based on the subframe data Dsf, and outputs the calculated power consumption value to the controller 11. The controller 11 determines the coefficient of the low-pass filter 12 according to the power consumption value, and outputs the coefficient designation data Di to the low-pass filter 12 to control the filter characteristics. The determined filter coefficient is applied from the frame data Df of the next frame.

[0030] Next, the configuration of the low-pass filter 12 will be described. The low-pass filter 12 may perform filtering in the vertical direction (direction in which the address electrode Aj extends) on the screen of M columns and N rows in the PDP 1, or in the horizontal direction (direction in which the electrodes Xi and Yi extend). A filtering process may be applied. It is also possible to perform filtering in both the vertical and horizontal directions.

[0031] The case of performing filtering in the vertical direction on the screen of M columns and N rows in PDP 1 will be described. The image data of the vertical line (j column) corresponding to the address electrode Aj is L j (y). Note that y is the vertical coordinate of the pixel and is expressed in units of the vertical pixel pitch. Hereinafter, the length is expressed in units of pixel pitch.

[0032] If the image data after filtering by the low-pass filter 12 is Lj (y), the low-pass filter 12

f

Filter 12 is represented by equation (1). [0033] [Equation 1] / = ∑ (ァ-)-∑ ^b i ^L jf (y ~ ^l )…)

For example, when a second-order Butterworth filter is configured as the low-pass filter 12, Q = R = 2 and the cutoff frequency is ω

Assuming 0 Z (2 π), each coefficient is as shown in Equation (2).

[0035] [Equation 2] 0-«0 / b ₀

[0036] According to the power consumption value of the address driver 17 calculated by the power calculation circuit 14, the value of ω

By controlling 0, the filter characteristic of the low-pass filter 12 is controlled. Control of the value of ω

0 is performed as follows, for example.

[0037] When the power consumption value of the address driver 17 is sufficiently small, there is no need to limit the frequency band of the low-pass filter 12, and therefore the controller 11 uses Nyquist as the value of ω.

0

Set to π, which gives a limit, or higher. This ω

A value of 0 is used as the preset upper limit value ω. Also, let the target value of the power consumption of the address driver 17 be Ρ.

Omax max

[0038] The controller 11 compares the power consumption value of the address driver 17 calculated by the power calculation circuit 14 with the target value P, and determines that the power consumption value of the address driver 17 is equal to or greater than the target value P and is max max. If this happens, decrease the value of ω. On the other hand, the power consumption value of the address driver 17 is

0

If it is determined that the target value is less than Ρ, increase the value of ω. However, controller 11 max 0

Does not set the value of ω to be greater than or equal to ω. [0039] If the power consumption value of the address driver 17 exceeds a predetermined value in this way,

0

By sequentially controlling the controller 11 so that the cut-off frequency of the one-pass filter 12 is lowered, it is possible to suppress the high-frequency component of the image data and to keep the power consumption of the address driver 17 below the target value. .

The same applies to the case where the filter processing is performed in the horizontal direction on the screen of the row and row in PDP 1. Let L i (x) be the image data of the horizontal line (i column) corresponding to the electrodes Xi and Yi. X is the horizontal coordinate of the pixel and is expressed in units of vertical pixel pitch. Hereinafter, the length is expressed in units of pixel pitch.

If the image data after filtering by the low-pass filter 12 is Li (X),

f

Filter 12 is expressed by equation (3).

[0041] [Equation 3]

Q R

Lif \ x) = 2 ^a k ^Li , ^x _) —∑ ^h i ^Li f \ ^x ~ ^l )… (3)

(t = 0 / = 1

[0042] Other control (such as the value of ω) according to the power consumption value of the address driver 17 is controlled in the vertical direction.

0

Since this is the same as when the filter process is performed, the description thereof is omitted. Here, since R, G, and B display cells are arranged in the horizontal direction, it is a matter of course to apply filter processing to each display cell corresponding to the same color!

Next, a method for calculating the power consumption value of the address driver 17 by the power calculation circuit 14 will be described.

[0044] The direction in which the address electrode Aj extends is the column direction, the direction orthogonal to the direction in which the address electrode Aj extends is the row direction, and the subframe data Dsf related to the display cell in the i-th row and j-th column is d (i, j) Let [d (i, j) = {0, 1}]. The power consumed by the address driver 17 is charging power for the interelectrode capacitance and power due to gas discharge at the time of addressing. The interelectrode capacitance is divided into the interelectrode capacitance between the address electrode Aj and the interelectrode capacitance between the address electrode Aj and the electrodes Xi and Yi.

[0045] The charging power to the interelectrode capacitance between the address electrodes Aj can be expressed by the difference _u (i, j) between the display data of adjacent display cells, and is defined as in equation (4). [0046] [Equation 4]

"(/, D (i, j + \)-d (i, j) [, z) = {—ι, ο, ι}] (4)

[0047] As the subframe data changes in the row order, the potential of the address electrode Aj changes, and when the charging energy between the address electrodes Aj increases, power is supplied from the address driver 17. When the subframe data in the i-th row changes to the subframe data in the (i + 1) -th row, the charging power to the interelectrode capacitance between one address electrode Aj is expressed as f (u (i, j), u ( i + lm

, j)), the following formula (5) is obtained.

[0048] [Equation 5]

/ „, (" '") = O (u = ·! _ 1,0,1

(", O) = 0 (M =-1,0,1

(0, ") = Pi (" = {-1,1}) (5)

(_ 1,1) = P

(1, -1) = P

Here, p and p are determined by the interelectrode capacitance between the address electrodes Ai and the address pulse waveform.

1 2

Determined.

[0050] Another element of the interelectrode capacitance is the counterelectrode capacitance between the address electrode Aj and the electrodes Xi and Yi as described above. The power is supplied from the address driver 17 when the subframe data changes from “0” to “1”. Therefore, when the subframe data in the i-th row changes to the subframe data in the (i + 1) -th row, the charging power to the counter electrode capacitance associated with one address electrode Aj is expressed as f (d (i, j), d (i + l, j))

P

I will become.

[0051] [Equation 6] (0,1) = Ps

(,) = 0 ((d,) ≠ (0,1)) (6)

In the above, p is determined by the capacitance between the counter electrodes and the address pulse waveform. In addition, the power supplied by the address driver 17 includes power due to gas discharge at the time of addressing, so-called address discharge power. This address discharge power is supplied when the subframe data is “1”. The address discharge power per display cell is f (d (i, j)) d

Then, it becomes like Formula (7).

[0054] [Equation 7]

f _d (d) = P, d ...) [0055] The charging power f to the above-mentioned inter-address electrode capacitance f and the charging power to the counter-electrode capacitance fmp

And the sum of the address discharge power f is the power supplied by the address driver 17, and d

On the other hand, the power supplied by the address driver 17, that is, the power consumption P is as shown in Equation (8).

A

The

[0056] [Equation 8]

PA = ∑∑ \ f _m j), u (i + 1, f _p [d {i, j), d (i + 1, f _d (d (i,;))}… (8)

, ■ = 0 Z = 0

Note that, regarding Expression (8), the screen has a size of M columns and N rows when viewed in units of display cells, and the interelectrode capacitance with a dummy address electrode outside the screen is also taken into consideration. It also takes into account the change from the state before the address period to the state of the first row and the change to the state after the state force address period of the Nth row. Therefore, the definition of data d (i, j) is expanded and values are set as shown in Equation (9).

[0058] [Equation 9] d (0, j) = d (N + \, j) = d (i, 0) = d (i, M + \) = 0-(9)

[0059] Since the power consumption value of the address driver 17 in one subframe can be calculated from the above equation (8), the power consumption per frame can be calculated by calculating the power in all the subframes in one frame. it can. This power calculation circuit 14 calculates one frame. The power consumption value may be used as it is for the control of the low-pass filter 12, or the average value of a plurality of frames may be used for the control.

FIG. 3 is a diagram showing an example of a driving sequence of the plasma display device in the present embodiment.

The image is composed of a plurality of time-series frames f (subscripts indicate display order) such as frames fk 1, fk, fk + 1, etc. shown in FIG. In the image display, in order to perform gradation reproduction by binary lighting control for each pixel unit, each frame f is divided into, for example, eight subframes sfl, sf2, sf3, sf4, sf5, sf6, sf7, sf Divide into 8.

[0061] In the subframes sf1 to sf8, the relative ratio of luminance is, for example, approximately 1: 2: 4: 8: 16: 32: 64:

The number of sustaining discharges is set for each of the subframes sfl to sf8. In the example shown in FIG. 3, the subframe sfl has the highest luminance weight in the order of the subframes sf2, sf3,... With the lowest luminance weight, and the subframe sf8 has the highest luminance weight. The brightness can be set in 256 steps for each color of R, G, and B by the combination of lighting Z not lighting in each subframe unit, and the number of colors that can be displayed is 256 to the third power.

[0062] The subframe period Tsf allocated to each of the subframes sfl to sf8 includes a reset period TR, an address period TA, and a sustain (sustain discharge) period TS. In the reset period TR, the charge distribution of the display cell is initialized. In the address period TA, a charge distribution corresponding to the display content (subframe data) is formed by row selection. In the sustain period TS, the lighting state is maintained in order to ensure the luminance according to the gradation level.

[0063] Specifically, in the reset period TR, first, positive obtuse waves Prl are simultaneously applied to the Y electrode Yi to form wall charges. Next, negative wall wave Pr2 is simultaneously applied to Y electrode Yi to adjust the wall charge amount of the display cell.

[0064] In the address period TA, wall charges necessary to maintain the lighting state are formed only in the display cells to be lit in the sustain period TS. With all X electrodes XI and all Y electrodes Yi biased to a predetermined potential, row selection is performed in a predetermined order, and a negative scan pulse Py is applied to one Y electrode Yi corresponding to the selected row. Apply. Corresponding to the scan pulse Py, the address pulse Pa is applied to the address electrode Aj corresponding to the display cell to be lit. As a result, address discharge occurs in the display cell to be lit, and the sustain is A desired wall charge necessary for maintaining the lighting state in the period TS is formed.

[0065] In the sustain period TS, all the address electrodes Aj are biased to a predetermined positive potential in order to prevent unnecessary discharge, and the sustain pulse Ps is alternately applied to the X electrode XI and the Y electrode Yi. Apply. The sustain pulse Ps is a pulse having a voltage lower than the discharge start voltage. Each time the sustain pulse Ps is applied, a surface discharge occurs in the display cell in which wall charges are formed in the address period TA, that is, the selected display cell, and the display cell emits light.

[0066] Although the case of performing addressing in the writing format has been described as an example, in the case of performing addressing in the erasing address format, the entire surface is uniformly charged in the reset period TR, and non-addressing is performed in the address period TA. It suffices to generate an address discharge only in the display cells to be lit to erase unnecessary wall charges and leave the wall charges in the display cells to be lit.

In addition, the drive waveform shown in FIG. 3 is an example, and various changes can be made without being limited thereto.

As described above, according to the first embodiment, when the power consumption value of the address driver 17 calculated by the power calculation circuit 14 is equal to or higher than the target value, the low pass is set so as to lower the cutoff frequency. The filter characteristics of the filter 12 are controlled to suppress high frequency components of the input frame data Df (display image data). On the other hand, when the power consumption value of the address driver 17 is less than the target value, the filter characteristics of the low-pass filter 12 are controlled so that the cutoff frequency is increased within the predetermined range without exceeding the predetermined range. That is, the amount of suppression of the high frequency component of the input frame data Df is controlled according to the power consumption value of the address driver 17.

Thus, if the power consumption value of the address driver 17 is equal to or higher than the target value, the high frequency component of the input frame data Df can be suppressed and the number of potential changes at the address electrode Aj can be reduced. Therefore, with a simple circuit configuration without complicating the circuit configuration, the power consumption of the address driver 17 can be suppressed to a target value or less while suppressing deterioration of the image quality of the displayed image and reducing the power consumption. Can do.

[0069] (Second Embodiment) Next, a second embodiment will be described.

FIG. 4 is a diagram showing a configuration example of the plasma display device according to the second embodiment of the present invention. In FIG. 4, blocks having the same functions as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted. The driving sequence of the plasma display device according to the second embodiment is the same as that of the first embodiment.

The plasma display device 100 according to the first embodiment described above obtains the power consumption value of the address driver 17 by calculation based on the subframe data Dsf, and the low-pass filter 12 according to the power consumption value. Control properties. The plasma display apparatus 200 according to the second embodiment shown in FIG. 4 measures the current supplied to the address driver 17 and controls the characteristics of the low-pass filter 12 according to the measurement result.

Since the power value is obtained by multiplying the current value by the value of the power supply voltage, the measured current value supplied to the address driver 17 is an index of the power consumed by the address driver 17. In the second embodiment, the power consumption of the address driver 17 is reduced by filtering the frame data Df based on the current value supplied to the address driver 17 and appropriately suppressing high frequency components. Let

[0072] The plasma display device 200 according to the second embodiment includes an AC type PDP 1 and a drive unit 20 as shown in FIG.

The drive unit 20 also receives frame data Df in units of pixels indicating the luminance level (gradation level) of each color of R, G, and B, as well as various synchronization signals. This is to selectively light up a number of display cells that make up the N-line screen. The drive unit 20 includes a controller 21, a low-pass filter 12, a data processing circuit 13, an X driver 15, a Y driver 16, an address driver 17, and a current measurement circuit 22.

The controller 21 controls the low-pass filter 12, the X driver 15, the Y driver 16, and the address driver 17 based on external input signals (frame data Df and various synchronization signals).

In addition, the controller 21 receives the measurement result of the current value supplied to the address driver 17 from the current measurement circuit 22, and determines the coefficient of the low-pass filter 12 based on the measurement result. Output coefficient specification data Di. For example, if the current value supplied to the address driver 17 is greater than or equal to a predetermined value, the controller 21 determines the value of ω (cuts the low-pass filter 12).

0

If the measured current value is less than the specified value

Increase the value of ω within the range not exceeding Omax.

0

The current measurement circuit 22 measures the current value actually supplied to the address driver 17 and outputs the measurement result to the controller 21.

According to the second embodiment, the low-pass filter 12 filter appropriately suppresses the high-frequency component of the frame data Df according to the current value supplied to the address driver 17 measured by the current measurement circuit 22. Characteristics are controlled. As a result, the power consumption of the address driver 17 can be suppressed to a target value or less while suppressing image quality degradation with a simple circuit configuration, and the power consumption can be reduced.

[0077] (Third embodiment)

Next, a third embodiment will be described.

FIG. 5 is a diagram showing a configuration example of a plasma display device according to the third embodiment of the present invention. In FIG. 5, blocks having the same functions as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted. The driving sequence of the plasma display device according to the third embodiment is the same as that of the first embodiment.

The plasma display device 300 according to the third embodiment shown in FIG. 5 measures the temperature of the address driver 17 and controls the characteristics of the low-pass filter 12 according to the measurement result. Here, since the driver temperature increases as the power consumption increases, the measured temperature of the address driver 17 is an index of the power consumed by the address driver 17. In the third embodiment, the power consumption of the address driver 17 is reduced by applying a filtering process to the frame data Df and appropriately suppressing high frequency components based on the temperature of the address driver 17.

The plasma display device 300 according to the third embodiment includes an AC type PDP 1 and its drive unit 30 as shown in FIG.

The drive unit 30 also has the power of external devices such as TV tuners and computers. Frame data Df for each pixel indicating the luminance level (gradation level) of each color of R, G, and B is used for various synchronization signals. The number of display cells that are input together with the number and constitute the screen of M columns and N rows are selectively lit. The drive unit 30 includes a controller 31, a low-pass filter 12, a data processing circuit 13, an X driver 15, a Y driver 16, an address driver 17, and a temperature measurement circuit 32.

The controller 31 controls the low-pass filter 12, the X driver 15, the Y driver 16, and the address driver 17 based on external input signals (frame data Df and various synchronization signals).

Further, the controller 31 is supplied with the temperature measurement result of the address driver 17 from the temperature measurement circuit 22, determines the coefficient of the low-pass filter 12 based on the measurement result, and outputs the coefficient designation data Di. For example, the controller 31 decreases the value of ω (the cutoff frequency of the low-pass filter 12) if the temperature of the address driver 17 is equal to or higher than a predetermined temperature.

0

If the measured temperature is lower than the specified temperature, increase the value of ω within a range that does not exceed ω.

Omax 0

The temperature measurement circuit 32 measures the temperature of the address driver 17 and outputs the measurement result to the controller 31. In the plasma display device, since a circuit for enabling the driver temperature to be monitored is generally provided, it may be used as the temperature measurement circuit 32 in the present embodiment.

According to the third embodiment, the filter characteristics of the low-pass filter 12 are controlled so as to appropriately suppress the high-frequency component of the frame data Df according to the temperature of the address driver 17 measured by the temperature measurement circuit 32. Is done. As a result, the power consumption of the address driver 17 can be reduced while suppressing image quality degradation with a simple circuit configuration. Further, since the control is performed based on the temperature of the address driver 17, it is possible to reliably prevent the address driver 17 from being damaged by heat generation, and the address driver 17 can be protected.

[0084] (Fourth embodiment)

Next, a fourth embodiment will be described.

In the plasma display device according to the first to third embodiments described above, the frame data Df inputted from the outside is filtered by the low-pass filter 12. The sub-frame data Dsf is filtered by the low-pass filter. At any rate good. The plasma display device according to the fourth embodiment described below can perform a filtering process for suppressing high frequency components on the subframe data Dsf obtained by processing in the data processing circuit 13. It is a thing.

FIG. 6 is a diagram showing a configuration example of a plasma display device according to the fourth embodiment of the present invention. In FIG. 6, blocks having the same functions as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted. The driving sequence of the plasma display device according to the fourth embodiment is the same as that of the first embodiment.

As shown in FIG. 6, the plasma display device 400 according to the fourth embodiment includes an AC type PDP 1 and a drive unit 40 thereof.

In the drive unit 40, external device power such as a TV tuner or a computer also receives frame data Df in pixel units indicating the luminance level (gradation level) of each color of R, G, and B together with various synchronization signals, and M columns. This is to selectively light up a number of display cells that make up the N-line screen. The drive unit 40 includes a controller 41, a low-pass filter 42, a power calculation circuit 43, a data processing circuit 13, an X driver 15, a Y driver 16, and an address driver 17.

The controller 41 controls the low-pass filter 42, the X driver 15, the Y driver 16, and the address driver 17 based on external input signals (frame data Df and various synchronization signals). Further, the controller 41 is supplied with the power consumption value of the address driver 17 obtained by the power calculation circuit 43, and determines the coefficient of the low-pass filter 42 based on the power consumption value! Is output.

The low-pass filter 42 is a filter that can suppress high-frequency components of input data, and performs filtering processing on the subframe data Dsf output from the data processing circuit 13. The low pass filter 42 is provided independently corresponding to each of a plurality of subframes constituting one frame. The filter characteristics of the low-pass filter 42 are controlled by the coefficient specifying data Di from the controller 41. For example, the cutoff frequency of the low-pass filter 42 is controlled according to the coefficient specifying data Di.

The power calculation circuit 43 is configured in the same manner as the power calculation circuit 14 in the first embodiment, and is based on the subframe data Dsf filtered by the low-pass filter 42! /, Calculate the power consumption of the address driver 17. The power calculation circuit 43 outputs data Dr indicating the power consumption value obtained as a calculation result to the controller 41.

In the plasma display device 400 according to the fourth embodiment shown in FIG. 6, Lj and Lj in the equation (1) shown in the first embodiment and Li in the equation (3)

f and Li respectively

f

It may be read as frame data. However, when input to the address driver 17, the subframe data needs to be quantized to "0" or "1". Therefore, after being filtered by the low-pass filter 42, the data L input to the address driver 17 is expressed by the equation

d

Quantized according to (10).

[0091] [Equation 10]

L _d = 0 (L _f <0.5)

L _d = l (L _f ≥ 0.5)

[0092] In the above equation (10), L is a data value after filtering by the low-pass filter 42.

f

is there.

Note that the other points of the plasma display apparatus 400 according to the fourth embodiment are the same as those of the plasma display apparatus 100 according to the first embodiment described above, and thus the description thereof is omitted.

Further, not only the power consumption value of the address driver 17 calculated based on the subframe data Dsf but also the current supplied to the address driver 17 and the same as in the second and third embodiments described above. It is also possible to actually measure the temperature of the address driver 17 and control the characteristics of the mouth-pass filter 42 according to the measurement result!

FIG. 7 is a diagram showing another configuration example of the plasma display device according to the fourth embodiment of the present invention. In FIG. 7, blocks having the same functions as those shown in FIGS. 1 and 6 are denoted by the same reference numerals, and redundant description is omitted. The plasma display device 500 shown in FIG. 7 measures the current supplied to the address driver 17 and controls the characteristic of the low-pass filter 42 that filters the subframe data Dsf according to the measurement result.

[0095] The plasma display device 500 includes an AC type PDP 1 and a drive unit 50 thereof. It is.

In the drive unit 50, external device power such as a TV tuner or a computer also receives frame data Df in pixel units indicating the luminance level (gradation level) of each color of R, G, and B together with various synchronization signals. This is to selectively light up a number of display cells that make up the N-line screen. The drive unit 50 includes a controller 51, a low-pass filter 42, a data processing circuit 13, an X driver 15, a Y driver 16, an address driver 17, and a current measurement circuit 52.

The controller 51 controls the low-pass filter 42, the X driver 15, the Y driver 16, and the address driver 17 based on external input signals (frame data Df and various synchronization signals). Further, the controller 51 is supplied with the measurement result of the current value supplied to the address driver 17 from the current measurement circuit 52, and based on the measurement result, determines the coefficient of the low-pass filter 42 to obtain the coefficient designation data Di. Output.

The current measurement circuit 52 measures the current value actually supplied to the address driver 17 and outputs the measurement result to the controller 51.

FIG. 8 is a diagram showing another configuration example of the plasma display device according to the fourth embodiment of the present invention. In FIG. 8, blocks having the same functions as those shown in FIGS. 1 and 6 are denoted by the same reference numerals, and redundant description is omitted. The plasma display device 600 shown in FIG. 8 measures the temperature of the address driver 17 and controls the characteristics of the low-pass filter 42 that filters the subframe data Dsf according to the measurement result.

[0098] Plasma display apparatus 600 includes AC type PDP 1 and drive unit 60 thereof.

In the drive unit 60, the external device power of the TV tuner, the computer, etc. is also inputted with frame data Df in pixel units indicating the luminance level (gradation level) of each color of R, G, B together with various synchronization signals, and M columns This is to selectively light up a number of display cells that make up the N-line screen. The drive unit 60 includes a controller 61, a low-pass filter 42, a data processing circuit 13, an X driver 15, a Y driver 16, an address driver 17, and a temperature measurement circuit 62. The controller 61 controls the low-pass filter 42, the X driver 15, the Y driver 16, and the address driver 17 based on external input signals (frame data Df and various synchronization signals). Further, the controller 61 is supplied with the measurement result of the current value supplied to the address driver 17 from the current measurement circuit 62, and determines the coefficient of the low-pass filter 42 based on the measurement result to obtain the coefficient designation data Di. Output.

The temperature measurement circuit 62 measures the temperature of the address driver 17 and outputs the measurement result to the controller 61.

[0100] As described above, according to the fourth embodiment, as in the first to third embodiments described above, the power consumption of the address driver 17 can be reduced while suppressing image quality degradation with a simple circuit configuration. Can do. Further, the sub-frame data Dsf, which is the control data itself of the address driver 17, can be controlled for each sub-frame by performing a filtering process by the low-pass filter 42 as a unit. For example, the upper subframe (or subframe group) data with a higher luminance weight is not filtered, and the lower luminance frame! Or lower subframe (or subframe group) data is not filtered. By performing the filtering process using only the low-pass filter 42, the power consumption of the address driver 17 can be reduced while suppressing an increase in gradation error.

[0101] In the plasma display device according to the fourth embodiment described above, a low pass filter 42 is provided corresponding to each subframe, but one single pass filter 42 is provided. The coefficient may be changed and controlled for each subframe. In addition, a plurality of low-pass filters 42 may be provided in addition to one low-pass filter 42, and the coefficients may be appropriately controlled to be used in V and several subframes.

[0102] In the first to fourth embodiments described above, as an index of the power consumed by the address driver 17, the calculated power consumption value of the address driver 17 and the measured address driver 17 are used. Only one of the supplied current value and the measured temperature of the address driver 17 is used. However, the present invention is not limited to this. Anyway!

[0103] When using multiple indicators together, set a target value for each indicator, and when at least one indicator exceeds the target value, the cutoff frequency of the low-pass filter If the wave number is reduced and all indicators are below the target value, control can be performed to increase the cutoff frequency of the low-pass filter.

[0104] Further, as in the first and fourth embodiments described above, when the power consumed by the address driver 17 is obtained by calculation, the screen is divided into a plurality of areas and each area is divided. Alternatively, the power consumption value of the address driver 17 may be calculated, and a filtering process using a low-pass filter may be performed so as to suppress high-frequency components only in a region where the power consumption is large. Specifically, a target value of power consumption of the address driver 17 may be set for each divided area, and filtering may be performed according to a comparison result between the calculated power consumption value and the target value. Such control is suitable, for example, for an image in which a moving image is displayed on a part of the screen and a still image is displayed on the other part.

[0105] In addition, each of the above-described embodiments is merely an example of the implementation of the present invention, and the technical scope of the present invention should not be construed in a limited manner. Is. That is, the present invention can be implemented in various forms without departing from the technical idea or the main characteristic power thereof.

Industrial applicability

[0106] According to the present invention, the characteristics of the filter that filters the display data are controlled based on the index information related to the power consumption of the address driver, and the power consumption of the address driver is large. The filter characteristics are controlled so as to suppress the high-frequency component of the display data. As a result, it is possible to reduce the number of potential changes in the address electrode in accordance with display data with a simple circuit configuration, thereby suppressing image quality deterioration and reducing the power consumption of the address driver.

Claims

The scope of the claims

[1] A filter that filters the display data,

An address electrode for selecting light emission or non-light emission of the display cell;

An address driver for driving the address electrode based on the filtered display data;

A plasma display device, wherein the characteristics of the filter are controlled based on index information relating to power consumption of the address driver.

[2] When the filter determines that the power consumption of the address driver exceeds a predetermined value based on the index information, the filter lowers the cut-off frequency so as to suppress a high-frequency component of the display data, 2. The plasma display device according to claim 1, wherein when it is determined that the value is less than the value, the cutoff frequency is controlled to be increased.

[3] The plasma display device according to [1], wherein the filtering process is performed in units of display data of a plurality of subframes obtained by converting display data of one frame.

[4] The plurality of subframes are classified into a high luminance weight! ヽ subframe group and a low luminance weight! ヽ subframe group, and the display data of subframes belonging to the subframe group having the low luminance weight 4. The plasma display device according to claim 3, wherein the filtering process is performed only on the screen.

5. The plasma display device according to claim 1, wherein the index information is a power consumption value of the address driver calculated by using the display data.

[6] The screen on which the display image based on the display data is displayed is divided into a plurality of areas, the power value is calculated for each area, and the filter is applied to the display data for each area based on the power value. 6. The plasma display device according to claim 5, wherein treatment is performed.

7. The plasma display device according to claim 1, wherein the index information is information on a current supplied to the address driver measured by a current measuring circuit.

8. The plasma display device according to claim 1, wherein the index information is temperature information of the address driver measured by a temperature measurement circuit.

[9] Based on a plurality of index information relating to power consumption of the address driver, the filter 2. The plasma display device according to claim 1, wherein the characteristics of the plasma display device are controlled.

[10] The plurality of index information includes a power consumption value of the address driver calculated by using the display data, information on a current supplied to the address driver measured by a current measurement circuit, and a temperature. 10. The plasma display device according to claim 9, wherein at least two pieces of information on the temperature of the address driver measured by a measurement circuit are included.

11. The plasma display device according to claim 1, wherein the filter processing is performed on the display data in a direction in which the address electrodes extend on a screen on which a display image based on display data is displayed.

[12] The filter processing is performed on the display data of the display cells of the same color in a direction orthogonal to a direction in which the address electrodes extend on a screen on which a display image based on display data is displayed. The plasma display device according to claim 1.

[13] The display of display cells of the same color in both the first direction in which the address electrodes extend on the screen on which a display image based on display data is displayed and the second direction orthogonal to the first direction The plasma display device according to claim 1, wherein the filtering process is performed on the data.

[14] address electrodes for selecting light emission or non-light emission of the display cell;

Based on the filtered display data, an address driver that drives the address electrodes;

A power calculation circuit for calculating a power consumption value of the address driver using the filtered display data;

A plasma display device comprising: a filter that controls a filter coefficient based on a power consumption value calculated by the power calculation circuit and performs the filtering process on display data.

[15] An address electrode for selecting light emission or non-light emission of the display cell;

A current measuring circuit for measuring a current supplied to the address driver; A plasma display device, comprising: a filter that controls a filter coefficient based on a measurement result of the current measurement circuit and performs the filter process on display data.