WO2007080926A1 - Inter-substrate bonding chip part, its manufacturing method, and wiring substrate connection method using the same - Google Patents

Inter-substrate bonding chip part, its manufacturing method, and wiring substrate connection method using the same Download PDF

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Publication number
WO2007080926A1
WO2007080926A1 PCT/JP2007/050247 JP2007050247W WO2007080926A1 WO 2007080926 A1 WO2007080926 A1 WO 2007080926A1 JP 2007050247 W JP2007050247 W JP 2007050247W WO 2007080926 A1 WO2007080926 A1 WO 2007080926A1
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WO
WIPO (PCT)
Prior art keywords
inter
chip component
conductive
board
connection
Prior art date
Application number
PCT/JP2007/050247
Other languages
French (fr)
Japanese (ja)
Inventor
Humikazu Harazono
Motohiko Aono
Yoshiharu Takade
Yoshiyuki Hotta
Masahiko Mikami
Original Assignee
Matsushita Electric Industrial Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Publication of WO2007080926A1 publication Critical patent/WO2007080926A1/en

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Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits
    • H05K3/368Assembling printed circuits with other printed circuits parallel to each other
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/141One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/10378Interposers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0235Laminating followed by cutting or slicing perpendicular to plane of the laminate; Embedding wires in an object and cutting or slicing the object perpendicular to direction of the wires
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3442Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers

Definitions

  • Chip component for board-to-board connection its manufacturing method, and wiring board wiring using the same) Method C
  • the present invention relates to a chip component for inter-plate connection, a method for manufacturing the same, and a method for connecting a wiring board using the same, and particularly relates to a chip component for connection used for collective connection between wiring boards.
  • Mounted circuit modules are widely used in which semiconductor elements, resistors, capacitors, and the like are mounted on a wiring board made of resin or ceramic.
  • the structure is generally composed of a wiring layer formed on the substrate and an insulating layer that insulates it, and the wiring layer on the substrate is a hole-like conductor contact layer called a via hole provided in the substrate. They are connected to each other by (conduction vias).
  • a high-density circuit board such as a surface wiring printed circuit (SLC) board has come to be used as this circuit board.
  • the SLC is composed of a substrate and its surface wiring layer.
  • the surface layer wiring layer is a laminate of a wiring layer and an insulating layer, and the wiring layers are connected to each other through conductive vias.
  • the connection between the wirings on both sides of the board is made by conductive vias (through holes) in the board.
  • Build-up of mounting circuit module using such SLC board The lower part of the board is electrically connected to the mounting board (mother board, etc.) via the solder balls (ball-dally-array) for carrier connection .
  • a semiconductor chip is electrically connected to the upper part of the buildup substrate via chip connection bumps (solder bumps).
  • the printed circuit board 10 on which the electronic component 20 is mounted is individually connected to the flexible wiring board 40, that is, the connection terminal 43 on the flexible board 42 via the solder ball 130. The method of doing is taken.
  • solder ball 130 is placed at a desired position on the printed circuit board 10 (FIG. 13A) on which the electronic component 20 is mounted. Position and install (Fig. 13 (b)), and attach this to the connection terminal 43 (Fig. 13 (c)) on the flexible board 40. It is formed by wearing and reflowing (Fig. 13 (d)). In this method, it is necessary to individually mount solder balls 130 for connection between connection plates at connection points.
  • Patent Document 1 JP 2001-102749 A
  • connection process in FIG. 13 it is necessary to individually mount the solder balls 130 for connecting the plates to the connection points, which increases the number of parts. It was. Positioning is also an important issue. It takes a lot of time for mounting, and misalignment easily occurs.
  • the present invention has been made in view of the above circumstances, and an object thereof is to enable easy mounting of a circuit module on a printed circuit board without requiring special equipment.
  • Another object is to efficiently facilitate alignment between substrates. Means for solving the problem
  • the present invention is an inter-plate connecting chip component used for connecting substrates to a wiring substrate on which a wiring pattern is formed, wherein the first and second surfaces facing each other form a flat surface.
  • a plurality of conductive regions and an insulating region are arranged on the first and second surfaces, and the conductive region is connected to the second surface from the first surface.
  • the insulating regions are formed so as to form a path.
  • connection between the substrates can be easily realized with chip parts with good workability, and the presence of the insulating region can surely prevent a short circuit between the conductive paths.
  • the present invention provides the above-described chip component for board connection, wherein the conductive region is the first part.
  • One of the first and second surfaces includes one-dimensionally arranged ones.
  • the present invention includes the above-described chip component for board connection, wherein the conductive region is a columnar region arranged toward the second surface with the first surface force. According to this configuration, the conductive path is reliably ensured by the columnar region.
  • the present invention provides the above-described chip component for inter-plate connection, wherein the conductive region is the first part.
  • a conductive pattern disposed on the side surface in contact with the end portions of the first and second surfaces is included.
  • the configuration is simple and the manufacture is easy.
  • the present invention also includes the above-described chip component for connecting plates, including an insulating coating layer disposed between the conductive regions on at least one of the first and second surfaces.
  • the present invention includes the above-described chip component for inter-plate connection, wherein the conductive region forms a recess in the vicinity of at least one of the first and second surfaces.
  • the recess serves as a liquid reservoir that prevents the solder from flowing out, and the solder flow can be more reliably suppressed.
  • the present invention includes the above-described chip component for inter-plate connection, wherein the columnar region includes concave grooves penetrating from the first surface to the second surface on both side surfaces.
  • the concave groove serves to increase the contact area between the connection terminal on the wiring board surface and the solder layer, and serves as a liquid reservoir that prevents the solder layer from flowing out.
  • the insulative area becomes a dam. This suppresses the solder from spreading indefinitely and increases the area of the solder joint, thereby ensuring reliable and strong electrical and physical connection.
  • the present invention is configured by a laminate in which an insulating region made of an insulating substrate and a conductive region made of a conductive substrate are stacked in a direction perpendicular to the first and second surfaces. Including things.
  • the recess serves as a liquid reservoir that prevents the solder from flowing out, and the solder flow can be more reliably suppressed.
  • the present invention includes the above-described chip component for board connection, wherein the insulating substrate is a ceramic substrate. According to this configuration, it is possible to configure a firm and reliable chip component for inter-plate connection.
  • the present invention includes the above-described chip component for inter-plate connection, wherein the insulating substrate is a resin substrate.
  • the present invention includes the above-described chip component for inter-plate connection, wherein the conductive substrate is a metal substrate.
  • the present invention is also a method of manufacturing a chip component for inter-plate connection used for connecting substrates with a wiring substrate on which a wiring pattern is formed, wherein the first and second surfaces facing each other are provided.
  • a plurality of conductive regions are arranged on the first and second surfaces through insulating regions, and the conductive regions are arranged from the first surface to the second surface.
  • the conductive region and the insulating region are arranged so as to form a plurality of conductive paths connected to the.
  • the laminated body is cut perpendicularly to the stacking direction so that the cut surfaces constitute the first and second surfaces, the flat surface can be easily formed and more reliable connection can be achieved. Is possible.
  • the present invention provides the above-described method for manufacturing a chip component for inter-plate connection, wherein, after the step of forming the laminate, prior to the step of cutting, a through hole is formed in the conductive substrate along the cut surface.
  • the step of cutting includes a step of cutting at a position where the through hole is cut.
  • the present invention provides the above-described method for manufacturing a chip component for inter-plate connection, the step of forming a stripe-shaped first conductive pattern on the front surface and the back surface of the insulating substrate; Cutting the insulating substrate into a predetermined width in a direction perpendicular to the conductive pattern to form a plate-like body having a predetermined width; and forming the plate-like body into the first conductive pattern.
  • the same effect can be achieved at low cost by forming the conductive pattern in the form of stripes on the surface of the insulating substrate.
  • the step of forming the first and second conductive patterns includes a screen printing step.
  • the process of forming the first and second conductive patterns is a screen printing process, it is possible to efficiently perform highly accurate pattern formation.
  • the step of forming the second conductive pattern includes a coating step by an ink jet method.
  • the first and second surfaces facing each other form a flat surface, and a plurality of conductive regions are arranged on the first and second surfaces via insulating regions.
  • the inter-plate connection chip component is disposed so that the first surface is in contact with the connection terminal region, and solder-bonded.
  • a second step in which the second surface of the interchip connecting chip component is disposed so as to abut on the second connecting terminal region of the second wiring board and soldered.
  • the first and second steps are in contact with the first and second surfaces of the first and second connection terminal regions.
  • a solder layer is also formed on the outer side of the surface, and a joining region is formed from the first and second surfaces to the side surface connected to the first and second surfaces.
  • a groove is formed on a side surface of the conductive region, and in the first and second steps, the solder flows into the groove. This includes a process for forming a bonding region.
  • the joining region is formed so that the solder flows into the recessed groove, it is possible to increase the connection area, the joining property is improved, and the wall surface of the recessed groove serves as a liquid reservoir. As a result, the bonding becomes stronger and more reliable.
  • the present invention includes the above wiring board connection method, wherein at least one of the first and second wiring boards is a hard board (rigid board).
  • the present invention includes the above wiring board connection method, wherein at least one of the first and second wiring boards is a flexible board.
  • a flexible wiring board since a flexible wiring board has flexibility and it is easy to use space, it is often used for the connection between wiring boards or a glass substrate.
  • the directly connected flexible substrate is less likely to be peeled off, which leads to a reduction in yield and reliability of electronic products.
  • a plurality of inter-plate connection points can be connected together, and the number of parts can be reduced.
  • dedicated mounting equipment for mounting components is not required, and efficient mounting can be realized with a standard equipment configuration.
  • FIG. 1 is a diagram showing a circuit module mounted using the inter-plate connecting chip component according to the first embodiment of the present invention.
  • FIG. 2 is a diagram showing a chip component for inter-plate connection according to Embodiment 1 of the present invention.
  • FIG. 3 is a top view of the circuit module according to the first embodiment of the present invention.
  • FIG. 4 is a view showing an inter-plate connection process using the inter-plate connection chip component according to the first embodiment of the present invention.
  • FIG. 5 is a manufacturing process diagram of a chip component for inter-plate connection according to Embodiment 1 of the present invention.
  • FIG. 6 is a manufacturing process diagram of a chip component for inter-board connection according to Embodiment 1 of the present invention.
  • FIG. 7 is a manufacturing process diagram of a chip component for inter-board connection according to Embodiment 1 of the present invention.
  • FIG. 8 is a diagram showing a chip part for connecting between plates according to the second embodiment of the present invention.
  • FIG. 9 is a view showing a chip part for connecting between plates according to a third embodiment of the present invention.
  • FIG. 10 is a diagram showing a manufacturing process of the interchip connecting chip part according to the third embodiment of the present invention.
  • FIG. 11 is a diagram showing a manufacturing process of the inter-plate connecting chip part according to the third embodiment of the present invention.
  • FIG. 12 A diagram showing a circuit module mounted using a conventional chip component for inter-plate connection.
  • FIG. 13 is a diagram showing a manufacturing process of a conventional circuit module.
  • FIG. 1 is a cross-sectional view showing a circuit module 100 mounted using the inter-plate connecting chip component according to the embodiment of the present invention.
  • FIG. 2 is a chip part for inter-plate connection of the present embodiment
  • FIG. 3 is a top view of the circuit module 100 of FIG.
  • FIG. 4 is a diagram illustrating a circuit module mounting process using the inter-plate connection method using the inter-plate connecting chip component
  • FIGS. 5 to 7 are diagrams illustrating a manufacturing process of the inter-chip connecting chip component.
  • an inter-plate connection chip is formed on a flexible wiring board 40 having wiring patterns 43 and 41 formed on the front and back surfaces of a polyimide resin film material 42.
  • the multilayer wiring board 10 is connected via the component 30 to achieve board-to-board connection.
  • the inter-plate connecting chip component 30 is an inter-plate connecting chip component used to connect the substrates with the wiring substrate on which the wiring pattern is formed, as shown in FIG.
  • the first and second surfaces 30a, 30b are flat surfaces, and a plurality of conductive regions 31 having the same width and insulating regions 32 are arranged on the first and second surfaces.
  • the conductive region 31 is formed separately from the first surface by the insulating region 32 so as to constitute a plurality of conductive paths connected to the second surface.
  • Reference numeral 34 denotes an insulating coating layer.
  • this conductive region constitutes a columnar conductive path, and has concave grooves 33 penetrating from the first surface 30a to the second surface 30b on both side surfaces.
  • the circuit module 100 has six inter-plate connecting chip components 30 arranged on the periphery of the multilayer wiring board 10 of the circuit module. Yes. Further, chip components such as the solid-state imaging device chip 21, the capacitor 22, and the resistor 23 are connected to the surface side of the multilayer wiring board of the circuit module by the solder layer 24. As shown in FIG. 1, this multilayer wiring board 20 is composed of a multilayer ceramic substrate. From the chip component side, wiring patterns 1 2a to 1st board 11, 2nd board 15 and 3rd board 18 are respectively provided. , 14, 17, 12b Snoley Honore connecting these 13, 16, 19 forces are formed!
  • the interchip connecting chip component 30 shown in FIG. 2 is prepared. Then, as shown in FIG. 4 (b), the solder layer 24 is applied to the connection terminal region of the multilayer wiring board 10 using a dispenser, and the chip component 30 for board-to-board connection 30 is placed and heated, so that the multilayer wiring board is heated. 10 and the chip part 30 for connecting between plates are joined.
  • the solder is heated while supplying the dispenser side force, and the interchip connecting chip component and the flexible wiring board 40 are connected.
  • inter-plate connecting chip components are used, so six inter-plate connecting chip components 30 are temporarily fixed at predetermined positions of the multilayer wiring board 10. If bonding is performed by batch heating, bonding can be performed with better workability.
  • the inter-plate connecting chip parts 30 can be connected together and the terminals are arranged in a one-dimensional manner, so that it can be used for general purposes. In other words, if the connection terminal area is long, a plurality of chip components for inter-plate connection can be used.
  • the concave groove 33 provided on the side surface of the conductive region 31 of the inter-plate connecting chip component 30 helps to increase the contact area between the connection terminal region on the wiring board surface and the solder layer. .
  • it acts as a reservoir that prevents the solder layer from flowing out, and as a result, the isolated region that is a protruding region acts as a dam. This suppresses the solder from spreading indefinitely and increases the area of the solder joint, thereby ensuring reliable and strong electrical and physical connection.
  • connection between the substrates can be easily realized with chip parts with good workability, and the presence of the insulating region can surely prevent a short circuit between the conductive paths.
  • the insulating substrate constituting the insulating region 32 and the conductive substrate constituting the conductive region 31 are alternately laminated to form a laminate, and the cut surface is the first surface 30a. And a step of cutting the stacked body perpendicularly to the stacking direction so as to constitute the second surface 30b.
  • the laminated body is cut perpendicularly to the stacking direction so that the cut surfaces constitute the first and second surfaces, the flat surface can be easily formed and more reliable connection can be achieved. Is possible.
  • the insulating substrate constituting the insulating region 32 and the conductive substrate constituting the conductive region 31 are alternately laminated to form a laminate.
  • the stacked body is cut along the dicing line DL perpendicularly to the stacking direction so that the cut surfaces form the first surface 30a and the second surface 30b.
  • the base to be the chip component 30 for connecting the plates obtained in this way is formed.
  • an insulating coating layer 34 is formed on the insulating regions of the first and second surfaces by a coating method.
  • resists Rl and R2 are applied to the first surface 30a and the second surface 30b, and the conductive region 31 is etched to thereby form the conductive region 31.
  • a concave groove 33 is formed on the side surface (FIG. 7 (b)).
  • the force described in the chip component for connecting between plates in which the conductive regions 31 are formed at an equal pitch is not necessarily the same pitch, and the first surface and the second surface are electrically connected. It may be formed so that the pitch of the sex region 31 is different! /.
  • FIG. 8 is a diagram showing a chip component for connecting between plates according to an embodiment of the present invention.
  • the concave portion 33 is formed on the side surface of the conductive region 31 of the inter-plate connecting chip component 30.
  • it may have a rectangular parallelepiped shape without forming the concave portion. Is formed by executing the steps of FIGS. 5 to 6 in the first embodiment.
  • FIG. 9 is a diagram showing a chip component for connecting between plates according to the embodiment of the present invention.
  • conductive regions 31P made of a conductor pattern formed by screen printing are formed on the surface of the base substrate 36 having a ceramic substrate force at predetermined intervals, and the base substrate 36 is located between the conductive regions 31P.
  • an insulating coating layer 34 is formed on the surface of the insulating region. A method for manufacturing the inter-plate connecting chip component 30 will be described.
  • a ceramic substrate 36 is prepared, and stripe-shaped conductive patterns 31P are formed at predetermined intervals on the front and back surfaces by screen printing.
  • the ceramic substrate on which this conductive pattern 31P is formed Is cut along the dicing line DL to form a rectangular parallelepiped shape.
  • FIG. 11 (a) rearrangement is made so that the cut surface is on top, and again on the front and back surfaces as shown in FIG. 11 (b) so as to continue to the conductive pattern 31P.
  • a second conductive pattern 31 S is formed.
  • the present invention it is possible to provide a chip component for connecting between plates that is small in size and high in mounting strength, so that the connection between the plates is realized with a thin shape and high reliability.

Abstract

It is possible to easily mount a circuit module on a printed board without requiring a special facility. Moreover, it is possible to significantly simplify the positioning between substrates. An inter-substrate connection chip part is used for connection between wiring substrates having a wiring pattern. A first and a second surface opposing to each other constitute a flat plane. A plurality of conductive regions are arranged via an insulating region on the first and the second surface. The conductive regions are separately formed so as to constitute a plurality of conductive paths for connection from the first surface to the second surface.

Description

明 細 書  Specification
板間接続用チップ部品、その製造方法およびこれを用いた配線基板の接 糸) C方法  Chip component for board-to-board connection, its manufacturing method, and wiring board wiring using the same) Method C
技術分野  Technical field
[0001] 本発明は板間接続用チップ部品、その製造方法およびこれを用いた配線基板の 接続方法に係り、特に、配線基板間の一括接続に用いられる接続用チップ部品に関 する。  The present invention relates to a chip component for inter-plate connection, a method for manufacturing the same, and a method for connecting a wiring board using the same, and particularly relates to a chip component for connection used for collective connection between wiring boards.
背景技術  Background art
[0002] 榭脂製あるいはセラミック製の配線基板上に、半導体素子や抵抗、コンデンサなど を搭載して実装回路モジュールが広く用いられている。その構造は、一般に基板上 に形成された配線層とそれを絶縁する絶縁層からなり、基板上の配線層が基板内に 設けられたビア (スルー) ·ホールと呼ばれる孔状の導体めつき層(導通ビア)によって 相互に接続されている。  [0002] Mounted circuit modules are widely used in which semiconductor elements, resistors, capacitors, and the like are mounted on a wiring board made of resin or ceramic. The structure is generally composed of a wiring layer formed on the substrate and an insulating layer that insulates it, and the wiring layer on the substrate is a hole-like conductor contact layer called a via hole provided in the substrate. They are connected to each other by (conduction vias).
[0003] この回路基板として、近年、表層配線プリント回路 (SLC)基板のような高密度なも のが用いられるようになつてきた。 SLCとは、基板と、その表層配線層よりなり、表層 配線層は配線層と絶縁層との積層体であり、配線層間は導通ビアを介して相互に接 続されている。また、基板両面上の配線間の接続は、基板内の導通ビア (スルーホー ル)により行われる。このような SLC基板を用いた実装回路モジュールのビルドアップ 基板の下部は、キャリア接続用の半田ボール (ボール ·ダリッド ·アレイ)を介して実装 基板 (マザ一ボード等)と電気的に接続される。一方、ビルドアップ基板の上部には、 チップ接続バンプ (半田バンプ)を介して半導体チップが電気的に接続される。  In recent years, a high-density circuit board such as a surface wiring printed circuit (SLC) board has come to be used as this circuit board. The SLC is composed of a substrate and its surface wiring layer. The surface layer wiring layer is a laminate of a wiring layer and an insulating layer, and the wiring layers are connected to each other through conductive vias. In addition, the connection between the wirings on both sides of the board is made by conductive vias (through holes) in the board. Build-up of mounting circuit module using such SLC board The lower part of the board is electrically connected to the mounting board (mother board, etc.) via the solder balls (ball-dally-array) for carrier connection . On the other hand, a semiconductor chip is electrically connected to the upper part of the buildup substrate via chip connection bumps (solder bumps).
[0004] 接続に際しては、図 12に示すように、電子部品 20の搭載されたプリント基板 10を 半田ボール 130を介して個別に、フレキシブル配線基板 40すなわちフレキシブル基 板 42上の接続端子 43に接続するという方法がとられる。  [0004] When connecting, as shown in FIG. 12, the printed circuit board 10 on which the electronic component 20 is mounted is individually connected to the flexible wiring board 40, that is, the connection terminal 43 on the flexible board 42 via the solder ball 130. The method of doing is taken.
上記構造では、図 13 (a)乃至 (d)にその接続工程を示すように、電子部品 20の搭 載されたプリント基板 10 (図 13 (a) )上の所望の位置に半田ボール 130を位置決めし て装着し (図 13 (b) )、これを、フレキシブル基板 40上の接続端子 43 (図 13 (c) )に装 着してリフローすることにより形成される(図 13 (d) )。この方法の場合、接続板間接続 用の半田ボール 130を接続ポイントに個別に搭載する必要がある。 In the above structure, as shown in the connection process in FIGS. 13A to 13D, the solder ball 130 is placed at a desired position on the printed circuit board 10 (FIG. 13A) on which the electronic component 20 is mounted. Position and install (Fig. 13 (b)), and attach this to the connection terminal 43 (Fig. 13 (c)) on the flexible board 40. It is formed by wearing and reflowing (Fig. 13 (d)). In this method, it is necessary to individually mount solder balls 130 for connection between connection plates at connection points.
[0005] 特許文献 1:特開 2001-102749 Patent Document 1: JP 2001-102749 A
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0006] このように上記構造では、図 13にその接続工程を示すように、板間接続用の半田 ボール 130を接続ポイントに個別に搭載する必要があり、部品点数が増加するという 問題があった。また、位置決めも重要な問題であり、搭載に多大な時間を要する上、 位置ずれが生じ易!ヽと ヽぅ問題もあった。 As described above, in the above structure, as shown in the connection process in FIG. 13, it is necessary to individually mount the solder balls 130 for connecting the plates to the connection points, which increases the number of parts. It was. Positioning is also an important issue. It takes a lot of time for mounting, and misalignment easily occurs.
また効率よく接続するためには、半田ボールを搭載するための専用設備が必要と なり、コストの高騰につながるという問題があった。  In addition, in order to connect efficiently, a dedicated facility for mounting solder balls is required, leading to a problem of increased costs.
[0007] 本発明は、前記実情に鑑みてなされたもので、特別な設備を要することなく容易に 回路モジュールのプリント基板への実装を可能にすることを目的とする。 [0007] The present invention has been made in view of the above circumstances, and an object thereof is to enable easy mounting of a circuit module on a printed circuit board without requiring special equipment.
また、併せて、基板間の位置合わせを効率的に容易化することを目的とする。 課題を解決するための手段  In addition, another object is to efficiently facilitate alignment between substrates. Means for solving the problem
[0008] 本発明は、配線パターンの形成された配線基板との基板同士の接続に用いられる 板間接続用チップ部品であって、相対向する第 1および第 2の面が平坦面を構成し、 前記第 1および第 2の面には複数の導電性領域と、絶縁性領域とが配列され、前記 導電性領域は、前記第 1の面から、前記第 2の面に接続する複数の導電路を構成す るように、前記絶縁性領域によって分離形成される。 [0008] The present invention is an inter-plate connecting chip component used for connecting substrates to a wiring substrate on which a wiring pattern is formed, wherein the first and second surfaces facing each other form a flat surface. A plurality of conductive regions and an insulating region are arranged on the first and second surfaces, and the conductive region is connected to the second surface from the first surface. The insulating regions are formed so as to form a path.
この構成によれば、基板間の接続を、チップ部品によって容易に作業性よく実現で き、絶縁性領域の存在により、導電路間の短絡を確実に防止することができる。  According to this configuration, the connection between the substrates can be easily realized with chip parts with good workability, and the presence of the insulating region can surely prevent a short circuit between the conductive paths.
[0009] また本発明は、上記板間接続用チップ部品において、前記導電性領域は、前記第[0009] Further, the present invention provides the above-described chip component for board connection, wherein the conductive region is the first part.
1および第 2の面のうち少なくとも一方で、一次元配列されるものを含む。 One of the first and second surfaces includes one-dimensionally arranged ones.
この構成によれば、所定の長さに切断して、いかなる箇所にも装着できるため、汎 用性が高い。  According to this configuration, it can be cut into a predetermined length and can be attached to any location, so that it is highly versatile.
[0010] また本発明は、上記板間接続用チップ部品において、前記導電性領域は、前記第 1の面力 第 2の面に向けて配列された柱状領域であるものを含む。 この構成によれば、柱状領域によって確実に導電路が確保される。 [0010] Further, the present invention includes the above-described chip component for board connection, wherein the conductive region is a columnar region arranged toward the second surface with the first surface force. According to this configuration, the conductive path is reliably ensured by the columnar region.
[0011] また本発明は、上記板間接続用チップ部品において、前記導電性領域は、前記第 [0011] Further, the present invention provides the above-described chip component for inter-plate connection, wherein the conductive region is the first part.
1の面から、第 2の面に向けて、前記第 1および第 2の面の端部に当接する側面に配 設された導電性パターンを含む。 From the first surface to the second surface, a conductive pattern disposed on the side surface in contact with the end portions of the first and second surfaces is included.
この構成によれば、簡単な構成でかつ製造が容易である。  According to this configuration, the configuration is simple and the manufacture is easy.
[0012] また本発明は、上記板間接続用チップ部品において、前記第 1および第 2の面の 少なくとも一方において前記導電性領域間に配設された絶縁性コーティング層を含 む。 [0012] The present invention also includes the above-described chip component for connecting plates, including an insulating coating layer disposed between the conductive regions on at least one of the first and second surfaces.
この構成によれば、絶縁性コーティング層の存在により、半田の流れ出しを抑制し 短絡を防止することができる。  According to this configuration, due to the presence of the insulating coating layer, the flow of solder can be suppressed and a short circuit can be prevented.
[0013] また本発明は、上記板間接続用チップ部品において、前記第 1および第 2の面の 少なくとも一方の近傍で、前記導電性領域は凹部を構成しているものを含む。 [0013] In addition, the present invention includes the above-described chip component for inter-plate connection, wherein the conductive region forms a recess in the vicinity of at least one of the first and second surfaces.
この構成によれば、凹部が、半田の流出を妨げる液溜めの役割を果たし、より確実 に半田の流れ出しを抑制することができる。  According to this configuration, the recess serves as a liquid reservoir that prevents the solder from flowing out, and the solder flow can be more reliably suppressed.
[0014] また本発明は、上記板間接続用チップ部品にお 、て、前記柱状領域は、両側面に 第 1の面から第 2の面まで貫通する凹溝を具備したものを含む。 [0014] In addition, the present invention includes the above-described chip component for inter-plate connection, wherein the columnar region includes concave grooves penetrating from the first surface to the second surface on both side surfaces.
この構成によれば、凹溝が、配線基板面の接続端子上と、半田層との接触面積を 増大するのに役立ち、半田層の流出を妨げる液溜めの役割を果たし、結果的に突出 領域となっている絶縁性領域がダムの働きをする。これにより、半田が無制限に広が るのを抑制し、半田接合部の面積を増大することになり、電気的および物理的接続 が確実かつ強固となる。  According to this configuration, the concave groove serves to increase the contact area between the connection terminal on the wiring board surface and the solder layer, and serves as a liquid reservoir that prevents the solder layer from flowing out. The insulative area becomes a dam. This suppresses the solder from spreading indefinitely and increases the area of the solder joint, thereby ensuring reliable and strong electrical and physical connection.
[0015] また本発明は、絶縁性基板からなる絶縁性領域と、導電性基板からなる導電性領 域が、第 1および第 2の面に直交する方向に積層された積層体で構成されたものを 含む。 [0015] Further, the present invention is configured by a laminate in which an insulating region made of an insulating substrate and a conductive region made of a conductive substrate are stacked in a direction perpendicular to the first and second surfaces. Including things.
この構成によれば、凹部が、半田の流出を妨げる液だめの役割を果たし、より確実 に半田の流れ出しを抑制することができる。  According to this configuration, the recess serves as a liquid reservoir that prevents the solder from flowing out, and the solder flow can be more reliably suppressed.
[0016] また本発明は、上記板間接続用チップ部品において、前記絶縁性基板はセラミック 基板であるものを含む。 この構成によれば、強固で確実な板間接続用チップ部品を構成することができる。 [0016] Further, the present invention includes the above-described chip component for board connection, wherein the insulating substrate is a ceramic substrate. According to this configuration, it is possible to configure a firm and reliable chip component for inter-plate connection.
[0017] また本発明は、上記板間接続用チップ部品において、前記絶縁性基板は榭脂基 板であるものを含む。  [0017] Further, the present invention includes the above-described chip component for inter-plate connection, wherein the insulating substrate is a resin substrate.
この構成によれば、強固で確実な板間接続用チップ部品を構成することができる。  According to this configuration, it is possible to configure a firm and reliable chip component for inter-plate connection.
[0018] また本発明は、上記板間接続用チップ部品において、前記導電性基板は金属基 板であるものを含む。  [0018] Further, the present invention includes the above-described chip component for inter-plate connection, wherein the conductive substrate is a metal substrate.
この構成によれば、強固で確実な板間接続用チップ部品を構成することができる。  According to this configuration, it is possible to configure a firm and reliable chip component for inter-plate connection.
[0019] また本発明は、配線パターンの形成された配線基板との基板同士の接続に用いら れる板間接続用チップ部品の製造方法であって、相対向する第 1および第 2の面が 平坦面を構成し、前記第 1および第 2の面には複数の導電性領域が、絶縁性領域を 介して配列され、前記導電性領域が、前記第 1の面から、前記第 2の面に接続する複 数の導電路を構成するように、前記導電性領域と前記絶縁性領域とを配列するよう にした方法である。  [0019] The present invention is also a method of manufacturing a chip component for inter-plate connection used for connecting substrates with a wiring substrate on which a wiring pattern is formed, wherein the first and second surfaces facing each other are provided. A plurality of conductive regions are arranged on the first and second surfaces through insulating regions, and the conductive regions are arranged from the first surface to the second surface. The conductive region and the insulating region are arranged so as to form a plurality of conductive paths connected to the.
[0020] また本発明は、上記板間接続用チップ部品の製造方法において、絶縁性基板と、 導電性基板とを交互に積層し、積層体を形成する工程と、切断された面が第 1および 第 2の面を構成するように、前記積層体を、積層方向に垂直に切断する工程とを含 む。  [0020] Further, according to the present invention, in the method for manufacturing a chip component for inter-plate connection, a step of alternately laminating an insulating substrate and a conductive substrate to form a laminate, and the cut surface is a first surface. And a step of cutting the stacked body perpendicularly to the stacking direction so as to constitute the second surface.
この構成によれば、切断面が第 1および第 2の面を構成するように、前記積層体を、 積層方向に垂直に切断しているため、平坦面の形成が容易となり、より確実な接続が 可能となる。  According to this configuration, since the laminated body is cut perpendicularly to the stacking direction so that the cut surfaces constitute the first and second surfaces, the flat surface can be easily formed and more reliable connection can be achieved. Is possible.
[0021] また本発明は、上記板間接続用チップ部品の製造方法において、前記積層体を形 成する工程後、前記切断する工程に先立ち、切断面に沿って、前記導電性基板にス ルーホールを形成する工程を含み、前記切断する工程は、前記スルーホールを分断 する位置で切断する工程を含む。  [0021] Further, the present invention provides the above-described method for manufacturing a chip component for inter-plate connection, wherein, after the step of forming the laminate, prior to the step of cutting, a through hole is formed in the conductive substrate along the cut surface. The step of cutting includes a step of cutting at a position where the through hole is cut.
この構成によれば、スルーホールを形成し、これを分断するように切断することによ り、側面の凹部が同時形成され、生産性が向上する。  According to this configuration, by forming the through hole and cutting it so as to divide it, the recesses on the side surfaces are simultaneously formed, and the productivity is improved.
[0022] また本発明は、上記板間接続用チップ部品の製造方法において、絶縁性基板の 表面及び裏面に、ストライプ状の第 1の導電性パターンを形成する工程と、前記第 1 の導電性パターンに直交する方向に、前記絶縁性基板を、所定幅に切断し、所定幅 の板状体を形成する工程と、前記板状体を、前記第 1の導電性パターンの形成され た面同士が当接するように再配列し、切断面を揃える再配列工程と、再配列された 前記切断面に、前記第 1の導電性パターンに符合するようにストライプ状の第 2の導 電性パターンを形成する工程とを含む。 [0022] Further, the present invention provides the above-described method for manufacturing a chip component for inter-plate connection, the step of forming a stripe-shaped first conductive pattern on the front surface and the back surface of the insulating substrate; Cutting the insulating substrate into a predetermined width in a direction perpendicular to the conductive pattern to form a plate-like body having a predetermined width; and forming the plate-like body into the first conductive pattern. A rearrangement step of rearranging the cut surfaces so as to make contact with each other and aligning the cut surfaces; and a second conductive strip in the rearrangement so as to match the first conductive pattern on the rearranged cut surfaces. Forming a sex pattern.
この構成によれば、絶縁性基板の表面に導電性パターンをストライプ状に形成する ことにより、低コストで同様の効果を奏功しうるものとなる。  According to this configuration, the same effect can be achieved at low cost by forming the conductive pattern in the form of stripes on the surface of the insulating substrate.
[0023] また本発明は、上記板間接続用チップ部品の製造方法において、前記第 1および 第 2の導電性パターンを形成する工程は、スクリーン印刷工程を含む。 [0023] Further, according to the present invention, in the method for manufacturing a chip component for inter-plate connection, the step of forming the first and second conductive patterns includes a screen printing step.
この構成によれば、前記第 1および第 2の導電性パターンを形成する工程は、スクリ ーン印刷工程であるため、効率よく高精度のノターン形成を行うことが可能となる。  According to this configuration, since the process of forming the first and second conductive patterns is a screen printing process, it is possible to efficiently perform highly accurate pattern formation.
[0024] また本発明は、上記板間接続用チップ部品の製造方法において、前記第 2の導電 性パターンを形成する工程は、インクジェット法による塗布工程を含む。 [0024] Further, according to the present invention, in the method for manufacturing a chip component for inter-plate connection, the step of forming the second conductive pattern includes a coating step by an ink jet method.
この構成によれば、凹凸のある表面に対しても効率よぐ高精度のパターン形成が 可能となる。  According to this configuration, it is possible to form a highly accurate pattern with high efficiency even on an uneven surface.
[0025] また本発明は、相対向する第 1および第 2の面が平坦面を構成し、前記第 1および 第 2の面には複数の導電性領域が、絶縁性領域を介して配列され、前記導電性領 域が、前記第 1の面から、前記第 2の面に接続する複数の導電路を構成するように、 絶縁性領域で分離形成された板間接続用チップ部品を用意する工程と、第 1の配線 基板の第 1の接続用端子領域に、前記板間接続用チップ部品を前記第 1の面が前 記接続用端子領域に当接するように配置し、半田接合する第 1の工程と、板間接続 用チップ部品の前記第 2の面が第 2の配線基板の第 2の接続用端子領域に当接する ように配置し、半田接合する第 2の工程とを含む。  [0025] Further, according to the present invention, the first and second surfaces facing each other form a flat surface, and a plurality of conductive regions are arranged on the first and second surfaces via insulating regions. Preparing a chip component for inter-plate connection formed separately in an insulating region so that the conductive region constitutes a plurality of conductive paths connecting from the first surface to the second surface. In the first connection terminal region of the first wiring board, the inter-plate connection chip component is disposed so that the first surface is in contact with the connection terminal region, and solder-bonded. And a second step in which the second surface of the interchip connecting chip component is disposed so as to abut on the second connecting terminal region of the second wiring board and soldered.
この構成によれば、効率よく一括して、板間接続することが容易となる。  According to this structure, it becomes easy to connect between boards efficiently and collectively.
[0026] また本発明は、上記配線基板の接続方法において、前記第 1および第 2の工程は 、前記第 1および第 2の接続用端子領域の前記第 1および第 2の面との当接面よりも 外側にも半田層を形成し、それぞれ前記第 1および第 2の面からこれらに連接された 側面にかけて接合領域を形成するものを含む。 この構成によれば、第 1および第 2の接続用端子領域の前記第 1および第 2の面と の当接面だけでなぐ側面でも電気的接続および物理的接続がなされるため、より確 実な接続が可能となる。 [0026] Further, in the wiring board connection method according to the present invention, the first and second steps are in contact with the first and second surfaces of the first and second connection terminal regions. A solder layer is also formed on the outer side of the surface, and a joining region is formed from the first and second surfaces to the side surface connected to the first and second surfaces. According to this configuration, electrical connection and physical connection are made even on the side surfaces of the first and second connection terminal regions that are not just the contact surfaces with the first and second surfaces, so that the connection is more reliable. Connection is possible.
[0027] また本発明は、上記配線基板の接続方法において、前記導電性領域の側面に凹 溝が形成されており、前記第 1および第 2の工程は前記凹溝内に半田が流れ込むよ うに接合領域を形成する工程であるものを含む。 [0027] Further, according to the present invention, in the method for connecting wiring boards, a groove is formed on a side surface of the conductive region, and in the first and second steps, the solder flows into the groove. This includes a process for forming a bonding region.
この構成によれば、凹溝内に半田が流れ込むように接合領域が形成されるため、 接続面積の増大をは力ることができ、接合性が高められる上、凹溝の壁面が液溜め として作用するためより強固で信頼性の高い接合が可能となる。  According to this configuration, since the joining region is formed so that the solder flows into the recessed groove, it is possible to increase the connection area, the joining property is improved, and the wall surface of the recessed groove serves as a liquid reservoir. As a result, the bonding becomes stronger and more reliable.
[0028] また本発明は、上記配線基板の接続方法において、前記第 1および第 2の配線基 板の少なくとも一方は、硬質基板 (リジッド基板)であるものを含む。 [0028] Further, the present invention includes the above wiring board connection method, wherein at least one of the first and second wiring boards is a hard board (rigid board).
この構成によれば、硬質基板が平坦性を維持することができるため、両配線基板間 の剥がれを防止することができる。  According to this configuration, since the hard substrate can maintain flatness, peeling between the two wiring substrates can be prevented.
[0029] また本発明は、上記配線基板の接続方法において、前記第 1および第 2の配線基 板の少なくとも一方は、フレキシブル基板であるものを含む。 [0029] Further, the present invention includes the above wiring board connection method, wherein at least one of the first and second wiring boards is a flexible board.
上記構成によれば、フレキシブル配線基板は可撓性を有し、空間の利用がし易い ことから、配線基板間の接続やガラス基板等との接続に、よく用いられる。本発明を 適用することにより、直接に接続されたフレキシブル基板が剥がれにくくなり、このこと は、電子製品の歩留まりや信頼性の低下の抑制につながる。  According to the said structure, since a flexible wiring board has flexibility and it is easy to use space, it is often used for the connection between wiring boards or a glass substrate. By applying the present invention, the directly connected flexible substrate is less likely to be peeled off, which leads to a reduction in yield and reliability of electronic products.
発明の効果  The invention's effect
[0030] 本発明によれば、複数の板間接続ポイントを一括で接続することが可能で部品点 数の削減を図ることが可能となる。また、部品搭載用の専用実装設備が不要であり、 標準的な設備構成で効率よい実装を実現することができる。  [0030] According to the present invention, a plurality of inter-plate connection points can be connected together, and the number of parts can be reduced. In addition, dedicated mounting equipment for mounting components is not required, and efficient mounting can be realized with a standard equipment configuration.
図面の簡単な説明  Brief Description of Drawings
[0031] [図 1]本発明の実施の形態 1の板間接続用チップ部品を用いて実装した回路モジュ ールを示す図  [0031] FIG. 1 is a diagram showing a circuit module mounted using the inter-plate connecting chip component according to the first embodiment of the present invention.
[図 2]本発明の実施の形態 1の板間接続用チップ部品を示す図  FIG. 2 is a diagram showing a chip component for inter-plate connection according to Embodiment 1 of the present invention.
[図 3]本発明の実施の形態 1の回路モジュールの上面図 [図 4]本発明の実施の形態 1の板間接続用チップ部品を用いた板間接続工程を示す 図 FIG. 3 is a top view of the circuit module according to the first embodiment of the present invention. FIG. 4 is a view showing an inter-plate connection process using the inter-plate connection chip component according to the first embodiment of the present invention.
[図 5]本発明の実施の形態 1の板間接続用チップ部品の製造工程図  FIG. 5 is a manufacturing process diagram of a chip component for inter-plate connection according to Embodiment 1 of the present invention.
[図 6]本発明の実施の形態 1の板間接続用チップ部品の製造工程図  FIG. 6 is a manufacturing process diagram of a chip component for inter-board connection according to Embodiment 1 of the present invention.
[図 7]本発明の実施の形態 1の板間接続用チップ部品の製造工程図  FIG. 7 is a manufacturing process diagram of a chip component for inter-board connection according to Embodiment 1 of the present invention.
[図 8]本発明の実施の形態 2の板間接続用チップ部品を示す図  FIG. 8 is a diagram showing a chip part for connecting between plates according to the second embodiment of the present invention.
[図 9]本発明の実施の形態 3の板間接続用チップ部品を示す図  FIG. 9 is a view showing a chip part for connecting between plates according to a third embodiment of the present invention.
[図 10]本発明の実施の形態 3の板間接続用チップ部品の製造工程を示す図  FIG. 10 is a diagram showing a manufacturing process of the interchip connecting chip part according to the third embodiment of the present invention.
[図 11]本発明の実施の形態 3の板間接続用チップ部品の製造工程を示す図  FIG. 11 is a diagram showing a manufacturing process of the inter-plate connecting chip part according to the third embodiment of the present invention.
[図 12]従来例の板間接続用チップ部品を用いて実装した回路モジュールを示す図 [FIG. 12] A diagram showing a circuit module mounted using a conventional chip component for inter-plate connection.
[図 13]従来例の回路モジュールの製造工程を示す図 FIG. 13 is a diagram showing a manufacturing process of a conventional circuit module.
符号の説明  Explanation of symbols
[0032] 10 多層配線基板 [0032] 10 multilayer wiring board
20 チップ部品  20 chip parts
30 板間接続用チップ部品  30 Chip components for board-to-board connection
31 導電性領域  31 Conductive area
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0033] 次に、本発明の実施の形態について、図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
(実施の形態 1)  (Embodiment 1)
[0034] 図 1は本発明の実施の形態の板間接続用チップ部品を用いて実装された回路モジ ユール 100を示す断面図である。図 2は本実施の形態の板間接続用チップ部品、図 3は図 1の回路モジュール 100の上面図である。図 4はこの板間接続用チップ部品を 用いた板間接続方法を用いた回路モジュールの実装工程を示す図、図 5乃至図 7は 板間接続用チップ部品の製造工程を示す図である。  FIG. 1 is a cross-sectional view showing a circuit module 100 mounted using the inter-plate connecting chip component according to the embodiment of the present invention. FIG. 2 is a chip part for inter-plate connection of the present embodiment, and FIG. 3 is a top view of the circuit module 100 of FIG. FIG. 4 is a diagram illustrating a circuit module mounting process using the inter-plate connection method using the inter-plate connecting chip component, and FIGS. 5 to 7 are diagrams illustrating a manufacturing process of the inter-chip connecting chip component.
[0035] 本実施の形態では、図 1に示すように、ポリイミド榭脂系のフィルム素材 42の表面及 び裏面に配線パターン 43, 41の形成されたフレキシブル配線基板 40に、板間接続 用チップ部品 30を介して、多層配線基板 10が接続され、板間接続を達成したことを 特徴とする。 [0036] ここで板間接続用チップ部品 30は、図 2に示すように、配線パターンの形成された 配線基板との基板同士の接続に用いられる板間接続用チップ部品であって、相対向 する第 1および第 2の面 30a、 30bが平坦面を構成し、前記第 1および第 2の面には 複数の同一幅の導電性領域 31と、絶縁性領域 32とが配列形成され、この導電性領 域 31は、前記第 1の面から、前記第 2の面に接続する複数の導電路を構成するよう に、絶縁性領域 32によって分離形成される。 34は絶縁性コーティング層である。 In the present embodiment, as shown in FIG. 1, an inter-plate connection chip is formed on a flexible wiring board 40 having wiring patterns 43 and 41 formed on the front and back surfaces of a polyimide resin film material 42. The multilayer wiring board 10 is connected via the component 30 to achieve board-to-board connection. [0036] Here, the inter-plate connecting chip component 30 is an inter-plate connecting chip component used to connect the substrates with the wiring substrate on which the wiring pattern is formed, as shown in FIG. The first and second surfaces 30a, 30b are flat surfaces, and a plurality of conductive regions 31 having the same width and insulating regions 32 are arranged on the first and second surfaces. The conductive region 31 is formed separately from the first surface by the insulating region 32 so as to constitute a plurality of conductive paths connected to the second surface. Reference numeral 34 denotes an insulating coating layer.
[0037] また、この導電性領域は柱状の導電路を構成し、両側面に第 1の面 30aから第 2の 面 30bまで貫通する凹溝 33を具備して 、る。 [0037] Further, this conductive region constitutes a columnar conductive path, and has concave grooves 33 penetrating from the first surface 30a to the second surface 30b on both side surfaces.
[0038] 回路モジュール 100は、図 1に断面図、図 3に上面図を示すように、回路モジユー ルの多層配線基板 10の周縁部に 6個の板間接続用チップ部品 30が配列されている 。また、この回路モジュールの多層配線基板の表面側には固体撮像素子チップ 21、 コンデンサ 22、抵抗 23などのチップ部品が半田層 24によって接続されて!、る。 この多層配線基板 20は図 1に示すように、積層セラミック基板で構成されており、チ ップ部品側から第 1基板 11、第 2基板 15、第 3基板 18に、それぞれ、配線パターン 1 2a, 14, 17, 12bこれらをつなぐスノレーホ一ノレ 13, 16, 19力 ^形成されて!/、る。 [0038] As shown in the cross-sectional view of FIG. 1 and the top view of FIG. 3, the circuit module 100 has six inter-plate connecting chip components 30 arranged on the periphery of the multilayer wiring board 10 of the circuit module. Yes. Further, chip components such as the solid-state imaging device chip 21, the capacitor 22, and the resistor 23 are connected to the surface side of the multilayer wiring board of the circuit module by the solder layer 24. As shown in FIG. 1, this multilayer wiring board 20 is composed of a multilayer ceramic substrate. From the chip component side, wiring patterns 1 2a to 1st board 11, 2nd board 15 and 3rd board 18 are respectively provided. , 14, 17, 12b Snoley Honore connecting these 13, 16, 19 forces are formed!
[0039] 次に、この板間接続用チップ部品 30を用いた板間接続方法にっ 、て説明する。 Next, the inter-plate connection method using the inter-plate connection chip component 30 will be described.
図 4 (a)に示すように、図 2に示した板間接続用チップ部品 30を用意する。そして図 4 (b)に示すように、多層配線基板 10の接続端子領域に半田層 24をデイスペンサを 用いて塗布し、板間接続用チップ部品 30を載せて加熱することにより、多層配線基 板 10と板間接続用チップ部品 30とを接合する。  As shown in FIG. 4 (a), the interchip connecting chip component 30 shown in FIG. 2 is prepared. Then, as shown in FIG. 4 (b), the solder layer 24 is applied to the connection terminal region of the multilayer wiring board 10 using a dispenser, and the chip component 30 for board-to-board connection 30 is placed and heated, so that the multilayer wiring board is heated. 10 and the chip part 30 for connecting between plates are joined.
続いて、図 4 (c)に示すように、フレキシブル配線基板 40の配線パターン 43上に板 間接続用チップ部品 30の第 2の面 30bが当接するように位置決めする。  Subsequently, as shown in FIG. 4 (c), positioning is performed so that the second surface 30b of the inter-plate connecting chip part 30 contacts the wiring pattern 43 of the flexible wiring board 40.
そして、図 4 (d)に示すように、半田をデイスペンサ側方力 供給しながら加熱し板 間接続用チップ部品とフレキシブル配線基板 40とを接続する。  Then, as shown in FIG. 4 (d), the solder is heated while supplying the dispenser side force, and the interchip connecting chip component and the flexible wiring board 40 are connected.
このようにして極めて容易に板間接続が実現される。  In this way, the inter-plate connection can be realized very easily.
図 3に示したように、本実施の形態では、 6個の板間接続用チップ部品を用いるた め、多層配線基板 10の所定の箇所に 6個の板間接続用チップ部品 30を仮留めし、 一括加熱により接合するようにすれば、より作業性よく接合することが可能となる。 [0040] この構成によれば、板間接続用チップ部品 30によって、一括接続することができ、 し力も一次元に端子が配列されているため、汎用的に用いることができる。つまり、接 続端子領域が長 、場合は複数個の板間接続用チップ部品を配列して用いればょ ヽ As shown in FIG. 3, in the present embodiment, six inter-plate connecting chip components are used, so six inter-plate connecting chip components 30 are temporarily fixed at predetermined positions of the multilayer wiring board 10. If bonding is performed by batch heating, bonding can be performed with better workability. [0040] According to this configuration, the inter-plate connecting chip parts 30 can be connected together and the terminals are arranged in a one-dimensional manner, so that it can be used for general purposes. In other words, if the connection terminal area is long, a plurality of chip components for inter-plate connection can be used.
[0041] また、板間接続用チップ部品 30の導電性領域 31の側面に設けられた凹溝 33が、 配線基板面の接続端子領域上と、半田層との接触面積を増大するのに役立つ。また 、半田層の流出を妨げる液溜めの役割を果たし、結果的に突出領域となっている絶 縁性領域がダムの働きをする。これにより、半田が無制限に広がるのを抑制し、半田 接合部の面積を増大することになり、電気的および物理的接続が確実かつ強固とな る。 [0041] Further, the concave groove 33 provided on the side surface of the conductive region 31 of the inter-plate connecting chip component 30 helps to increase the contact area between the connection terminal region on the wiring board surface and the solder layer. . In addition, it acts as a reservoir that prevents the solder layer from flowing out, and as a result, the isolated region that is a protruding region acts as a dam. This suppresses the solder from spreading indefinitely and increases the area of the solder joint, thereby ensuring reliable and strong electrical and physical connection.
この構成によれば、基板間の接続を、チップ部品によって容易に作業性よく実現で き、絶縁性領域の存在により、導電路間の短絡を確実に防止することができる。  According to this configuration, the connection between the substrates can be easily realized with chip parts with good workability, and the presence of the insulating region can surely prevent a short circuit between the conductive paths.
[0042] 次に、この板間接続用チップ部品の製造方法について説明する。 [0042] Next, a method for manufacturing the chip component for inter-plate connection will be described.
この方法では、絶縁性領域 32を構成する絶縁性基板と、導電性領域 31を構成す る導電性基板とを交互に積層し、積層体を形成し、切断された面が第 1の面 30aおよ び第 2の面 30bを構成するように、積層体を、積層方向に垂直に切断する工程とを含 む。  In this method, the insulating substrate constituting the insulating region 32 and the conductive substrate constituting the conductive region 31 are alternately laminated to form a laminate, and the cut surface is the first surface 30a. And a step of cutting the stacked body perpendicularly to the stacking direction so as to constitute the second surface 30b.
この構成によれば、切断面が第 1および第 2の面を構成するように、前記積層体を、 積層方向に垂直に切断しているため、平坦面の形成が容易となり、より確実な接続が 可能となる。  According to this configuration, since the laminated body is cut perpendicularly to the stacking direction so that the cut surfaces constitute the first and second surfaces, the flat surface can be easily formed and more reliable connection can be achieved. Is possible.
[0043] まず、図 5 (a)に示すように絶縁性領域 32を構成する絶縁性基板と、導電性領域 3 1を構成する導電性基板とを交互に積層し、積層体を形成する。  First, as shown in FIG. 5 (a), the insulating substrate constituting the insulating region 32 and the conductive substrate constituting the conductive region 31 are alternately laminated to form a laminate.
ついで図 5 (b)に示すように、切断面が第 1の面 30aおよび第 2の面 30bを構成する ように、ダイシングライン DLに沿って積層体を、積層方向に垂直に切断する。  Next, as shown in FIG. 5 (b), the stacked body is cut along the dicing line DL perpendicularly to the stacking direction so that the cut surfaces form the first surface 30a and the second surface 30b.
[0044] 図 6 (a)に示すようにこのようにして得られた板間接続用チップ部品 30となるベース が形成される。  [0044] As shown in Fig. 6 (a), the base to be the chip component 30 for connecting the plates obtained in this way is formed.
そして、図 6 (b)に示すように第 1および第 2の面の絶縁性領域に塗布法により絶縁 性コーティング層 34を形成する。 [0045] この後、図 7 (a)に示すように第 1の面 30aおよび第 2の面 30bにレジスト Rl, R2を 塗布し、導電性領域 31をエッチングすることにより、導電性領域 31の側面に凹溝 33 を形成する(図 7 (b) )。 Then, as shown in FIG. 6 (b), an insulating coating layer 34 is formed on the insulating regions of the first and second surfaces by a coating method. Thereafter, as shown in FIG. 7 (a), resists Rl and R2 are applied to the first surface 30a and the second surface 30b, and the conductive region 31 is etched to thereby form the conductive region 31. A concave groove 33 is formed on the side surface (FIG. 7 (b)).
このようにして図 2に示した板間接続用チップ部品が形成される。  In this way, the interchip connecting chip component shown in FIG. 2 is formed.
[0046] このようにして極めて容易に制御性よく寸法精度の高 、板間接続用チップ部品を 形成することができる。 [0046] In this way, a chip component for inter-plate connection can be formed very easily with high controllability and high dimensional accuracy.
なお前記実施の形態では等ピッチで導電性領域 31の形成された板間接続用チッ プ部品について説明した力 等ピッチでなくてもよぐまた第 1の面と第 2の面とで導 電性領域 31のピッチが異なるように形成してもよ!/、。  In the above-described embodiment, the force described in the chip component for connecting between plates in which the conductive regions 31 are formed at an equal pitch is not necessarily the same pitch, and the first surface and the second surface are electrically connected. It may be formed so that the pitch of the sex region 31 is different! /.
[0047] (実施の形態 2) [0047] (Embodiment 2)
図 8は本発明の実施の形態の板間接続用チップ部品を示す図である。 前記実施の形態 1では板間接続用チップ部品 30の導電性領域 31の側面には凹 部 33を形成したが、図 8に示すように、凹部を形成しない直方体形状であってもよい 製造に際しては、前記実施の形態 1における図 5乃至図 6の工程を実行することに より形成される。  FIG. 8 is a diagram showing a chip component for connecting between plates according to an embodiment of the present invention. In the first embodiment, the concave portion 33 is formed on the side surface of the conductive region 31 of the inter-plate connecting chip component 30. However, as shown in FIG. 8, it may have a rectangular parallelepiped shape without forming the concave portion. Is formed by executing the steps of FIGS. 5 to 6 in the first embodiment.
この構成によれば、実施の形態 1の板間接続用チップ部品に比べて製造が容易で あり製造工数の低減をは力ることができる。  According to this configuration, it is easier to manufacture than the inter-plate connecting chip part of the first embodiment, and it is possible to reduce the number of manufacturing steps.
[0048] (実施の形態 3) [0048] (Embodiment 3)
図 9は本発明の実施の形態の板間接続用チップ部品を示す図である。 本実施の形態では、セラミック基板力もなるベース基板 36の表面にスクリーン印刷 によって形成された導体パターンからなる導電性領域 31Pが所定間隔で形成された もので、ベース基板 36が導電性領域 31Pの間に存在して絶縁性領域を構成する。 またここでも絶縁性領域の表面には絶縁性コーティング層 34が形成されている。 この板間接続用チップ部品 30の製造方法について説明する。  FIG. 9 is a diagram showing a chip component for connecting between plates according to the embodiment of the present invention. In the present embodiment, conductive regions 31P made of a conductor pattern formed by screen printing are formed on the surface of the base substrate 36 having a ceramic substrate force at predetermined intervals, and the base substrate 36 is located between the conductive regions 31P. To constitute an insulating region. Also here, an insulating coating layer 34 is formed on the surface of the insulating region. A method for manufacturing the inter-plate connecting chip component 30 will be described.
図 10 (a)に示すように、セラミック基板 36を用意し、表面及び裏面にスクリーン印刷 法により所定の間隔でストライプ状の導電性パターン 31Pを形成する。  As shown in FIG. 10 (a), a ceramic substrate 36 is prepared, and stripe-shaped conductive patterns 31P are formed at predetermined intervals on the front and back surfaces by screen printing.
そして図 10 (b)に示すように、この導電性パターン 31Pの形成されたセラミック基板 をダイシングライン DLに沿って直方体形状をなすように切断する。 Then, as shown in FIG. 10 (b), the ceramic substrate on which this conductive pattern 31P is formed Is cut along the dicing line DL to form a rectangular parallelepiped shape.
この後図 11 (a)に示すように、切断面が上にくるように再配列し、再度導電性パタ ーン 31Pに連続するように図 11 (b)に示すように、表面及び裏面に第 2の導電性バタ ーン 31 Sを形成する。  After that, as shown in FIG. 11 (a), rearrangement is made so that the cut surface is on top, and again on the front and back surfaces as shown in FIG. 11 (b) so as to continue to the conductive pattern 31P. A second conductive pattern 31 S is formed.
このようにして極めて作業性よぐ平坦面を形成することができ、図 9に示した板間 接続用チップ部品が形成される。  In this way, a flat surface with excellent workability can be formed, and the interchip connecting chip component shown in FIG. 9 is formed.
産業上の利用可能性 Industrial applicability
本発明によれば、小型でかつ実装強度の高!、板間接続用チップ部品を提供できる ことから薄型で信頼性の高 、板間接続が実現する。  According to the present invention, it is possible to provide a chip component for connecting between plates that is small in size and high in mounting strength, so that the connection between the plates is realized with a thin shape and high reliability.

Claims

請求の範囲 The scope of the claims
[1] 配線パターンの形成された配線基板との基板同士の接続に用いられる板間接続用 チップ部品であって、  [1] A chip component for inter-board connection used for connection between boards with a wiring board on which a wiring pattern is formed,
相対向する第 1および第 2の面が平坦面を構成し、前記第 1および第 2の面には複 数の導電性領域と、絶縁性領域とが配列され、  The first and second surfaces facing each other form a flat surface, and a plurality of conductive regions and insulating regions are arranged on the first and second surfaces,
前記導電性領域が、前記第 1の面から、前記第 2の面に接続する複数の導電路を 構成するように、前記絶縁性領域によって分離形成された板間接続用チップ部品。  The chip component for board-to-plate connection formed by the insulating region so that the conductive region constitutes a plurality of conductive paths connecting from the first surface to the second surface.
[2] 請求項 1に記載の板間接続用チップ部品であって、 [2] The chip part for connecting between boards according to claim 1,
前記導電性領域は、前記第 1および第 2の面のうち少なくとも一方で、一次元配列 される板間接続用チップ部品。  The conductive region is a chip component for inter-plate connection that is one-dimensionally arranged on at least one of the first and second surfaces.
[3] 請求項 1または 2に記載の板間接続用チップ部品であって、 [3] A chip component for inter-plate connection according to claim 1 or 2,
前記導電性領域は、前記第 1の面から第 2の面に向けて配列された柱状領域であ る板間接続用チップ部品。  The interchip connecting chip component, wherein the conductive region is a columnar region arranged from the first surface toward the second surface.
[4] 請求項 1または 2に記載の板間接続用チップ部品であって、 [4] A chip component for inter-board connection according to claim 1 or 2,
前記導電性領域は、前記第 1の面から第 2の面に向けて、前記第 1および第 2の面 の端部に当接する側面に配設された導電性パターンを含む板間接続用チップ部品  The conductive region includes an inter-plate connection chip including a conductive pattern disposed on a side surface in contact with an end of the first and second surfaces from the first surface to the second surface. Parts
[5] 請求項 1乃至 4の 、ずれかに記載の板間接続用チップ部品であって、 [5] The chip component for inter-plate connection according to any one of claims 1 to 4,
前記第 1および第 2の面の少なくとも一方において前記導電性領域間に配設され た絶縁性コ一ティング層を含む板間接続用チップ部品。  An inter-plate connecting chip component including an insulating coating layer disposed between the conductive regions on at least one of the first and second surfaces.
[6] 請求項 1乃至 5の 、ずれかに記載の板間接続用チップ部品であって、 [6] The chip component for inter-plate connection according to any one of claims 1 to 5,
前記第 1および第 2の面の少なくとも一方の近傍で、前記導電性領域は凹部を構 成して 、る板間接続用チップ部品。  The inter-plate connecting chip component, wherein the conductive region forms a recess in the vicinity of at least one of the first and second surfaces.
[7] 請求項 3に記載の板間接続用チップ部品であって、 [7] The chip component for inter-plate connection according to claim 3,
前記柱状領域は、両側面に第 1の面力 第 2の面まで貫通する凹溝を具備した板 間接続用チップ部品。  The columnar region is a chip component for inter-plate connection having a concave groove penetrating to both sides of the first surface force and the second surface.
[8] 請求項 1乃至 7の 、ずれかに記載の板間接続用チップ部品であって、 [8] The chip component for inter-plate connection according to any one of claims 1 to 7,
絶縁性基板カゝらなる絶縁性領域と、導電性基板からなる導電性領域が、第 1および 第 2の面に直交する方向に積層された積層体で構成された板間接続用チップ部品。 An insulating region made up of an insulating substrate and a conductive region made of a conductive substrate are first and The chip component for board-to-board connection comprised of the laminated body laminated | stacked on the direction orthogonal to a 2nd surface.
[9] 請求項 8に記載の板間接続用チップ部品であって、 [9] The chip component for inter-plate connection according to claim 8,
前記絶縁性基板はセラミック基板である板間接続用チップ部品。  The chip part for board-to-board connection, wherein the insulating substrate is a ceramic substrate.
[10] 請求項 8に記載の板間接続用チップ部品であって、 [10] The chip component for inter-plate connection according to claim 8,
前記絶縁性基板は榭脂基板である板間接続用チップ部品。  The insulating board is a resin board chip component for board connection.
[11] 請求項 8乃至 10のいずれかに記載の板間接続用チップ部品であって、 [11] A chip component for inter-plate connection according to any one of claims 8 to 10,
前記導電性基板は金属基板である板間接続用チップ部品。  The inter-plate connecting chip component, wherein the conductive substrate is a metal substrate.
[12] 配線パターンの形成された配線基板との基板同士の接続に用いられる板間接続用 チップ部品の製造方法であって、 [12] A method of manufacturing a chip component for inter-board connection used for connection between substrates with a wiring substrate on which a wiring pattern is formed,
相対向する第 1および第 2の面が平坦面を構成し、前記第 1および第 2の面には複 数の導電性領域が、絶縁性領域を介して配列され、  The first and second surfaces facing each other form a flat surface, and a plurality of conductive regions are arranged on the first and second surfaces through insulating regions,
前記導電性領域が、前記第 1の面から、前記第 2の面に接続する複数の導電路を 構成するように、前記導電性領域と前記絶縁性領域とを配列するようにした板間接続 用チップ部品の製造方法。  The inter-plate connection in which the conductive region and the insulating region are arranged so that the conductive region constitutes a plurality of conductive paths connecting from the first surface to the second surface. Method for manufacturing chip components.
[13] 請求項 12に記載の板間接続用チップ部品の製造方法であって、 [13] A method of manufacturing a chip component for inter-plate connection according to claim 12,
絶縁性基板と、導電性基板とを交互に積層し、積層体を形成する工程と、 切断された面が第 1および第 2の面を構成するように、前記積層体を、積層方向に 垂直に切断する工程とを含む板間接続用チップ部品の製造方法。  Insulating substrates and conductive substrates are alternately stacked to form a stacked body, and the stacked body is perpendicular to the stacking direction so that the cut surfaces form the first and second surfaces. The manufacturing method of the chip | tip component for board connection including the process cut | disconnected into.
[14] 請求項 13に記載の板間接続用チップ部品の製造方法であって、 [14] A method for manufacturing a chip component for inter-plate connection according to claim 13,
前記積層体を形成する工程後、前記切断する工程に先立ち、切断面に沿って、前 記導電性基板にスルーホールを形成する工程を含み、  After the step of forming the laminate, prior to the cutting step, including a step of forming a through hole in the conductive substrate along the cut surface,
前記切断する工程は、前記スルーホールを分断する位置で切断する工程である板 間接続用チップ部品の製造方法。  The method of manufacturing a chip component for inter-plate connection, wherein the cutting step is a step of cutting at a position where the through hole is divided.
[15] 請求項 12に記載の板間接続用チップ部品の製造方法であって、 [15] A method for manufacturing a chip component for inter-plate connection according to claim 12,
絶縁性基板の表面及び裏面に、ストライプ状の第 1の導電性パターンを形成するェ 程と、  Forming a stripe-shaped first conductive pattern on the front and back surfaces of the insulating substrate; and
前記第 1の導電性パターンに直交する方向に、前記絶縁性基板を、所定幅に切断 し、所定幅の板状体を形成する工程と、 前記板状体を、前記第 1の導電性パターンの形成された面同士が当接するように 再配列し、切断面を揃える再配列工程と、 Cutting the insulating substrate into a predetermined width in a direction orthogonal to the first conductive pattern to form a plate-like body having a predetermined width; A rearrangement step of rearranging the plate-like bodies so that the surfaces on which the first conductive patterns are formed are in contact with each other, and aligning the cut surfaces;
再配列された前記切断面に、前記第 1の導電性パターンに符合するようにストライ プ状の第 2の導電性パターンを形成する工程とを含む板間接続用チップ部品の製造 方法。  Forming a strip-shaped second conductive pattern on the rearranged cut surfaces so as to coincide with the first conductive pattern.
[16] 請求項 15に記載の板間接続用チップ部品の製造方法であって、  [16] A method of manufacturing a chip component for inter-plate connection according to claim 15,
前記第 1および第 2の導電性パターンを形成する工程は、スクリーン印刷工程を含 む板間接続用チップ部品の製造方法。  The step of forming the first and second conductive patterns includes a board printing chip part manufacturing method including a screen printing step.
[17] 請求項 15に記載の板間接続用チップ部品の製造方法であって、 [17] A method of manufacturing a chip component for inter-plate connection according to claim 15,
前記第 2の導電性パターンを形成する工程は、インクジェット法による塗布工程を含 む板間接続用チップ部品の製造方法。  The step of forming the second conductive pattern includes a chip part for board-to-board connection including a coating step by an ink jet method.
[18] 相対向する第 1および第 2の面が平坦面を構成し、前記第 1および第 2の面には複 数の導電性領域が、絶縁性領域を介して配列され、 [18] The first and second surfaces facing each other form a flat surface, and a plurality of conductive regions are arranged on the first and second surfaces through insulating regions,
前記導電性領域は、前記第 1の面から、前記第 2の面に接続する複数の導電路を 構成するように、分離形成された板間接続用チップ部品を用意する工程と、  A step of preparing chip-parts for board-to-board connection separately formed so that the conductive region forms a plurality of conductive paths connected from the first surface to the second surface;
第 1の配線基板の第 1の接続用端子領域に、  In the first connection terminal area of the first wiring board,
前記板間接続用チップ部品を前記第 1の面が前記接続用端子領域に当接するよう に配置し、半田接合する第 1の工程と、  A first step in which the inter-plate connecting chip component is disposed such that the first surface is in contact with the connecting terminal region and soldered;
板間接続用チップ部品の前記第 2の面が第 2の配線基板の第 2の接続用端子領域 に当接するように配置し、半田接合する第 2の工程とを含む配線基板の接続方法。  A wiring board connecting method comprising: a second step of arranging and soldering the second surface of the interchip connecting chip component so as to contact the second connecting terminal region of the second wiring board.
[19] 請求項 18に記載の配線基板の接続方法であって、 [19] The wiring board connection method according to claim 18,
前記第 1および第 2の工程は、前記第 1および第 2の接続用端子領域の前記第 1お よび第 2の面との当接面よりも外側にも半田層を形成し、それぞれ前記第 1および第 2の面カゝらこれらに連接された側面にかけて接合領域を形成してなる配線基板の接 続方法。  In the first and second steps, a solder layer is formed outside the contact surface of the first and second connection terminal regions with the first and second surfaces, respectively. A method of connecting a wiring board, wherein a bonding region is formed on the side surfaces connected to the first and second surface surfaces.
[20] 請求項 19に記載の配線基板の接続方法であって、  [20] The wiring board connection method according to claim 19,
前記導電性領域の側面に凹溝が形成されており、  A concave groove is formed on a side surface of the conductive region,
前記第 1および第 2の工程は前記凹溝内に半田が流れ込むように接合領域を形成 する工程である配線基板の接続方法。 In the first and second steps, a joining region is formed so that solder flows into the concave groove. A method of connecting a wiring board, which is a process to perform.
[21] 請求項 18乃至 20のいずれか記載の配線基板の接続方法であって、  [21] The method for connecting wiring boards according to any one of claims 18 to 20,
前記第 1および第 2の配線基板の少なくとも一方は、硬質基板 (リジッド基板)である ことを特徴とする配線基板の接続方法。  At least one of the first and second wiring boards is a hard board (rigid board). A wiring board connection method, wherein:
[22] 請求項 18乃至 20の 、ずれか記載の配線基板の接続方法であって、 [22] The method for connecting wiring boards according to any one of claims 18 to 20, comprising:
前記第 1および第 2の配線基板の少なくとも一方は、フレキシブル基板であることを 特徴とする配線基板の接続方法。  A wiring board connection method, wherein at least one of the first and second wiring boards is a flexible board.
PCT/JP2007/050247 2006-01-13 2007-01-11 Inter-substrate bonding chip part, its manufacturing method, and wiring substrate connection method using the same WO2007080926A1 (en)

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JP2006006477A JP2007189098A (en) 2006-01-13 2006-01-13 Chip component for connecting between boards, manufacturing method therefor, and method for connecting wiring board using the same
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Citations (4)

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Publication number Priority date Publication date Assignee Title
JPH09246686A (en) * 1996-03-11 1997-09-19 Murata Mfg Co Ltd Connecting member and manufacture thereof
JPH10195597A (en) * 1996-11-14 1998-07-28 Sumitomo Metal Ind Ltd Thin steel sheet excellent in joinability
JPH10228244A (en) * 1997-02-14 1998-08-25 Citizen Electron Co Ltd Liquid crystal display device
JP2005149812A (en) * 2003-11-12 2005-06-09 Hokuriku Electric Ind Co Ltd Connector chip and its manufacturing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09246686A (en) * 1996-03-11 1997-09-19 Murata Mfg Co Ltd Connecting member and manufacture thereof
JPH10195597A (en) * 1996-11-14 1998-07-28 Sumitomo Metal Ind Ltd Thin steel sheet excellent in joinability
JPH10228244A (en) * 1997-02-14 1998-08-25 Citizen Electron Co Ltd Liquid crystal display device
JP2005149812A (en) * 2003-11-12 2005-06-09 Hokuriku Electric Ind Co Ltd Connector chip and its manufacturing method

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