WO2007058436A1 - Dispositif de memoire - Google Patents

Dispositif de memoire Download PDF

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Publication number
WO2007058436A1
WO2007058436A1 PCT/KR2006/004058 KR2006004058W WO2007058436A1 WO 2007058436 A1 WO2007058436 A1 WO 2007058436A1 KR 2006004058 W KR2006004058 W KR 2006004058W WO 2007058436 A1 WO2007058436 A1 WO 2007058436A1
Authority
WO
WIPO (PCT)
Prior art keywords
resin
memory device
recited
pvdf
ferroelectric layer
Prior art date
Application number
PCT/KR2006/004058
Other languages
English (en)
Inventor
Byung-Eun Park
Original Assignee
Iferro Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020060097901A external-priority patent/KR100966302B1/ko
Application filed by Iferro Co., Ltd. filed Critical Iferro Co., Ltd.
Publication of WO2007058436A1 publication Critical patent/WO2007058436A1/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only

Definitions

  • the present invention relates to a memory device, in and from which information data can be written and read electrically and, more particularly, to a memory device fabricated in a simplified structure excluding a storing element such as a capacitor and a switch element such as transistor and providing non-volatile storage and read of data .
  • ROMs such as electrically programmable read only memory (EPROM) , electrically erasable PROM (EEPROM) , flash ROM, etc.
  • RAMs such as static random access memory (SRAM), dynamic RAM (DRAM), ferroelectric RAM (FRAM), etc.
  • All semiconductor memory devices used at present include fundamentally a switching element such as transistor and a storing element such as capacitor. Such memory devices execute data writing, deleting and reading through operations of storing and reading data values in and from the storing element through the switching element.
  • the conventional memory devices have some drawbacks in that numerous manufacturing processes are required and it is difficult to materialize a high density over a predetermined level as the switching element and the capacitor should be arranged on a wafer.
  • an object of the present invention is to provide a memory device fabricated in a simply structure, not including separate switch element and capacitor, that provides non- volatile data storage and read.
  • Another object of ' the present invention is to provide a memory device that can be manufactured at a low manufacturing cost and materialize a high density of a high level .
  • a memory device in accordance with a first aspect of the present invention comprises: a substrate; a lower electrode established on the substrate and made of a conductive material; a ferroelectric layer provided on the lower electrode; and an upper electrode arranged on the ferroelectric layer and made of a conductive material.
  • a memory device in accordance with a second aspect of the present invention comprises: a substrate; a plurality of lower electrodes established in parallel with each other on the substrate; a ferroelectric layer provided on the lower electrodes; and a plurality of upper electrodes arranged in parallel with each other and in an orthogonal direction to the lower electrodes on the ferroelectric layer.
  • the lower and upper electrodes are made of conductive organic materials.
  • the ferroelectric layer is an organic material having a crystal structure of ⁇ -phase.
  • the ferroelectric layer is one selected from the group consisting of polyvinylidene fluoride (PVDF) , PVDF polymer, PVDF copolymer or PVDF terpolymer, odd-numbered nylon, cyano-polymer and their polymer or copolymer.
  • PVDF polyvinylidene fluoride
  • the substrate is formed with one selected from the group consisting of Si wafer, Ge wafer, paper coated with parylene and organic material.
  • the organic material includes at least one selected from the group consisting of polyimide (PI) , polycarbonate (PC) , polyethersulfone (PES) , polyetheretherketone (PEEK), polybutyleneterephthalate (PBT), polyethyleneterephthalate (PET) , polyvinylchloride (PVC) , polyethylene (PE) , ethylene copolymer, polypropylene (PP) , propylene copolymer, poly (4-methyl-l-pentene) (TPX) , polyarylate (PAR), polyacetal (POM), polyphenyleneoxide (PPO), polysulfone (PSF), polyphenylenesulfide (PPS), polyvinylidenechloride (PVDC) , polyvinylacetate (PVAC) , polyvinylalcohol (PVA) , polyvinylacetal (PVAL) , polystyrene (PS), AS resin, ABS resin, polymethylmethacrylate
  • Fig. 1 is a graph showing polarization characteristics of a PVDF thin film
  • Fig. 2 is a characteristic diagram depicting the changes of capacitance values of the PVDF thin film according to the lapse of time;
  • Fig. 3 is an equivalent circuit diagram of a memory device having a IT structure using a conventional ferroelectric-
  • Fig. 4 is an equivalent circuit diagram of a memory device having a 1C structure using a ferroelectric of the present invention
  • Fig. 5 illustrates a configuration of a memory device in accordance with a preferred embodiment of the present invention.
  • Fig. 6 illustrates a configuration of a memory device in accordance with another embodiment of the present invention.
  • the present inventor of the invention has disclosed non-volatile memory devices using organic materials such as polyvinylidene fluoride (PVDF) for example, in Korean Patent Application Nos. 10-2005-0039167 titled “Memory device using organic material and method of manufacturing the same” and 10-2005-0084571 titled “Ferroelectric memory device and method of manufacturing the same.”
  • PVDF polyvinylidene fluoride
  • the present inventor of the invention has shown that it is possible to materialize excellent nonvolatile memory devices having a IT structure, whereas, all existing memory devices have the 1T-1C (one transistor-one capacitor) structure.
  • Such patent applications are directed to non-volatile memory devices of the IT structure using polarization characteristics of an organic material, particularly, PVDF having a crystal structure of J3 -phase.
  • Fig. 1 is a graph showing polarization characteristics of PVDF having a crystal structure of ⁇ -phase that the present inventor has invented.
  • the PVDF having the polarization characteristics is formed in such a manner that, after forming a PVDF thin film having a thickness of 60nm via a spin-coating process below 3,000rpm and an annealing process above 120 ° C, the temperature of the PVDF thin film was monotonously lowered on a hot plate, and finally the PVDF thin film was cooled rapidly at 65 ° C, for example.
  • the PVDF thin film of J3 -phase has excellent hysteresis characteristics in that the capacitance value is decreased with the increase of the applied voltage in about 0 to IV, and the capacitance value is increased with the decrease of the applied voltage in about 0 to -IV.
  • Fig. 2 is a characteristic diagram depicting the changes of capacitance values of the PVDF thin film according to the lapse of time, from which it can be learned that the capacitance value of the PVDF thin film is not changed but maintained regularly according to the lapse of time.
  • the PVDF thin film has the following features.
  • the PVDF thin film shows a capacitance value over a specific value at OV. That is, the polarization value of the PVDF thin film is not changed but maintained at OV, where no voltages are applied from the outside. Second, the polarization value of the PVDF thin film is changed at a voltage below IV.
  • the PVDF thin film has a property in that the polarization value of the PVDF thin film is not changed but maintained according to the lapse of time.
  • the capacitance value that the PVDF thin film has, i.e., the polarization value is used as an electric data value
  • the PVDF thin film can be used as a material for a non-volatile memory device that operates at a lower voltage below IV.
  • the present inventor of the invention has proposed a non-volatile memory device of a IT structure using the PVDF thin film in Korean Patent Application No. 2005-0084571.
  • Fig. 3 is an equivalent circuit diagram of the memory device proposed in the above patent application.
  • the PVDF thin film i.e., the ferroelectric layer is used as a gate layer of a transistor 10 to maintain the on or off state of the transistor 10 based on the polarization value of the PVDF.
  • the data value is set at high or low level according to the on/off state of the transistor 10, it is possible to materialize an excellent non-volatile memory device with a simplified IT structure .
  • the corresponding configuration can be utilized as a memory device.
  • the PVDF thin film has a polarization value if a predetermined voltage is applied thereto, and it is possible to read such polarization easily to determine. Accordingly, it is possible to realize a memory device of a 1C structure (one- capacitor) as depicted in Fig. 4 using the polarization characteristics of the PVDF thin film.
  • a PVDF thin film is used as a ferroelectric layer 23 between a lower electrode 21 and an upper electrode 22 in the configuration depicted in Fig. 4.
  • a transistor In general, in case where a transistor is formed on a silicon substrate, etc., drain and source regions and a channel region are first established on the substrate, a gate layer is provided on the channel region, and electrodes are arranged on the drain and source regions and the gate layer. Accordingly, a lot of manufacturing processes are required.
  • the formation of the capacitor can be made with a simplified manufacturing process in that, after forming a dielectric layer on a lower electrode, an upper electrode is provided on the dielectric layer.
  • the capacitor structure has an occupied space smaller than that of the transistor structure, it is possible to arrange a large amount of elements in the same space. That is, the configuration of Fig. 4 can materialize a memory device of high capacity compared with that of Fig. 3.
  • a substrate such as silicon is unnecessary.
  • a substrate of special material is not required for materializing a memory device. Accordingly, it is possible to reduce the manufacturing cost of the memory device considerably and manufacture a memory device on a flexible material such as general resins or papers, thus realizing a memory device that can be folded or in the form of a roll.
  • Fig. 5 illustrates an exemplary example of the memory device depicted in Fig. 4.
  • a plurality of lower electrodes 51 and a plurality of upper electrodes 53 are arranged intersecting each other on a substrate 50, and a ferroelectric layer 52 having polarization characteristics is disposed between the intersections of the lower electrodes 51 and the upper electrodes 53.
  • the substrate 50 may be formed with organic materials including the existing Si wafer, Ge wafer, paper coated with parylene, flexible plastic, etc.
  • the available organic materials may include polyimide (PI) , polycarbonate (PC), polyethersulfone (PES), polyetheretherketone (PEEK), polybutyleneterephthalate (PBT) , polyethyleneterephthalate (PET), polyvinylchloride (PVC), polyethylene (PE), ethylene copolymer, polypropylene (PP), propylene copolymer, poly (4- methyl-1-pentene) (TPX) , polyarylate (PAR), polyacetal (POM), polyphenyleneoxide (PPO) , polysulfone (PSF) , polyphenylenesulfide (PPS) , polyvinylidenechloride (PVDC) , polyvinylacetate (PVAC) , polyvinylalcohol (PVA) , polyvinylacetal (PVAL) , polystyrene (PS) , AS resin, ABS resin, polymethylmethacrylate (PMMA) , fluorocarbon
  • the substrate 50 may be formed using any kinds of materials, not limited to specific ones.
  • the lower electrode 51 and the upper electrode 53 may be formed with conductive metals, metal oxides and conductive organic materials including aurum, argentum, aluminum, platinum, indium-tin oxide (ITO) , strontium titanate (SrTiOs) , other conductive metal oxides and their alloys and compounds, and mixtures, compounds or multilayer compounds, of which bases are conductive polymers, such as polyaniline, poly (3, 4-ethylenedioxythiophene) /polystyrenesulfonate (PEDOT: PSS), etc.
  • bases are conductive polymers, such as polyaniline, poly (3, 4-ethylenedioxythiophene) /polystyrenesulfonate (PEDOT: PSS), etc.
  • PVDF polyvinylidene fluoride
  • a drive device for driving the respective electrodes and a sense amplifier for reading the polarization values of the ferroelectric layer 53 are electrically coupled to the lower and upper electrodes 51 and 53 in the same manner as the general memory device .
  • Fig. 6a and ⁇ b illustrate another exemplary example of the memory device depicted in Fig. 4, in which Fig. 6a is a plane view and Fig. 6b is a cross-sectional view. In the embodiment depicted in Fig.
  • the ferroelectric layers 52 are formed in the region where the lower electrodes 51 and the upper electrode 53 intersect each other, whereas, in the present embodiment, a ferroelectric layer 62 is formed on the overall surface of the lower electrodes 61 extended in the horizontal direction, and a plurality of upper electrodes 63 extended in the vertical direction is established intersecting with the lower electrodes 61 on the top of the ferroelectric layer 62.
  • the lower electrodes 61 are formed on the substrate 60 and, then, the ferroelectric layer 62 is established on the overall surface of the lower electrodes 61, thus simplifying the manufacturing process.
  • the region where the lower electrode 61 and the upper electrode 63 intersect each other functions as a capacitor, the operation is substantially the same as the embodiment depicted in Fig. 5.
  • the materials of the substrate 60, lower and upper electrodes 61 and 63 and the ferroelectric layer 62 are substantially the same as the embodiment of Fig, 5, detailed description will be omitted.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)

Abstract

La présente invention a trait à un dispositif de mémoire fabriqué en une structure simplifiée excluant un élément de commutation et un élément de stockage et fournissant une mémoire non volatile et la lecture de données. Le dispositif de mémoire selon la présente invention comporte: un substrat; une pluralité d'électrodes disposées en parallèle les unes aux autres sur le substrat; une couche ferroélectrique disposée sur les électrodes inférieures; et une pluralité d'électrodes supérieures disposées en parallèle les unes aux autres dans une direction orthogonale aux électrodes inférieures sur la couche ferroélectrique.
PCT/KR2006/004058 2005-11-15 2006-10-10 Dispositif de memoire WO2007058436A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR20050109298 2005-11-15
KR10-2005-0109298 2005-11-15
KR10-2006-0097901 2006-10-09
KR1020060097901A KR100966302B1 (ko) 2005-11-15 2006-10-09 메모리 장치

Publications (1)

Publication Number Publication Date
WO2007058436A1 true WO2007058436A1 (fr) 2007-05-24

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PCT/KR2006/004058 WO2007058436A1 (fr) 2005-11-15 2006-10-10 Dispositif de memoire

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WO (1) WO2007058436A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002043071A1 (fr) * 2000-11-27 2002-05-30 Thin Film Electronics Asa Circuit de memoire ferroelectrique et son procede de fabrication
US6784017B2 (en) * 2002-08-12 2004-08-31 Precision Dynamics Corporation Method of creating a high performance organic semiconductor device
US20050077606A1 (en) * 2001-11-16 2005-04-14 Gunter Schmid Semiconductor arrangement comprising transistors based on organic semiconductors and non-volatile read-writing memory cells
US20050170543A1 (en) * 2001-12-26 2005-08-04 Tokyo Electron Limited Substrate treating method and production method for semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002043071A1 (fr) * 2000-11-27 2002-05-30 Thin Film Electronics Asa Circuit de memoire ferroelectrique et son procede de fabrication
US20050077606A1 (en) * 2001-11-16 2005-04-14 Gunter Schmid Semiconductor arrangement comprising transistors based on organic semiconductors and non-volatile read-writing memory cells
US20050170543A1 (en) * 2001-12-26 2005-08-04 Tokyo Electron Limited Substrate treating method and production method for semiconductor device
US6784017B2 (en) * 2002-08-12 2004-08-31 Precision Dynamics Corporation Method of creating a high performance organic semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"Mechanical and Electromechanical Properties of Vinylidene Fluoride Terpolymers", CHEM. MATER., vol. 16, 2004, pages 857 - 861 *

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