WO2007054886A2 - Convertisseur d'amplification pour correction de facteur de puissance - Google Patents

Convertisseur d'amplification pour correction de facteur de puissance Download PDF

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Publication number
WO2007054886A2
WO2007054886A2 PCT/IB2006/054135 IB2006054135W WO2007054886A2 WO 2007054886 A2 WO2007054886 A2 WO 2007054886A2 IB 2006054135 W IB2006054135 W IB 2006054135W WO 2007054886 A2 WO2007054886 A2 WO 2007054886A2
Authority
WO
WIPO (PCT)
Prior art keywords
signal
boost converter
demagnetization
boost
switching
Prior art date
Application number
PCT/IB2006/054135
Other languages
English (en)
Other versions
WO2007054886A3 (fr
Inventor
Johannes L. E. M. Lammers
Original Assignee
Bobinados De Transformadores S.L.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bobinados De Transformadores S.L. filed Critical Bobinados De Transformadores S.L.
Publication of WO2007054886A2 publication Critical patent/WO2007054886A2/fr
Publication of WO2007054886A3 publication Critical patent/WO2007054886A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to boost converters for power factor correction that are adapted for zero, or near zero, voltage switching.
  • SMPS non-linear switching-mode power supplies
  • a SMPS is arranged to "chop" an input signal, typically a rectified mains AC-signal, by switching the input signal on and off at high frequency.
  • SMPS 's are prone to cause substantial harmonic distortion to the line current, emit electromagnetic noise and have worse power factor than more traditional types of power supplies.
  • SMPS In order to reach higher power factors and to diminish harmonics, SMPS 's typically employ power factor correction (PFC).
  • PFC power factor correction
  • the PFC In order to diminish harmonics, the PFC typically is of so-called active type. To put it simple, the objective is to make the input current waveform to follow the input voltage waveform, i.e. to accomplish input impedance resembling that of a linear resistor.
  • PFC typically is considered, and accomplished, as a stand-alone circuitry, although the SMPS requirement of regulating an output voltage often is combined with the requirement of PFC.
  • SMPS SMPS
  • a rectifying stage typically followed by a PFC pre-regulator and a main regulator.
  • a power, or boost, switch 3 connected between ground and the node between the boost inductor and the boost diode.
  • the power switch typically comprises a field effect transistor (FET), such as a metal oxide semiconductor FET (MOSFET).
  • FET field effect transistor
  • the boost converter may be operated in either discontinuous or continuous mode.
  • discontinuous mode the boost transistor is switched ON after the current through the boost inductor has reduced to zero, and in continuous mode, the boost transistor is switched ON before the current has reached zero.
  • transition mode refers to the situation when the transistor is switched ON exactly when the current drops to zero.
  • control of the switch 3 is crucial.
  • PFC control there is available a number of PFC control ICs on the market, such as ST L6562, which can be configured and adapted for use in various applications, see for example the data sheet of ST L6562.
  • a known method to eliminate switching losses in converters of the above type is to arrange control of the power switch such that the switch is turned ON under, or near, zero voltage switching (ZVS) conditions.
  • ZVS zero voltage switching
  • the boost converter is operated in discontinuous mode.
  • the switching frequencies typically are high and varying.
  • the switching frequency will typically vary from approximately 30 kHz up to 400 kHz. This is a problem since electromagnetic compatibility (EMC) related regulations and legislation typically requires that electromagnetic interference (EMI) above 150 kHz must stay below certain limits.
  • EMC electromagnetic compatibility
  • EMI electromagnetic interference
  • using a ZVS boost converter involves costs related to filtering and/or shielding in order to decrease EMI in the span 150-400 kHz.
  • a specific object is to provide a zero voltage switched boost converter for power factor correction that can comply with EMC requirements at lower cost.
  • a more general object is to provide a cost efficient zero voltage switched boost converter for power factor correction.
  • a zero voltage switching boost converter for power factor correction comprising a boost inductor, a switching transistor and a control circuitry arranged to control the switching transistor based on a demagnetization signal proportional to a current in the boost inductor.
  • the converter further comprises a signal alteration circuitry arranged to add a high frequency, small amplitude signal to said demagnetization signal, thereby forming an altered demagnetization signal.
  • a “demagnetization signal” is a signal proportional to the decrease of current stored in the boost inductor.
  • the demagnetization signal is typically accomplished by coupling an additional winding to the boost inductor so as to accomplish a step-down transformer producing the demagnetization signal in the additional winding.
  • a "high frequency, small amplitude signal” is in relation to the switching frequency and the amplitude of the demagnetization signal.
  • high frequency typically is a frequency higher than twice the switching frequency, and a small amplitude typically is less than half of the demagnetization signal peak amplitude.
  • the invention is based on the understanding, that when a PFC boost converter is arranged for zero voltage switching (ZVS) using a power factor correction (PFC) control circuitry, which utilizes a demagnetization signal with respect to the boost inductor, the high frequency content may be reduced by adding a high frequency, small amplitude signal to the demagnetization signal.
  • ZVS zero voltage switching
  • PFC power factor correction
  • the altered demagnetization signal has impact during switch OFF conditions and affects when the switch turns ON. Instead of switching ON when the drain voltage of the switch transistor reaches zero voltage, as in conventional ZVS, i.e. when the drain voltage reaches a first minimum, or valley, the drain voltage will oscillate and switch ON will occur at a later minimum, or valley. That is, so called multiple valley switching is accomplished. Which minimum, or valley, resulting in the switch ON, is determined by the high frequency, small amplitude signal?
  • the OFF time is prolonged, and frequency lowered.
  • the length of the switch OFF time can be set so as to accomplish switching frequencies that do not exceed a predetermined value, such as 150 KHz, which make it easier and cheaper to comply with EMC regulations.
  • the high frequency, small amplitude signal may be is a sinusoidal ringing.
  • the control circuitry may comprise a power factor correction control integrated circuit, wherein the signal alteration circuitry may be arranged to provide the altered demagnetization signal to a demagnetization pin of the integrated circuit.
  • One advantage from using such an IC is the cost efficiency obtained by being able to use commercially available, mass produced PFC control ICs.
  • such ICs need to be utilizing a demagnetization signal, as is the case of, for example, ST L6562 and similar circuits.
  • the high frequency, small amplitude signal may have a fixed, predetermined frequency.
  • a predetermined frequency which results in a predetermined decrease of the switching frequency.
  • This also allows for simple and cheap circuitry in order to form the high frequency, small amplitude signal alteration circuitry. For example, one might start with a conventional ZVS boost converter having a maximum switching frequency that is desired to be decreased and then predetermine the frequency of the high frequency, small amplitude signal such that the maximum frequency is lowered to a desired value.
  • the signal alteration circuitry may comprise a bipolar transistor having the base connected to the demagnetization signal.
  • a bipolar transistor coupled like this, forms the base for a simple, and thus cheap, circuitry that may accomplish the high frequency, small amplitude signal.
  • the high frequency, small amplitude signal may be adapted to prolong the length of the switching transistor's switch OFF time such that the maximum switching frequency occurs at, or near, a frequency limit set by electromagnetic compatibility regulations, such as 150 kHz. It may be noted that the energy of the ringing frequency is less compared with the frequency of the on and off time of the switching transistor.
  • the boost converter may be used as a pre-regulator in a switched mode power supply.
  • Fig. 1 shows a boost converter topology according to the prior art.
  • Fig. 2 shows a boost converter with control circuitry according to an embodiment.
  • Fig. 3a schematically depicts a boost inductor current and a power switch transistor drain voltage during a switching period of a conventional boost converter.
  • Fig. 3b schematically depicts a boost inductor current and a power switch transistor drain voltage during a switching period of a boost converter according to an embodiment of the invention.
  • Fig. 2 shows a boost converter for PFC having control circuitry blocks 120, 140, 160 according to an embodiment of the invention.
  • the boost converter further comprises a boost inductor 101, a power switch 103, here comprising a MOSFET, a boost diode 105 and a smoothing, or buffer, capacitor 107.
  • the power switch 103 may be controlled by a switch control block 120, which controls the switch using a signal provided by a demagnetizing signal block 140 via a signal alteration block 160.
  • the demagnetizing signal block 140 may be arranged to produce a demagnetization signal that is proportional to the current flowing in the boost inductor 101.
  • the signal alteration block 160 may be arranged to add a high frequency, small amplitude signal to the demagnetization signal before it is delivered to the switch control block 120.
  • the high frequency, small amplitude signal is a sinusoidal ringing.
  • the switch control block 120 may comprise a PFC control integrated circuit (IC) 122 that is substantially adapted for ZVS and furnished with a demagnetization signal input 124, or pin, which receives the altered demagnetization signal from the signal alteration block 160.
  • IC PFC control integrated circuit
  • the PFC control IC 122 is a ST L6562. It should be noted that other PFC control ICs having a demagnetization pin or similar may be used instead.
  • a demagnetization pin, or signal is utilized by the ST L6562, and many similar PFC control ICs, in order to monitor the boost inductor's demagnetization during switch OFF, i.e. to monitor decrease of energy that was stored in the inductor during switch ON, and use this information in the control of the switch.
  • the demagnetization pin is named zero current detection (ZCD) since it is used to sense when the current in the boost inductor drops to zero. Still referring to Fig.
  • the demagnetizing signal block 140 comprises an additional winding 142 across the boost inductor 101, i.e. a transformer is formed.
  • the additional winding 142 may have the same polarity as the boost inductor 101. Since the current flowing in the boost inductor 101 typically is high, the additional winding 142 is arranged so as to accomplish a step-down transformer, providing a comparatively small amplitude demagnetization signal.
  • the signal alternation block 160 is exemplified by a minimal circuit implementation that generates and adds, or superimposes, a small amplitude, high frequency ringing to the demagnetization signal.
  • the signal alternation block 160 may comprise a bipolar transistor 166, resistors 168, 170, 164 and a capacitor 162.
  • the bipolar transistor 166 may have its emitter connected to the demagnetization signal via resistor 168.
  • the bipolar transistor may be the common BC857B
  • the resistor 164 may be 1 kOhm
  • the resistor 168 may be 100 kOhm
  • the resistor 170 may be 10 kOhm
  • the capacitor 162 may be 33 pF. It is clear for those skilled in the art that there exists a number of alternative techniques so as to accomplish and superimpose a high frequency, small amplitude signal to another signal, which may be used to replace the exemplifying circuitry in block 160.
  • the switch control block 120 comprises a PFC control IC 122 having a demagnetization input 124 and a gate drive output 126.
  • the demagnetization input corresponds to the ZCD pin and the gate drive output corresponds to the GD pin.
  • the exemplifying circuitry shown in the switch control block 120 of Fig. 2 further comprises components 130, 132, 134, 136 arranged for affecting the length of the switch OFF time in a conventional manner.
  • the arrangement, and the values, of these components may be in accordance with any known method for accomplishing a constant, fixed OFF time length for a conventional ZVS boost converter.
  • a typical PFC control circuit 122 that is arranged for a ZVS boost converter, may not only be requiring circuitry for providing a demagnetization signal, i.e. information on the boost inductor current, but also circuitry providing information on the output voltage, information on the input voltage and information on the switch transistor current.
  • Fig. 3a schematically depicts a boost inductor current and a drain voltage of a power switch's MOSFET, during a switching period of a conventional ZVS boost converter for PFC.
  • a conventional converter may for example be achieved by connecting the circuitry in block 140 of Fig. 2b, directly to the circuitry in block 120 of Fig. 2b, i.e. without adding the high frequency, small amplitude signal to the demagnetization signal.
  • the power switch is ON, the boost diode 105 is reverse biased and an input voltage is applied across the boost inductor 101, whereby current builds up from zero (discontinuous mode) in the boost inductor 101, and reaches a peak value at tl, where the power switch is turned OFF.
  • the switch control block 120 typically by the PFC IC 122.
  • the switch 103 turns OFF, the voltage over the boost inductor 101 will reverse, and the boost diode will start to conduct energy stored in the boost inductor 101, plus any energy direct from the input, to the smoothing capacitor 107 and a load (not shown).
  • This transfer of energy from, or demagnetization of, the boost inductor is illustrated by the decreasing slope between tl and t2 in Fig. 3 a.
  • the switch control block is arranged for constant OFF-time control, resulting in a constant time period between tl and t2.
  • control block 120 is arranged not to turn the switch ON again until the drain voltage has reached zero, or at least a minimum, i.e. there will be an additional OFF time between t2 and t3.
  • Fig. 3b schematically depicts corresponding waveforms as in Fig. 3a but for a boost converter such as in Fig. 2.
  • an altered demagnetization signal which has been altered by adding a high frequency, small amplitude ringing, is being used.
  • the altered demagnetization signal is used as input to a switch control block 120 instead for the demagnetization signal.
  • the waveforms of Fig. 3a and 3b, and the operation of the boost converters producing these waveforms are substantially the same.
  • the altered demagnetization signal has impact on the length of the switch OFF time.
  • a high frequency oscillation can be seen between t2' and t5' for the inductor current and the drain voltage. It may be noted that this small ripple in the inductor current has a negligible effect on the demagnetization signal and, thus, there is no self-sustained loop effect, or instability due to feedback.
  • switching ON when the drain voltage reaches zero, or at the first minimum as in the example of Fig.
  • the switch ON here occur at a later minimum, or valley. In the example of Fig. 3b this happens at the second minimum at t5'. However, generally, which minimum, or valley, at which switch ON occurs, depends on the ringing signal. Hence, so called multiple valley switching is accomplished and the switch
  • the switch ON occurs at a minimum that is not zero voltage.
  • it is not zero voltage switching, but since the switching occurs at a minimum, it is still within a common, wider definition of ZVS comprising low voltage switching as well.
  • many conventional ZVS designs are in practice not switching at precisely zero voltage, but instead at, or near, a minimum.
  • the switching losses typically is higher compared to an exact zero case, but will still only be a small part of the total losses in the switch.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

L'invention concerne un convertisseur d'amplification à commutation à tension nulle en vue d'une correction de facteur de puissance. Le convertisseur d'amplification comprend une bobine d'inductance d'amplification (101), un transistor de commutation (103) et des circuits de commande (120) agencés pour commander le transistor de commutation sur la base d'un signal de démagnétisation proportionnel à un courant dans la bobine inductance d'amplification (101). Il existe des circuits de modification de signal (160) agencés pour ajouter un signal à haute fréquence, de faible amplitude au dit signal de démagnétisation, ce qui forme un signal de démagnétisation modifié. Il en résulte qu'une commutation multiple sur des creux d'oscillation est réalisée et que le contenu à haute fréquence est réduit ce qui rend possible de satisfaire aux exigences de la compatibilité électromagnétique à faible coût.
PCT/IB2006/054135 2005-11-11 2006-11-07 Convertisseur d'amplification pour correction de facteur de puissance WO2007054886A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05110633.4 2005-11-11
EP05110633 2005-11-11

Publications (2)

Publication Number Publication Date
WO2007054886A2 true WO2007054886A2 (fr) 2007-05-18
WO2007054886A3 WO2007054886A3 (fr) 2007-09-13

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PCT/IB2006/054135 WO2007054886A2 (fr) 2005-11-11 2006-11-07 Convertisseur d'amplification pour correction de facteur de puissance

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TW (1) TW200727106A (fr)
WO (1) WO2007054886A2 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112010004816B4 (de) 2009-12-15 2021-11-11 Tridonic Uk Ltd. PFC mit verringerten Pinanzahlanforderungen für einen Steuer-/Regel-IC
CN115441702A (zh) * 2022-11-08 2022-12-06 成都智融微电子有限公司 一种应用于反激式电源电路的自适应屏蔽时间生成系统

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI382291B (zh) * 2008-11-10 2013-01-11 Apollo Energy Technology Co Ltd 多模式功率因素修正器之控制方法與裝置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001057999A1 (fr) * 2000-02-04 2001-08-09 Koninklijke Philips Electronics N.V. Circuit de conversion continu-continu
US6341073B1 (en) * 2000-11-16 2002-01-22 Philips Electronics North America Corporation Multiple valley controller for switching circuit
US20050078493A1 (en) * 2003-09-08 2005-04-14 Jung-Won Kim Switching power supply device and method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001057999A1 (fr) * 2000-02-04 2001-08-09 Koninklijke Philips Electronics N.V. Circuit de conversion continu-continu
US6341073B1 (en) * 2000-11-16 2002-01-22 Philips Electronics North America Corporation Multiple valley controller for switching circuit
US20050078493A1 (en) * 2003-09-08 2005-04-14 Jung-Won Kim Switching power supply device and method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
VARIOUS AUTHORS: "L6563 - L6563A - Advanced transition-mode PFC controller" INTERNET CITATION, [Online] 13 November 2004 (2004-11-13), XP002422562 Retrieved from the Internet: URL:http://www.alldatasheet.com/datasheet- pdf/pdf/158050/STMICROELECTRONI CS/L6563.html?> [retrieved on 2007-02-28] *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112010004816B4 (de) 2009-12-15 2021-11-11 Tridonic Uk Ltd. PFC mit verringerten Pinanzahlanforderungen für einen Steuer-/Regel-IC
CN115441702A (zh) * 2022-11-08 2022-12-06 成都智融微电子有限公司 一种应用于反激式电源电路的自适应屏蔽时间生成系统
CN115441702B (zh) * 2022-11-08 2023-02-17 成都智融微电子有限公司 一种应用于反激式电源电路的自适应屏蔽时间生成系统

Also Published As

Publication number Publication date
TW200727106A (en) 2007-07-16
WO2007054886A3 (fr) 2007-09-13

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