WO2007036201A1

WO2007036201A1 - Method for the production of an electrical component having little tolerance

Info

Publication number: WO2007036201A1
Application number: PCT/DE2006/001660
Authority: WO
Inventors: Javier Arrimadas Matias; Gerald Kloiber; Werner Krauss
Original assignee: Epcos Ag
Priority date: 2005-09-27
Filing date: 2006-09-20
Publication date: 2007-04-05
Also published as: JP2009510740A; DE102005046191A1; EP1929485A1; EP1929485B1

Abstract

Disclosed is a method for producing an electrical component having a predefined setpoint resistance. First, a base plate (1) is provided which comprises a substrate (100') and two large-area electrodes (211, 221) that are arranged on the main surfaces of the substrate. The size of the base plate (1) in lateral directions (x, y) amounts to a multiple of the respective size (Lx, Ly) of a zone (11 - MN) of the component. The actual resistance of the intermediate substrate zone located between the large-area electrodes (211, 221) is measured. A covering area of a zone (11 - MN) of the component required for obtaining the setpoint resistance is calculated based on said measurement. The zone of the component that has the calculated covering area is cut out of the base plate (1) in order to produce the component. The tolerance error resulting from the substrate thickness that may be different from the setpoint value can be compensated by adjusting the surface of the zone of the component at the actual substrate thickness.

Description

description

Method for producing an electrical component with a low tolerance

A method for producing an electrical component is described.

From the document DE 10020224 A1 a method for the production of NTC components with a given specific resistance is known. NTC stands for "Negative Temperature Coefficient".

An object to be solved is to provide a method for producing an electrical component with low tolerances.

The component may in particular be a resistance component. In the device is at least one functional unit such. As an NTC resistor, a PTC thermistor or a varistor realized. The component comprises a base body with at least two electrodes. The main body is preferably a sintered ceramic body. The basic body of the component is produced starting from a substrate which is singulated to form a plurality of basic bodies.

The actual parameters (in particular the specific resistance and the thickness) of the substrate, which later forms the basic body of a component to be produced, can each differ, for production reasons, from a corresponding predetermined value, which was calculated for the electrical size of the component to be achieved. As a result, the actual value of the electrical size of the construction elements deviates from the specified setpoint. To account for these manufacturing variations, the area of a device region may be adjusted at the actual parameters of the substrate to achieve the electrical size setpoint. For example, with an actual substrate thickness that is higher relative to the nominal value of the substrate thickness, the area of the component regions may be smaller than the corresponding nominal value of the surface and vice versa, the area of the component regions may be selected to be larger given a smaller substrate thickness relative to the nominal value of the substrate thickness. Due to the adaptation of the area of the component regions, in spite of the manufacturing error during the production of the substrate, essentially the nominal value of the volume relevant for the achievement of the desired value can be achieved.

It is a method for producing an electrical component having a predetermined setpoint of an electrical variable, for. B. specified a desired resistance value. First, a base plate is provided which has a substrate, a first large-area electrode and a second large-area electrode. The large-area electrodes are arranged on main surfaces, ie on the base and top surfaces of the substrate. The dimension of the base plate is in two mutually perpendicular lateral directions a multiple of the corresponding dimension of a provided device region. Between the large-area electrodes of the actual value of the electrical size of the interposed substrate region -. B. its actual resistance - measured. On the basis of this measurement, a cover area of a component area necessary to achieve the SOI resistance value is calculated. The base plate is singulated, wherein cut out for the preparation of the device from the base plate of the component area with the calculated top surface becomes .

The baseplate is preferably divided into a two-dimensional arrangement of similar component regions with the calculated top surface and singulated according to this division into separate component regions. By adapting the surface of the component region in the production-related actual thickness of the substrate, for example, it is possible to compensate for the tolerance error by a substrate thickness deviating from the ideal value.

The specified method is intended in particular for producing an SMD-capable resistor element.

The separated component region forms a basic body provided with electrodes of the component to be produced. After the separation of the base plate, a first or a second electrode of the component is formed from the large-area first and second electrodes.

The base plate is made by sintering a large-area substrate, for. Ceramic substrates, and metallizing this substrate to form the large area electrodes. In a preferred variant, a first metallization layer is formed on the upper side of the substrate to form the first large-area electrode, and a second metallization layer is formed on the lower side of this substrate to form the second large-area electrode. These layers are z. B. applied as a metal paste on the main surfaces of the substrate and baked. These layers can preferably be plated by electroplating or by sputtering to form a barrier layer before or after singulation of the baseplate. The nickel-plated electrodes can be used in one tinned advantageous variant for forming a solderable layer.

In principle, a barrier layer suitable as a diffusion barrier or a layer sequence comprising a solderable layer and a barrier layer can be produced on the respective electrode. The solderable layer preferably contains tin or a tin alloy. The barrier layer is arranged between the solderable layer and the corresponding electrode. The barrier layer is preferably a nickel-containing layer, the z. B. forms a Ni / Sn barrier. The arranged on the opposite faces of the body metallization layers (on each side of the electrode, the barrier layer and the solderable layer) form electrical connections of the device.

The application of the barrier layer and, if necessary, also the solderable layer is preferably carried out before the measurement. But they can also be applied only after the measurement.

On the preferably nickel-plated electrodes supporting first and second end faces of the body and on the frontal region of its lateral surface is in a variant, a first or a second outer electrode z. B. applied by dipping in a metal paste. In this case, the region of the first and the second outer electrode arranged on the lateral surface or on the underside of the main body respectively forms a contact of the component suitable for surface mounting.

For the outer electrodes, a material containing a noble metal, in particular silver or a silver alloy, may be used be used. The outer electrode may also contain a solderable material or, preferably, as the outer layer, a solderable layer. The outer electrode can be tinned in particular.

An electrically insulating passivation layer can be applied to the outer surface of the main body before the outer electrodes are applied. To produce the passivation layer z. B. a glass slip can be used. Other electrically insulating materials are also suitable for the passivation layer. The outer electrodes are preferably applied in such a way that at least a portion of the respective outer electrode lies on the passivation layer.

In a preferred variant, the outer electrodes each form an end cap, wherein the side wall of this cap lies on the passivation layer and is held by the layer at a distance from the main body or electrically insulated from it. The connection cap thus has areas arranged on the lateral surface of the component. Since the parts of the cap arranged on the lateral surface of the component are electrically insulated from the main body by the passivation, they have no influence on the resistance of the component. The use of the passivation layer thus has the advantage that the tolerances associated with the application of the connection cap can essentially be excluded.

In one variant, the glass slip is first baked and only then the outer electrodes are applied and baked. But it is also possible, after the application of the glass slip and the outer electrodes together in one Step in to burn.

In the following, the specified method will be explained with reference to schematic and not to scale figures. Show it:

FIG. 1 shows the base plate to be singulated in component regions in cross section;

FIG. 2 shows the division of the base plate according to FIG. 1 into component regions;

3 shows a component with frontally arranged SMD contacts;

FIG. 4 shows a component with a passivation layer which separates the parts of external electrodes arranged on the lateral surface from the main body of the component.

FIG. 1 shows the cross section of a base plate 1, which has a substrate 100 '. As substrate 100 'can z. B. a ceramic plate can be used. On the upper side of the substrate, a first large-area electrode 211 'and on its underside a second large-area electrode 221' is arranged. The large-area electrodes 211 ', 221' are z. B. silver-containing metal layers. To form these layers, a metal paste is applied to the substrate 100 'and preferably baked.

Figure 2 shows a plan view of the base plate 1 from above. With the dot-dash lines (dividing lines), the division of the base plate into component regions 11, 12, 13,. IN; 21, ...; 31, ...; Ml, M2, M3 ... MN indicated. The base plate 1 is z along these lines. B. isolated by sawing.

The two-dimensional arrangement of device regions 11... MN forms a matrix of dimension M × N with M rows and N columns, where N> _ 2 and M j> 2. The base plate is therefore a large-area plate whose lateral dimensions are many times larger the lateral dimensions Lx, Ly amount to a provided device area. With x and y are lateral directions and z denotes a vertical direction. The main surfaces of the base plate preferably comprise the end faces of the component regions to be separated. The thickness of the base plate 1 essentially defines the length of the component to be produced. The z-direction thickness of the substrate 100 'and the area Lx x Ly of a device region define the actual resistance of the device.

Before the separation of the base plate 1, the resistance of the substrate region disposed between the first and second large-area electrodes 211 ', 221' is measured at the actual substrate thickness. With the given dimensions of the large-area electrodes 211 ', 221', the measured resistance value allows to deduce the resistivity of the substrate material. If the actual resistivity of the substrate material determined from this measurement or the actual substrate thickness deviates from the corresponding ideal value, the area of a component area can be adjusted in such a way that the resistance of the component to be set is achieved.

FIG. 3 shows a separated component region or component. The main body 100 of the device was produced from the substrate 100 '. The first electrode layer 211 was formed from the first large-area electrode 211 'and the second electrode layer 221 of the device was generated from the first large-area electrode 221'.

A barrier layer 212, 222 was applied to the electrode layer 211, 221, and a solderable layer 213, 223 was applied to the latter, preferably galvanically or by sputtering. As a material for the layers 211, 221 is in particular silver, AgPd, Au, Al, Cu or Cr into consideration. The barrier layers 212, 222 are z. B. nickel-containing layers and the solderable layers 213, 223 tin-containing layers. The surface mount suitable electrical terminals 210, 220 of the device are arranged in this variant on the end sides of the body and each formed by the layer sequence 211, 212, 213 and 221, 222, 223.

The barrier layer 212, 222 can be applied after the measurement on the two main surfaces of the base plate 1 galvanically or by sputtering. However, it can also be applied to the electrodes 211, 211 only after the separation of component areas. This also applies to the solderable layer 213, 223.

FIG. 4 shows a component with SMD contacts 51, 52 arranged on its underside. Also in this variant, the electrodes 211, 221 are arranged on the end faces of the basic body 100. A glass slip is preferably applied to the lateral surface of the main body 100 of a separated component region in order to produce a passivation layer 30 in a spraying process. Instead of the solderable layer 213, 223, an outer electrode 41, 42 is used in the variant according to FIG.

The outer electrodes 41, 42 are preferably formed from a silver-containing and / or solderable material. Each outer electrode can also be several layers, for. As an Ag layer and a Ni / Sn layer. These layers are each, for example, by dipping the respective end face of the body in a metal paste or galvanized.

The outer electrodes 41, 42 each form an end-side metal cap, wherein the side wall of this cap lies on the passivation layer 30 and is kept at a distance from the base body 100 by this layer or electrically insulated from it. The arranged on the underside of the body 100 areas of the outer electrodes 41, 42 form SMD contacts of the device.

The outer electrodes 41, 42 are generated after the application of the passivation layer 30. It is possible first to burn in the passivation layer 30, then to produce outer electrodes 41, 42 on the base body provided with the passivation layer, to apply at least one metal layer on the face side and burn it. However, it is also possible to successively apply the passivation layer 30 and the metal layer provided for the formation of the outer electrode 41, 42, and to bake both layers together.

In order to keep the electrodes 211, 221 of the component regions free of the passivation layer 30, a preferably organic protective lacquer may be applied to these electrodes after the measurement and before the application of the passivation layer 30. which chars in the course of the burn-in of the passivation layer 30. The protective lacquer can be applied over a large area to the two main surfaces of the base plate 1. But it can also be applied to the separation of component areas on the end faces.

In a variant of the method, the large-area electrodes 211 'and 221' can be removed after the measurement. This can be done before or after the singulation of the substrate, before or after the application and / or burning of the passivation layer 30 z. B. done in a chemical etching process. The outer electrodes 41, 42 can then be applied after the application of the passivation layer 30 to the metal-free end sides of the component in this case and the end-side regions of the passivation layer 30. The baking of the passivation layer 30 and the outer electrodes 41, 42 can, as already explained, take place in succession or in a baking step.

LIST OF REFERENCE NUMBERS

1 base plate

100 'substrate

100 main body jl ... jN arranged in j-th row device areas

Ml ... MN arranged in M-th row device areas

Ik ... Mk arranged in k-th column device areas

210, 220 electrical connections of the component 211 'first large-area electrode

221 'second large-area electrode

211, 221 first and second electrode, respectively

212, 222 barrier layer

213, 223 solderable electrode layer 30 passivation layer

41 first outer electrode

42 second outer electrode

51, 52 formed by regions of the outer electrodes 41, 42

SMD contacts

Dimension of a component area in x-direction Ly dimension of a component area in y-direction x first lateral direction y second lateral direction z vertical direction

Claims

claims

A method of manufacturing an electrical device having a predetermined desired value of an electrical parameter, comprising the following steps: a) providing a base plate (1) comprising a substrate (100 ') _/ a first large area electrode (211') and a second large-area electrode (221 '), the large-area electrodes (211', 221 ') being arranged on the main surface of the substrate (100'), the lateral dimensions of the base plate (1) being a multiple of the lateral dimensions (Lx, Ly ) of a device region (11 - MN); b) measuring an actual value of the electrical parameter between the first large-area electrode (211 ') and the second large-area electrode (221') and calculating the surface area of a component area (11) associated with the component to be manufactured in order to achieve the desired value of the electrical parameter - MN); c) separating the base plate (1), wherein for the production of the component, the component region (11 - MN) is cut out of the base plate (1).

2. The method of claim 1, wherein the two-dimensional array of device regions (11 - MN) forms a matrix of dimension M x N, where N ^ 2 and M> _ 2.

3. The method of claim 1 or 2, wherein for forming the first large-area electrode (211 '), a first metallization layer on the upper side of the substrate (100') and the formation of the second large-area elec- trode (221 ') a second metallization on the Bottom of this substrate is generated.

4. The method according to any one of claims 1 to 3, wherein a ceramic plate is used as the substrate (100 ').

5. The method according to any one of claims 1 to 4, wherein the set electrical parameter is a resistor.

6. The method according to any one of claims 3 to 5, wherein for the production of the large-area electrodes (211 ', 221'), a material is used which contains Ag, Au, Al, Cu or Cr.

7. The method according to any one of claims 3 to 6, wherein when separating the base plate (1) this breaks down into component regions (11 - MN), each having a base body (100) arranged on its two end faces E- electrodes (211, 221) exhibit.

8. The method of claim 7, wherein on the respective electrode (211, 221), a layer sequence is generated, which comprises a solderable layer (213, 223) and a barrier barrier suitable as a barrier layer (212, 222), which between the solderable layer (213, 223) and the electrode (211, 221) is arranged.

9. The method of claim 8, wherein the barrier layer contains Ni.

10. The method according to claim 7,

- Wherein on the first electrode (211) carrying the first end face of the base body (100) and on the frontal region of its lateral surface, a first outer electrode (41) is applied,

- Wherein on the second electrode (221) carrying the first end face of the base body (100) and on the frontal region of its lateral surface, a second outer electrode (42) is applied.

11. The method of claim 10, wherein an electrically insulating passivation layer (30) is applied to the lateral surface of the base body.

12. The method according to claim 11, wherein a glass slip is used to produce the passivation layer (30).

13. The method of claim 11 or 12, wherein the outer electrodes (41, 42) are applied such that at least a portion of the respective outer electrode lies on the passivation layer (30).

14. The method according to any one of claims 1 to 13, wherein for the outer electrodes (41, 42), a silver-containing material is used.

15. The method of claim 12, wherein the glass slip is baked, and then the outer electrodes (41, 42) are applied and baked.

16. The method of claim 12, wherein the glass slip and the outer electrodes (41, 42) are applied and baked together in one step.

17. The method according to any one of claims 11 to 16, wherein after the measurement and before the application of the passivation layer (30), a protective varnish is applied to the electrodes (211, 221) and charred in the course of the burn-in of the passivation layer (30).

18. The method of claim 17, wherein the protective lacquer is applied over a large area, on the two main surfaces of the base plate 1 or after the separation of component areas on the end faces thereof.

19. The method according to any one of claims 1 to 18, which is carried out for the production of an NTC device.

20. The method of claim 1, wherein step c) comprises the following sub-steps: cl) the division of at least one region of the base plate (1) into a two-dimensional arrangement of component regions each having the calculated top surface, and c2) separating the base plate (1 ) in separate component areas according to this division.