WO2007030368A2 - Structures semi-conductrices en desaccord de maille sur des isolants et procedes correspondants - Google Patents

Structures semi-conductrices en desaccord de maille sur des isolants et procedes correspondants Download PDF

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Publication number
WO2007030368A2
WO2007030368A2 PCT/US2006/033859 US2006033859W WO2007030368A2 WO 2007030368 A2 WO2007030368 A2 WO 2007030368A2 US 2006033859 W US2006033859 W US 2006033859W WO 2007030368 A2 WO2007030368 A2 WO 2007030368A2
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Prior art keywords
active
area
region
substrate
insulator layer
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PCT/US2006/033859
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WO2007030368A3 (fr
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Matthew T. Currie
Anthony J. Lochtefeld
Zhiyuan Cheng
Thomas A. Langdo
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Amberwave Systems Corporation
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Priority claimed from US11/220,482 external-priority patent/US7638842B2/en
Priority claimed from US11/221,064 external-priority patent/US20070054467A1/en
Application filed by Amberwave Systems Corporation filed Critical Amberwave Systems Corporation
Publication of WO2007030368A2 publication Critical patent/WO2007030368A2/fr
Publication of WO2007030368A3 publication Critical patent/WO2007030368A3/fr

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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Definitions

  • This invention relates generally to lattice-mismatched semiconductor heterostructures and, specifically, to methods and materials for formation of integrated structures including alternative active-area materials on insulators.
  • NI-V materials such as gallium arsenide, gallium nitride, indium aluminum arsenide, and/or germanium with silicon, silicon-on- insulator, or silicon-germanium substrates
  • NI-V materials such as gallium arsenide, gallium nitride, indium aluminum arsenide, and/or germanium with silicon, silicon-on- insulator, or silicon-germanium substrates
  • alternative active- area materials having a low density of dislocation defects onto an insulator platform.
  • alternative materials refers to either a non-silicon semiconductor, or silicon with a different surface or rotational orientation compared to the underlying substrate. Such areas are suitable for use as active areas for MOSFETs or other electronic or opto-electronic devices.
  • Heterointegration of alternative materials has thus far been typically limited to the addition of SiGe alloys of small Ge content for use as source-drain contact materials or heteroj unction bipolar transistor base layers.
  • heteroepitaxial growth can be used to fabricate many modern semiconductor devices where lattice-matched substrates are not commercially available or to potentially achieve monolithic integration with silicon microelectronics. Performance and, ultimately, the utility of devices fabricated using a combination of dissimilar semiconductor materials, however, depends on the quality of the resulting structure. Specifically, a low level of dislocation defects is important in a wide variety of semiconductor devices and processes, because dislocation defects partition an otherwise monolithic crystal structure and introduce unwanted and abrupt changes in electrical and optical properties. These, in turn, result in poor material quality and limited performance. In addition, the threading dislocation segments can degrade physical properties of the device material and can lead to a premature device failure.
  • dislocation defects typically arise in efforts to epitaxially grow one kind of crystalline material on a substrate of a different kind of material — often referred to as a "heterostructure" - due to different crystalline lattice sizes of the two materials. This lattice mismatch between the starting substrate and subsequent layer(s) creates stress during material deposition that generates dislocation defects in the semiconductor structure.
  • the stress field associated with misfit dislocations under certain conditions may cause formation of linear agglomerations of threading dislocations, termed a "dislocation pile-up.”
  • This is generally defined as an area comprising at least three threading dislocations, with a threading dislocation density greater than 5x10 6 cm '2 , and with threading dislocations substantially aligned along a slip direction such that the linear density of dislocations within the pile-up and along a slip direction is greater than 2000/cm.
  • the slip directions in SiGe materials are in-plane ⁇ 110> directions.
  • a high localized threading dislocation density present in dislocation pile-ups has a potentially devastating impact on the yield of devices formed in these regions and may render these devices unusable. Inhibiting the formation of dislocation pile-ups is, therefore, desirable.
  • heterointegration of alternative materials is desirable for various electronic and optoelectronic applications.
  • the heterointegration of IN-V, M-Vl materials and/or Ge with Si is an attractive path for increasing the functionality and performance of the CMOS platform.
  • An economical solution to heterointegration could enable new fields and applications, such as replacing Si in CMOS transistors, particularly for critical-path logic devices.
  • Heterointegration could significantly lower (a) channel resistance, due to the ultra-high mobility and saturation velocity afforded by various non-Si semiconductors, and (b) source/drain resistance, due both to high mobility and to the narrower bandgap of many non- Si semiconductors, with the narrower bandgap leading to a lower electrical resistance between the metal (or metal-alloy) contact and the semiconductor.
  • Another new application could be the combination of Si CMOS logic with ultra-high speed RF devices, such as InP- or GaAs-based high electron-mobility transistor (HEMT) or heteroj unction bipolar transistor (HBT) devices similar to those utilized for high-frequency applications today.
  • HEMT high electron-mobility transistor
  • HBT heteroj unction bipolar transistor
  • Yet another application may be the combination of Si CMOS logic with opto-electronic devices, since many non-Si semiconductors have light emission and detection performance superior to Si.
  • Selective epitaxy is an attractive path for hetero-materials integration for several reasons. First, it facilitates adding the non-Si semiconductor material only where it is needed, and so is only marginally disruptive to a Si CMOS process performed on the same wafer. Also, selective epitaxy may allow multiple new materials to be combined on a common wafer, e.g., Ge for PMOS and InGaAs for NMOS. Furthermore, it is likely to be more economical than key alternative paths, e.g., layer transfer of global hetero-epitaxial films, especially for integrating materials with large lattice mismatch.
  • TDD threading dislocation densities
  • the free edge is brought closer to another free edge by patterning the substrate into growth areas, then it is possible to generally confine threading dislocations to a portion of the epitaxial layer proximate to its interface with the starting substrate, thereby minimizing the TDD in the remainder of the epitaxial layer.
  • the invention disclosed herein focuses on bonding patterned substrates with alternative active-area materials epitaxially formed thereon to a rigid platform, such as, for example, an insulator disposed over a handle wafer, and then removing the highly-defective interface areas along with the underlying substrates to produce alternative active-area regions disposed over the insulator and substantially exhausted of misfit and threading dislocations.
  • a rigid platform such as, for example, an insulator disposed over a handle wafer
  • the invention contemplates fabrication of semiconductor devices based on monolithic lattice- mismatched heterostructures on insulators long sought in the art but heretofore impractical due to dislocation defects.
  • the invention disclosed herein features methods for forming a structure, including providing a first substrate including, or consisting essentially of, a first crystalline semiconductor material.
  • a first insulator layer is formed over the first substrate, and at least one opening is defined in the first insulator layer extending to the first substrate.
  • the opening is filled, at least partially, with an active-area material by, for example, selective epitaxy to form an active-area region surrounded by an insulator region.
  • the method further includes forming a cleave area at a predetermined distance in relation to the interface between the first substrate and the active-area regions by, for example, implanting gaseous material into the active-area and the insulator regions.
  • the active-area and the insulator regions are then bonded to a rigid platform, for example, a structure including a second insulator layer disposed over a second substrate including, or consisting essentially of, a second crystalline semiconductor material.
  • the method further includes causing the bonded structure to split at least along the cleave area into a first portion and a second portion, the second portion including at least a portion of the active-area region bonded to the second insulator layer.
  • the split within the bonded structure is caused by thermal annealing, e.g. at a temperature ranging from about 350 0 C to 700 0 C.
  • a surface of the active-area region is planarized prior to implantation and bonding such that its surface is substantially coplanar with a surface of the insulator region.
  • an exposed surface of the second portion can be planarized to remove cleave-induced surface roughness and, if desired, reduce a thickness of the active-area region in the second portion to a desired value.
  • the second portion is annealed after the split at a temperature ranging from about 600 °C to about 900 ° C.
  • the cleave area at least partially lies within the active-area and the insulator regions substantially parallel to the interface between the first substrate and the active-area region at a first predetermined distance therefrom, such that, following the split, the first portion includes portions of the active-area and the insulator regions disposed over the first substrate.
  • a strained region is formed within the active-area region, such that the cleave area at least partially includes the strained region.
  • the cleave area at least partially lies within the first substrate substantially parallel to the interface between the first substrate and the active-area region at a second predetermined distance therefrom, such that, after causing the bonded structure to split into the first portion and the second portion, the second portion of the bonded structure includes a portion of the first substrate.
  • the remaining first crystalline semiconductor material is removed from the active-area and the insulator regions by post-annealing planarization and/or etching.
  • the active-area material is epitaxially grown over the first substrate in a bottom portion of the opening, and then a third insulator layer is deposited in a top portion of the opening over the active-area material.
  • the surface of the third insulator layer can be planarized prior to implantation and bonding such that the surface is substantially coplanar with a surface of the insulator region.
  • the cleave area substantially coincides with or is proximate to the interface between the active- area material and the first substrate, such that the cleave area at least partially includes the interface between the first substrate and the active-area region.
  • a strained semiconductor layer is deposited over the surface of the active-area region.
  • a dielectric material is deposited over the active-area material in the opening to form a buffer region above the active-area region. A surface of the buffer region extends at least to a surface of the first insulator layer.
  • the surface of the buffer region is or can be made co- planar with the surface of the first insulator layer.
  • the rigid platform may include one or more layers of glass, quartz, plastic, polymer, or other dielectric material, either self- supporting or disposed over another layer.
  • the rigid platform can be a substrate including a second insulator layer disposed over a second substrate including, or consisting essentially of, a second crystalline semiconductor material.
  • the first semiconductor and/or second semiconductor materials include, or consist essentially of, single-crystal silicon, germanium, a silicon-germanium alloy, and/or a IN-V material.
  • the first and second substrates may be, for example, a bulk silicon wafer, a bulk germanium wafer, a bulk Hl-V wafer such as gallium arsenide or indium phosphide, a semiconductor-on-insulator (SOI) substrate, or a strained semiconductor-on-insulator (SSOI) substrate.
  • the first and second insulator layers may include, or consist essentially of, silicon dioxide, aluminum oxide, silicon nitride, silicon carbide, and/or diamond, and may have a thickness of, e.g., 50 - 1000 nanometers.
  • the third insulator layer can include, or consist essentially of, either the same material as the first and second insulator layers, or include a different material, such as, for example, a low-K dielectric material.
  • the active-area material is a crystalline semiconductor material, such as a group IV element or compound, a Ml-V compound, and/or a H-Vl compound.
  • the group IV element may be carbon, germanium, and/or silicon, e.g., (110) silicon.
  • the group IV compound may include silicon, germanium, tin, and/or carbon, e.g., silicon germanium (SiGe).
  • the Hl-V compound may be, e.g., gallium arsenide (GaAs), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium phosphide (InP), or indium antimonide (InSb), gallium nitride (GaN), and/or indium nitride (InN).
  • the U-Vl compound may be, e.g., zinc telluride (ZnTe), cadmium selenide (CdSe), cadmium telluride (CdTe), zinc sulfide (ZnS), and/or zinc selenide (ZnSe).
  • the first crystalline semiconductor material may have a first crystalline orientation and the active-area material comprises a third crystalline semiconductor material having a second crystalline orientation different from the first crystalline orientation.
  • the first crystalline semiconductor material may be (100) silicon and the active-area material may be (110) silicon.
  • the gaseous material may include ions of hydrogen, helium, argon, krypton, and/or neon.
  • the invention relates to a semiconductor structure that includes a substrate and, thereover, a patterned insulator layer defining at least one opening.
  • the substrate can be a rigid platform that includes one or more layers of glass, quartz, plastic, polymer, or other dielectric material, either self-supporting or disposed over another layer, for example, including, or consisting essentially of, a crystalline semiconductor material.
  • the structure further includes an active-area region formed in the opening and bonded to the substrate.
  • the active-area region includes, or consists essentially of, an active-area material substantially exhausted of misfit and threading dislocations.
  • the substrate may include a base insulator layer disposed over the crystalline semiconductor material underneath the patterned insulator layer.
  • the active-area region may have a buffer region that includes, or consists essentially of, a dielectric material and is disposed in the opening between the substrate and the active-area material.
  • the active-area region may also have a strained semiconductor layer disposed over the active-area material.
  • a dislocation pile-up density in the active-area material does not exceed about 1 /cm, for example, is less than about 0.01 /cm.
  • a threading dislocation density in the active-area material does not exceed about 10 3 cm '2 , for example, is less than about 10 2 cm "2 .
  • one or more electronic devices such as, for example, a field-effect transistor (FET), such as a complementary metal-oxide-semiconductor FET
  • FET field-effect transistor
  • FET complementary metal-oxide-semiconductor
  • CMOSFET complementary metal-semiconductor FET
  • MESFET metal-semiconductor FET
  • non-FET device such as a diode
  • FIGS. 1A-1D, 2A-2C, 3A-3D, 4A-4B, and 5A-5C depict schematic cross-sectional side views illustrating formation of semiconductor structures including alternative active-area materials
  • the invention disclosed herein contemplates fabrication of monolithic lattice-mismatched semiconductor heterostructures disposed over an insulator platform with limited-area regions substantially exhausted of misfit and threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
  • a substrate 100 includes a crystalline semiconductor material.
  • the substrate may be, for example, a bulk silicon wafer, a bulk germanium wafer, a bulk Ml-V wafer such as gallium arsenide or indium phosphide, a SOI substrate, or a SSOI substrate.
  • An insulator layer 110 is formed over the substrate, as shown in FIG. 1A.
  • the insulator layer may be, for example, silicon dioxide, aluminum oxide, silicon nitride, silicon carbide, or diamond, and may have a thickness of, e.g., 50 - 1000 nanometers (nm).
  • the insulator layer may be formed by a deposition method, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD).
  • CVD chemical vapor deposition
  • PECVD plasma-enhanced chemical vapor deposition
  • LPCVD low-pressure chemical vapor deposition
  • a mask (not shown), such as a photoresist mask, is formed over the insulator layer 110.
  • the mask is patterned to expose at least a portion of the insulator layer.
  • the exposed portion of the insulator layer is removed by, e.g., reactive ion etching (RIE), to define openings 12OA and 12OB and expose areas 130A and 130B of a top surface of the substrate 100, as shown in FIG. 1B.
  • RIE reactive ion etching
  • Each of the openings may have a width of, e.g., 50 nm - 10 micrometers ( ⁇ m) and a length of, e.g., 50 nm - 10 ⁇ m.
  • the height of the openings equals the thickness of the insulator layer.
  • the openings 120A and 120B are filled with active-area materials by selective epitaxy, thereby forming active-area regions 140A and 140B surrounded by insulator regions of the insulator layer 110.
  • Selective epitaxy may be performed by a deposition method such as atomic layer deposition (ALD) or CVD, for example, PECVD, LPCVD, ultra-high vacuum CVD, reduced-pressure CVD, or metalorganic CVD.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • PECVD atomic layer deposition
  • LPCVD ultra-high vacuum CVD
  • reduced-pressure CVD reduced-pressure CVD
  • metalorganic CVD metalorganic CVD
  • the active-area regions 140A and 140B are formed selectively, i.e., the materials are deposited over the areas 130A, 130B of the crystalline semiconductor material of substrate 100 exposed by the openings, but are not substantially deposited or formed on the insulator layer 110.
  • the active-area materials are crystalline semiconductor material, such as a group IV element or compound, a Hl-V compound, or a H-Vl compound.
  • the group IV element may be carbon, germanium, or silicon, e.g., (110) silicon.
  • the group IV compound may include silicon, germanium, tin, or carbon, e.g., SiGe.
  • the NI-V compound may be, e.g., GaAs, InAs, InGaAs, InP, InSb, GaN, InN, or mixtures thereof.
  • the M-Vl compound may be, e.g., ZnTe, CdSe, CdTe, ZnS, and/or ZnSe.
  • the active-area regions 140A and 140B may include, or consist essentially of, the same or different materials. Also, in some embodiments, one or more of the active-area regions may include, or consist essentially of, silicon.
  • the lattice mismatch (or difference in equilibrium lattice constants) between the active-area materials and the crystalline semiconductor material of substrate 100 may, in some embodiments, exceed approximately 4%.
  • the lattice mismatch between the active-area materials and the crystalline semiconductor material of substrate is greater than approximately 8%.
  • the density of misfit dislocations which typically form as the active-area material relaxes to its equilibrium lattice constant and are present near the interface between the active-area material and the substrate, can exceed 1 x 10 6 cm '2 , even exceeding 2 x 10 6 cm '2 or 4 x 10 6 cm '2 in some embodiments.
  • These misfit dislocation defects are linear defects generally lying parallel to the interface and generally confined to a thin region near the interface.
  • portions 150A and 150B of the active-area materials may extend above a top surface 160 of the insulator layer 110 for various reasons, thereby forming a non-planar top surface.
  • facets may form at a vertical interface between the semiconductor active area material and the insulator.
  • a top surface of the active-area regions 140A and 140B may not be co-planar with a top surface of the insulator material, because of the difficulty of stopping the selective epitaxy precisely at the point that the openings are filled with the active-area materials.
  • a non-planar surface may present subsequent processing difficulties, for example, compromise bondability of the active-area regions.
  • the portions 150A, 15OB of the active area regions extending above the top surface of the insulator layer may be removed by, for example, planarization, so that surface 170 of the active-area regions is substantially coplanar with the top surface of the insulator layer.
  • the active area material surface may be planarized by, for example, a chemical-mechanical polishing (CMP) step that is selective with respect to the insulator layer.
  • CMP chemical-mechanical polishing
  • gaseous species 205 are introduced into the active-area regions 140A and 140B and the regions of the insulator layer 110 surrounding the active-area regions by, for example, ion implantation.
  • the gaseous species may include, or consist essentially of, ions of hydrogen, helium, argon, krypton, and/or neon.
  • the gaseous species consist essentially of H + ions. Implantation of the gaseous species is controlled such that the species penetrate the active- area and the insulator regions, forming a narrow cleave area 210 at a predetermined distance from the coplanar top surfaces 160, 170 of these regions.
  • the cleave area lies within the active-area and the insulator regions at a distance D1 above and substantially parallel to the interface between the substrate 100 and the active-area regions.
  • the insulator regions may have smaller cross-sectional areas than the active-area regions 140A and 140B, and thus the cleaving behavior of the insulator regions will be substantially similar to that of the active-area regions. Additionally, after the split induced along the cleave area discussed in detail below, the insulator regions may function as isolation regions, e.g., shallow trench isolation regions, for devices subsequently formed in the active-area regions.
  • the thickness of the cleave area depends on the parameters of the ion implantation, and, in many embodiments, is carefully controlled such that the cleave area is about 10 - 50% of the thickness of insulator layer 110. For example, for a thickness of insulator layer 110 of about 100 nm, the cleave area can be approximately 10 - 50 nm thick.
  • the implantation of the gaseous species to form cleave area 210 can be replaced or supplemented by another method of introducing gaseous species, such as diffusion or plasma- assisted gasification, e.g., plasma hydrogenation.
  • dislocation defects induced by the lattice mismatch between the crystalline semiconductor material of the substrate and the active-area material are generally concentrated in the active-area region proximate to the interface with the substrate.
  • the heights of these highly- defective zones 220A, 220B of the active-area regions above the interface with the substrate 100 depends on, e.g., the degree of lattice mismatch between the materials, as well as epitaxial deposition conditions.
  • portions 230A, 230B have a TDD at least three orders of magnitude lower than a TDD in the cleave area and/or highly-defective zones 220A, 220B. In another embodiment, portions 230A, 230B have a TDD at least five orders of magnitude lower than a TDD in the cleave area and/or the highly-defective zones.
  • portions 230A, 230B have a TDD at least five orders of magnitude lower than a TDD in the cleave area and/or the highly-defective zones.
  • the active-area region being "substantially exhausted of misfit and threading dislocations” refers either to a complete absence of dislocations in this region or to the level thereof being sufficiently low so as not to meaningfully affect the performance of electronic device(s) at least partially incorporating this region.
  • the off- state current of these devices is less than about 10 '6 A/ ⁇ m, preferably, less than about 10 '8 A/ ⁇ m, and more preferablylO '10 A/ ⁇ m.
  • top surfaces 160 and 170 of the o active-area and the insulator regions are bonded to a surface 240 of an insulator layer 250 disposed over a semiconductor substrate 260 utilizing methods known in the art, e.g. as described in U.S. Patent No. 6,602,613, incorporated herein by reference, thereby forming a structure 270.
  • the surface 240 of the insulator layer and/or top surfaces 160, 170 is cleaned by a wet chemical cleaning process, e.g. by a hydrophilic surface preparation process.
  • the wafer-bonding energy should be strong enough to sustain the subsequent layer transfer, as discussed below.
  • top surfaces 160,170 and/or the surface 240 of the insulator layer 250 are plasma- treated, either before, after, or instead of a wet clean.
  • the plasma environment may include at least one of the following species: oxygen, ammonia, argon, nitrogen, diborane, and phosphine.
  • top surfaces 160,170 and the surface 240 are bonded together by bringing them in contact with each other at room temperature.
  • the bond strength may be greater than 1000 mJ/m 2 , achieved at a low temperature, such as, for example, less than 600 "C.
  • bonding of top surfaces 160,170 of the active-area and the insulator regions with the surface 240 of the insulator layer 250 generally requires that the root mean square surface roughness of these surfaces not exceed about 1 nm. Accordingly, in many embodiments, to improve bondability, the surfaces are planarized by CMP.
  • the insulator layer includes, or consists essentially of, silicon dioxide, aluminum oxide, silicon nitride, silicon carbide, or diamond, and may have a thickness of, e.g., 50 - 1000 nanometers (nm).
  • the semiconductor substrate 260 may be, for example, a bulk silicon wafer, a bulk germanium wafer, a bulk Hl-V wafer such as gallium arsenide or indium phosphide, or a SOI substrate.
  • semiconductor substrate 260 and insulator layer 250 may be replaced by another type of rigid platform, including but not limited to self-supporting substrates including or consisting essentially of glass, quartz, plastic, polymer, or any of the dielectrics discussed above in reference to insulator layer 250.
  • the lattice mismatch between the active-area materials and the crystalline semiconductor material of substrate 260 may exceed approximately 4%. In a particular embodiment, the lattice mismatch between the active-area materials and the crystalline semiconductor material of substrate 260 exceeds approximately 8%.
  • a top insulator layer may be formed over the top surfaces 160, 170 of the active-area and insulator regions, resulting in insulator-on- insulator bonding.
  • This top insulator layer may include, or consist essentially of, silicon dioxide, aluminum oxide, silicon nitride, silicon carbide, or diamond, and may have a thickness of, e.g., 50 - 1000 nm.
  • the top insulator layer is bonded directly to the substrate 260, without providing the insulator layer 250 therebetween.
  • the structure 270 is then subjected to thermal annealing at a temperature ranging from about 350 0 C to 700 0 C for a period of time from about five minutes to about four hours.
  • the thermal annealing induces a split in the structure 270 along the cleave area 210, separating the substrate 100 with portions of the insulator layer 110, and the active-area regions 140A, 140B having thickness D1 thereon from the portions 230A, 230B of the active-area regions surrounded by the insulator regions and bonded to the insulator layer 250.
  • a mechanical force and/or a jet of gas or liquid may be applied to the structure 270 in addition to or instead of the thermal annealing to induce the split.
  • exposed surfaces 280 of the active-area regions are planarized or smoothed, e.g. using CMP, to remove cleave-induced surface roughness and, if desired, reduce a thickness of the active- area regions to a desired value.
  • a root mean square surface roughness of the surface 280 does not exceed about 1 nm.
  • the alternative active-area regions 230A and 230B are substantially exhausted of misfit and threading dislocations.
  • Defect densities can be measured using a standard chromic acid-based Schimmel etch as outlined, for example, in Journal of the Electrochemical Society 126:479 (1979), and an optical microscope operated in differential interference contrast (Nomarski) mode. TDDs can be calculated by counting the number of etch pits per unit area located away from dislocation pile-ups, yielding units of inverse area (cm '2 ).
  • Dislocation pile-up densities can be calculated by measuring the total length of dislocation pile-ups per unit area, yielding units of inverse length (cm 1 ).
  • Defect densities may also preferably be confirmed by the use of a complementary characterization technique such as plan-view transmission electron microscopy.
  • a dislocation pile-up density in these active-area regions does not exceed about 20/cm, for example, is less than about 5/cm, preferably ranges from 0 to about 1 /cm, and, more preferably, is less than about 0.01 /cm.
  • TDD in these regions is less than about 10 5 cm '2 , for example, less than about 10 3 cm '2 , and, preferably, ranges between 0 and about 10 2 cm '2 .
  • the structure 270 is further annealed at a temperature ranging from 600 - 900 "C, e.g., at a temperature greater than about 800 °C, to strengthen the bond between the surfaces 160, 170 and the surface 240.
  • co-planar active- area regions 340A and 340B and the regions of the insulator layer 310 surrounding the active-area regions are formed over the substrate 300 as described above in connection with FIGS. 1A- 1C.
  • Gaseous species 305 e.g. including, or consisting essentially of, ions of hydrogen, helium, argon, krypton, and/or neon, are introduced into the active-area and the insulator regions by, for example, ion implantation.
  • ion implantation e.g. including, or consisting essentially of, ions of hydrogen, helium, argon, krypton, and/or neon
  • implantation of the gaseous species is controlled such that the species penetrate the substrate 300 through the active-area and the insulator regions, forming a narrow cleave area 325 at a predetermined distance D2 below the interface between the substrate and the active-area regions.
  • the distance D2 may range, for example, from about 10 nm to about 1000 nm.
  • the cleave area is disposed within a homogeneous zone of the crystalline material of the substrate 300.
  • the structure 370 is split along the cleave area 325, separating the substrate from a portion 375 thereof having the thickness D2 (and disposed over the active-area regions surrounded by the insulator regions) and bonded to an insulator layer 380, which itself, in turn, is disposed over a semiconductor substrate 390.
  • the substrate 390 may be, for example, a bulk silicon wafer, a bulk germanium wafer, a bulk IM-V wafer such as gallium arsenide or indium phosphide, or a SOI substrate.
  • a TDD of the alternative active-area regions is at least three (and, preferably, at least five) orders of magnitude lower than that present in the removed portion of the active-area material.
  • a dislocation pile-up density in these active-area regions does not exceed about 20/cm, for example, is less than about
  • TDD in these regions is less than about 10 5 cm “2 , for example, less than about 10 3 cm 2 , and, preferably, ranges from 0 to about 10 2 cm "2 .
  • co-planar active-area regions 440A and 440B and the regions of the insulator layer 410 surrounding the active-area regions are formed over the substrate 400, as described above in connection with FIGS. 1A- 1C.
  • Gaseous species 405, e.g. including, or consisting essentially of, ions of hydrogen, helium, argon, krypton, and/or neon, are introduced into the active-area and the insulator regions by, for example, ion implantation.
  • ion implantation e.g. including, or consisting essentially of, ions of hydrogen, helium, argon, krypton, and/or neon
  • implantation of the gaseous species is controlled such that the species penetrate through the active-area and the insulator regions to an interface 430 between the substrate and the active-area regions, forming a narrow cleave area 425 that substantially coincides with the interface, as shown in FIG. 4A.
  • the resulting structure is split along the cleave area, separating the substrate from the active-area regions surrounded by the insulator regions and bonded to an insulator layer, which itself, in turn, is disposed over a semiconductor substrate.
  • a mild thermal anneal is performed after implantation of gaseous species 405. This anneal promotes diffusion of gaseous species 405 to interface 430 and any crystalline defects that may be present there.
  • the anneal may be performed at, for example, 100 - 300 0 C for a period of 1 - 30 minutes.
  • strained layers 435A and 435B are formed within the active-area regions during epitaxial deposition.
  • a layer of a semiconductor material that is lattice-mismatched to the active-area material can be selectively deposited over a portion of the active-area material to a thickness below the critical thickness of such lattice-mismatched material, and then the rest of the active-area material is deposited over the lattice-mismatched material.
  • the strained layer is tensilely, rather than compressively, strained to better accommodate implanted ions within its crystalline lattice.
  • Implantation of the gaseous species is controlled such that the species penetrate through the active-area and the insulator regions to the strained layers, forming a narrow cleave area 425 that substantially coincides with the strained layers in the active- area regions.
  • the resulting structure is split along the cleave area, separating the substrate from a portion thereof disposed over the active-area regions surrounded by the insulator regions and bonded to an insulator layer, which itself, in turn, is disposed over a semiconductor substrate.
  • exposed surfaces of the active-area regions can be planarized or smoothed, e.g. using CMP, to remove cleave-induced surface roughness and, if desired, reduce a thickness of the active-area regions to a desired value.
  • CMP CMP
  • alternative active-area regions disposed over the insulator and substantially exhausted of misfit and threading dislocations are obtained.
  • employing the interface area between the substrate and the active-area regions or the deliberately-introduced strained layer as a target height for the cleave area improves control over penetration of the implanted ions and associated thickness of the active-area regions.
  • any portion of strained layers 435A, 435B remaining after splitting and planarization may be used in subsequently formed devices, as, for example, transistor channel regions with enhanced mobility.
  • the epitaxially deposited active area material(s) only partially fill openings 520A and 520B defined in an insulator layer 510 and extending to the substrate 500.
  • top surfaces of active-area regions 540A and 540B do not reach to the top surface 560 of the insulator layer.
  • the remaining space in the openings can be left empty, or, as shown in FIG. 5B, filled with a dielectric material forming buffer regions 550A and 550B over the active-area regions.
  • the dielectric material may be deposited over the entire surface of active-area regions 540A, 540B and top surface 560 of the insulator layer.
  • the structure may then be planarized such that any dielectric material formed over top surface 560 of the insulator layer is removed, and the dielectric material remains only over active-area regions 540A, 540B. Should any dielectric material remain over top surface 560 of the insulator layer, it will at least be co-planar with a top surface of buffer regions.550A, 55OB.
  • the dielectric material may include, or consist essentially of, silicon dioxide, aluminum oxide, silicon nitride, and/or silicon carbide, and can be the same material used for the insulator layer 510, or a different material.
  • the dielectric material is a low-K dielectric with a lower dielectric constant than that of silicon dioxide; such materials are particularly suitable for subsequent manufacturing of FDSOI devices.
  • the dielectric material can be deposited, such as by CVD or ALD, or spun on from a solution. Suitable thicknesses for the dielectric material range from 10 to 200 nm.
  • suitable low-K dielectrics include silsequioxane-based polycyclic oligomers or polymers such as hydroxyl silsequioxane (HSQ) or methyl silsequioxane (MSQ); Black Diamond, available from Applied Materials, Inc. of Santa Clara, CA; CORAL, available from Novellus Systems Inc.
  • SiCOH organosilicate glasses or carbon doped oxides
  • SiLK available from Dow Chemical Co. of Midland, Ml
  • benzocyclobutene (BCB) porous silica
  • polymer foams available from GX-3, HOSP, and NANOGLASS, available from Honeywell International Inc. of Sunnyvale, CA.
  • top surface 565 of the dielectric buffer regions is optionally planarized for improved bondability.
  • steps of forming a cleave area by ion implantation, bonding, and annealing with optional post-annealing planarization of the active-area regions are performed in a manner similar to that described above in connection with FIGS. 2A- 2C, 3A-3D, and 4A-4B, forming the active-area regions of desired thickness disposed over the dielectric regions 550.
  • the dielectric buffer regions are bonded to a handle wafer 570, including a semiconductor substrate 590 having an optional insulating layer 580 thereover.
  • a final thickness of the active-area regions is established prior to the bonding steps.
  • having dielectric buffer regions of the active-area regions generally facilitates bondability to the insulator layer 590.
  • active area regions 640A, 640B are formed over a common insulator layer 680 disposed over a semiconductor wafer 690, as described above in connection with FIGS. 2A- 2C, 3A-3C, or 4A- 4B. Then, an n-MOS transistor 615A and a p-MOS transistor 615B are formed, having source regions 618A, 618B, drain regions 620A, 620B, and channel regions 622A, 622B disposed in the active-area material(s).
  • the insulator regions 610 function as isolation regions, e.g., shallow trench isolation regions, for transistor 615A, 615B.
  • Additional semiconductor layers may be formed above the active areas on the insulator.
  • thin strained semiconductor layers 645A, 645B are formed atop the active areas and can be subsequently used as channels for transistors.
  • the layers 645A, 645B are tensilely strained and formed of silicon.
  • these layers may be formed in a dedicated chamber of a deposition tool that is not exposed to the source gases for the epitaxial growth of the active-area material, thereby avoiding cross-contamination and improving the quality of the interface between the strained layers and the active-area regions.
  • strained layers 645A, 645B may be formed from one or more isotopically pure precursors, lsotopically pure materials have better thermal conductivity than conventional materials consisting of mixtures of different isotopes. Higher thermal conductivity may help dissipate heat from devices subsequently formed on these strained layers, thereby maintaining the enhanced carrier mobilities these layers provide.
  • the strained layers may be formed of SiGe, or at least one group II, group III, group V, and/or group Vl element.
  • the strained layers have a thickness of, for example, 50 - 500 A, preferably below 300 A.
  • Further processing steps may include the formation of gate dielectric layers 635A, 635B, the deposition of gate electrode materials 625A, 625B, and the definition of gates by, e.g., dry etching, such that spacers 642A, 642B are formed adjacent to the gate dielectric and gate electrode layers.
  • the source and drain regions may be defined by an ion implantation step, lnterlayer dielectrics may be formed over gate, source, and drain, and contact holes may be defined.
  • Metal layers may be deposited in the contact holes and over the structure.
  • the interlayer dielectrics for example, including or consisting essentially of, silicon nitride, are used to induce strain on at least one of channel regions 622A, 622B.
  • CMOS devices e.g. those having different n- and p-active areas, are described in co-pending provisional application Serial No. 60/702,363, incorporated herein by reference.
  • the resulting transistors may be, for example, a field- effect transistor (FEiT), such as a complementary metal-oxide-semiconductor FET (CMOSFET) or a metal-semiconductor FET (MESFET).
  • FET field- effect transistor
  • CMOSFET complementary metal-oxide-semiconductor FET
  • MESFET metal-semiconductor FET
  • the device is a non- FET device such as a diode.
  • the diode device could be a light detecting device (photodiode), or a light emitting device (either a light-emitting diode, or a laser diode).
  • the device is a bipolar junction transistor.

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Abstract

La présente invention concerne des hétérostructures semi-conductrices monolithiques en désaccord de maille ainsi que des procédés permettant de les fabriquer, par exemple par liaison de substrats à motifs avec des matériaux à surfaces actives alternatives sur une plate-forme diélectrique rigide puis par élimination des zones d'interface hautement défectueuses conjointement avec les substrats sous-jacents de manière à produire des zones à surfaces actives alternatives disposées sur le matériau isolant, lesquelles zones sont sensiblement exemptes de dislocations de désadaptation et de dislocations traversantes.
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EP2107602A1 (fr) * 2008-03-31 2009-10-07 Commissariat a L'Energie Atomique Procédé de fabrication d'une structure micro-électronique du type à semi-conducteur sur isolant et à motifs différenciés
FR2929444A1 (fr) * 2008-03-31 2009-10-02 Commissariat Energie Atomique Procede de fabrication d'une structure micro-electronique du type a semi-conducteur sur isolant et a motifs differencies, et structure ainsi obtenue.
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US8877606B2 (en) 2009-01-12 2014-11-04 International Business Machines Corporation Low cost fabrication of double box back gate silicon-on-insulator wafers with subsequent self aligned shallow trench isolation
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CN102439695A (zh) * 2009-02-19 2012-05-02 硅绝缘体技术有限公司 应变材料层的松弛和转移
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JP2012518284A (ja) * 2009-02-19 2012-08-09 ソイテック ひずみ材料層の緩和および転写
KR101512777B1 (ko) 2009-02-19 2015-04-16 소이텍 변형된 물질 층들의 이완 및 전달
TWI474402B (zh) * 2009-02-19 2015-02-21 Soitec Silicon On Insulator 應變材料層的鬆弛及轉移
GB2487307A (en) * 2009-11-06 2012-07-18 Ibm Hybrid double box back gate silicon-on-insulator wafers with enhanced mobility channels
GB2487307B (en) * 2009-11-06 2014-02-12 Ibm Hybrid double box back gate silicon-on-insulator wafers with enhanced mobility channels
US8587063B2 (en) 2009-11-06 2013-11-19 International Business Machines Corporation Hybrid double box back gate silicon-on-insulator wafers with enhanced mobility channels
WO2011054852A1 (fr) * 2009-11-06 2011-05-12 International Business Machines Corporation Tranches de silicium sur isolant à grille arrière à double boîtier hybride avec canaux de mobilité renforcés
KR20160098202A (ko) * 2013-12-24 2016-08-18 인텔 코포레이션 헤테로지니어스 반도체 재료 통합 기술들
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