WO2007029991A1 - Memoire vive statique a plusieurs valeurs - Google Patents

Memoire vive statique a plusieurs valeurs Download PDF

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Publication number
WO2007029991A1
WO2007029991A1 PCT/KR2006/003609 KR2006003609W WO2007029991A1 WO 2007029991 A1 WO2007029991 A1 WO 2007029991A1 KR 2006003609 W KR2006003609 W KR 2006003609W WO 2007029991 A1 WO2007029991 A1 WO 2007029991A1
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WO
WIPO (PCT)
Prior art keywords
transistor
drain
word lines
bitlines
gate
Prior art date
Application number
PCT/KR2006/003609
Other languages
English (en)
Inventor
Hun Woo Kye
Original Assignee
Excel Semiconductor Inc,
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Application filed by Excel Semiconductor Inc, filed Critical Excel Semiconductor Inc,
Publication of WO2007029991A1 publication Critical patent/WO2007029991A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/565—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using capacitive charge storage elements
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/02—Structural aspects of erasable programmable read-only memories
    • G11C2216/08—Nonvolatile memory wherein data storage is accomplished by storing relatively few electrons in the storage layer, i.e. single electron memory

Definitions

  • the present invention relates to a semiconductor memory apparatus and more particularly, to a multiple- valued (MV) static random-access-memory (SRAM) device capable of storing multiple value levels using a single electron transistor (SET) device.
  • MV multiple- valued
  • SRAM static random-access-memory
  • the SET has advantages of increasing the integration degree of a circuit and decreasing power consumption.
  • the SET also has inherent characteristics that the drain current of the SET increases and decreases periodically according to a gate bias.
  • researchers have made an effort to increase functionality of a circuit with fewer transistors by using such characteristics.
  • the SET device has been proven to have characteristics highly suitable for applications in a multiple- valued logic circuit and therefore, incessant efforts have been made to use the SET device for the multiple- valued logic circuit application.
  • FIG. 1 is a diagram for explaining a universal lateral gate 100 in which a single electron transistor (SET) device and a metal-oxide-semiconductor (MOS) transistor are coupled to each other.
  • SET single electron transistor
  • MOS metal-oxide-semiconductor
  • the drain voltage Vds of the SET is maintained at a constant voltage equal to Vgg - Vth. Since the voltage Vgg - Vth is low enough to satisfy a Coulomb blockage condition, the SET shows characteristics that the drain current of the SET increases and decreases periodically according to an input voltage Vin. In this case, a constant current Io is supplied from a constant current source to the drain of the SET.
  • the output voltage Vout will be rapidly decreased from a high level to a low level.
  • the input voltage Vin is changed so as to decrease the drain current of the SET to a current lower than the current Io supplied from the constant current source , the output voltage Vout will be rapidly increased from a low level to a high level.
  • the output voltage Vout of the universal lateral gate 100 may have a square waveform with a high voltage swing.
  • FIG. 2 is a diagram showing an exemplary circuit of a quantizer 200 using the universal lateral gate 100 of FIG. 1.
  • the constant current source provides a number of stability points and the quantizer 200 operates in stable regions defined by dotted lines between two neighboring stability points. More particularly, when a clock signal CLK is enabled, an input voltage Vin is transferred to a storage node SN through a transistor M2 and quantized to a stability point corresponding to the voltage after the clock signal CLK is cut off. Accordingly, it is possible to obtain an input-output (Vin-Vout) voltage characteristic similar to a stepped waveform.
  • the quantizer 200 having the SET device and the MOS transistor coupled to each other can be used for a memory application.
  • the quantizer 200 can store multiple level voltages without performing an additional refresh operation, it is highly effective in a multiple-valued static memory.
  • FIG. 3 is a circuit diagram showing a DRAM type multiple- valued (MV) static random-access-memory (SRAM) using the quantizer 200 of FIG. 2.
  • MV multiple- valued static random-access-memory
  • an MV SRAM cell 300 includes a first transistor Ml connected between an SET and a storage node SN and having a gate connected to the ground voltage; a second transistor M2 connected between a power supply voltage Vdd and the storage node SN and having a gate connected to the storage node SN; a third transistor M3 connected between a bitline BL and the storage node SN and having a gate connected to a word line WL; and a cell capacitor Cs connected between the storage node SN and the ground voltage.
  • the first and second transistors Ml and M2 are depletion transistors and the third transistor M3 is an NMOS transistor.
  • FIG. 4 is a timing diagram showing write and read operations of the MV SRAM shown in FIG. 3.
  • the word line WL is enabled at t ⁇ .
  • a voltage corresponding to a multiple logic value is applied to the bitline BL at tl.
  • voltages having four different levels need to be applied to the storage node SN through the bitline BL.
  • the word line WL is cut off at t2 and the bitline BL is precharged to the ground voltage at t3. Accordingly, the voltage levels stored in the storage node SN are maintained without being refreshed in accordance with the principle of the stability point of an operation of the quantizer 200 in FIG. 2.
  • the word line WL is enabled at t4 and electric charges stored in the cell capacitor Cs are shared with a parasitic capacitor of the bitline BL.
  • a sense amplifier is enabled so as to sense the multiple value levels.
  • the MV SRAM cell includes four transistors and one capacitor, the chip size of the MV SRAM cell is increased.
  • a multiple- valued memory is advantageous in that it increases storage density by increasing the number of bits stored in a cell but disadvantageous in that it decreases the number of device used in the cell, thereby defeating the advantages of the MV SRAM. Disclosure of Invention Technical Problem
  • the present invention is contrived to solve the above-mentioned problem.
  • An advantage of the present invention is that it provides a multiple- valued (MV) SRAM device including two transistors, a single electron transistor (SET) device, and a capacitor, in which a constant current source is shared by bitlines.
  • an MV multiple- valued
  • SRAM device for storing multiple value levels, the device including: one or more word lines; one or more bitlines; a first transistor having a source connected to a power supply voltage and a gate and a drain connected to the bitlines; and a unit cell connected to intersections of the word lines and the bitlines, wherein the unit cell comprises: a second transistor having a gate connected to the word lines and a drain connected to the bitlines; an SET (single electron transistor) device having a gate connected to the drain of the second transistor and a source connected to the ground voltage; a third transistor connected between the drain of the second transistor and the drain of the SET device, wherein the gate of the third transistor is connected to the ground voltage; and a cell capacitor connected between the drain of the second transistor and the ground voltage.
  • SET single electron transistor
  • the SET device may include the source and the drain formed on a semiconductor substrate; a metal island disposed between the source and the drain so as to form a tunnel junction between the source and the drain; and the gate disposed in the vicinity of the metal island so as to control electric current flowing through the metal island.
  • the first transistor is a depletion
  • the third transistor is a depletion NMOS transistor.
  • data stored in the unit cells is refreshed when the word lines are enabled.
  • the MV SRAM device may further include a plurality of unit cells connected to intersections of a plurality of word lines and a plurality of bitlines, and the word lines are sequentially enabled at a predetermined period in order to refresh the unit cells.
  • the MV SRAM device of the present invention since the number of transistors is fewer than that of the known MV SRAM cell by one, it is possible to increase the storage density of the device. In addition, since the MV SRAM device only needs to enable the word lines in order to rewrite the data, thereby requiring only a small amount of current flow, it is suitable for a low-power application.
  • FIG. 1 is a diagram for explaining a universal lateral gate 100 in which a single electron transistor (SET) device and a metal-oxide-semiconductor (MOS) transistor are coupled to each other;
  • FIG. 2 is a diagram showing an exemplary circuit of a quantizer 200 using the universal lateral gate shown in FIG. 1 ;
  • FIG. 3 is a circuit diagram showing a DRAM type multiple- valued (MV) static random-access-memory (SRAM) using the quantizer of FIG. 2; [27] FIG.
  • MV multiple- valued
  • SRAM static random-access-memory
  • FIG. 4 is a timing diagram showing write and read operations of the MV SRAM shown in FIG. 3;
  • FIG. 5 is a circuit diagram showing an MV SRAM cell according to an embodiment of the present invention;
  • FIG. 6 is a diagram for explaining a refreshing method of the MV SRAM cell shown in FIG. 5;
  • FIG. 7 is a diagram showing an MV SRAM cell array according to an embodiment of the present invention; and
  • FIG. 8 is a diagram for explaining a refreshing method of an MV SRAM cell array shown in FIG. 7.
  • FIG. 5 is a circuit diagram showing an MV SRAM cell according to an embodiment of the present invention.
  • a first transistor Nl serving as a constant current source for maintaining a stability point is connected to the bitlines BL and shared by a plurality of cells.
  • a unit cell 500 includes a second transistor N2 for connecting a storage node SN to the bitlines BL, a SET device N4, a third transistor N3 for maintaining the drain voltage of the SET device N4 at about 1OmV, and a capacitor Cs for storing electric charges.
  • the second transistor N2 has a gate connected to the word lines WL and a drain connected to the bitlines BL.
  • the plurality of cells are connected at intersections of the word lines WL and the bitlines BL.
  • the bitlines BL are connected to the first transistor Nl for maintaining the stability point for the Coulomb blockade condition, and the first transistor Nl is shared by the plurality of cells by means of the bitlines BL.
  • the number of transistors is fewer than that of the MV SRAM cell 300 shown in FlG. 3 by one. Accordingly, it is possible to increase the degree of integration of the MV SRAM device when a plurality of cells are arranged.
  • FlG. 6 is a diagram for explaining a refreshing method of the MV SRAM cell shown in FlG. 5;
  • the storage node SN stores a voltage level of IV during the write operation. When a voltage loss of about 10OmV is occurred in the OFF state of the word line WL, the word line WL is re-enabled.
  • the voltage level of the storage node SN is restored to IV level by the lOOpA current supplied from the first transistor Ml.
  • the word line WL is cut off and the corresponding voltage is stored. In this manner, the word lines are sequentially enabled before the data stored in the cell capacitor Cs is destroyed, thereby maintaining the data stored in each cell.
  • the MV SRAM refresh method according to the present invention is similar to the
  • the refresh method according to the present invention only needs to enable the word lines in order to rewrite the data, thereby eliminating the sense amplifier for a refresh operation, which was required in the refresh method known in the art, in which the sense amplifier needs to be operated after the word lines are enabled in order to rewrite the data.
  • the refresh method known in the art requires a large amount of current flow in order to refresh the data, whereas the refresh method according to the present invention requires only a small amount of current flow in order to rewrite the data. Accordingly, the MV SRAM refresh method according to the present invention is suitable for a low-power application.
  • FlG. 7 is a diagram showing an MV SRAM cell array according to an embodiment of the present invention.
  • MV SRAM cells are arrayed at intersections of word lines WL and bitlines BL.
  • current source transistors Nl serving as a constant current source are connected to each of the bitlines BL.
  • FlG. 8 is a diagram for explaining a refreshing method of an MV SRAM cell array shown in FlG. 7.
  • the word lines WL ⁇ 0>, WL ⁇ 1>, and WL ⁇ 3> are sequentially enabled for every refresh period tref. It is desirable that the refresh period tref is set so as to prevent the data stored in the cell capacitor Cs from being destroyed. Therefore, the voltage level stored in the cell capacitor Cs is maintained.
  • the MV SRAM device of the present invention since the number of transistors is fewer than that of the known MV SRAM cell by one, it is possible to increase the storage density of the device. In addition, since the MV SRAM device only needs to enable the word lines in order to rewrite the data, thereby requiring only a small amount of current flow, it is suitable for a low-power application.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Dram (AREA)

Abstract

L'invention concerne un dispositif à mémoire vive statique à plusieurs valeurs (MV SRAM) pouvant stocker plusieurs niveaux de valeurs au moyen d'un dispositif à transistor monoélectronique (SET). Le dispositif comporte un ou plusieurs canaux mots; une ou plusieurs lignes de bits; un premier transistor ayant une source connectée à une tension d'alimentation ainsi qu'une grille et un drain connectés aux lignes de bits; et une cellule connectée aux intersections des canaux mots et des lignes de bits. Ladite cellule comprend: un deuxième transistor ayant une grille connectée aux canaux mots et un drain aux lignes de bits; un dispositif SET ayant une grille connectée au drain du deuxième transistor et une source connectée à la tension de masse; un troisième transistor reliant le drain du deuxième transistor et celui du dispositif SET, la grille du troisième transistor étant connectée à la tension de masse; et un condensateur de cellule reliant le drain du deuxième transistor et la tension de masse. En conséquence, étant donné que le dispositif MV SRAM n'a besoin que d'activer les canaux mots afin de réécrire les données, ne nécessitant qu'une petite quantité de courant, il convient donc à une application de faible puissance.
PCT/KR2006/003609 2005-09-09 2006-09-11 Memoire vive statique a plusieurs valeurs WO2007029991A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2005-0084298 2005-09-09
KR1020050084298A KR100714823B1 (ko) 2005-09-09 2005-09-09 다치 에스램

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WO2007029991A1 true WO2007029991A1 (fr) 2007-03-15

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PCT/KR2006/003610 WO2007029992A1 (fr) 2005-09-09 2006-09-11 Memoire vive dynamique a plusieurs valeurs

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Publication number Priority date Publication date Assignee Title
KR100844947B1 (ko) 2007-01-16 2008-07-09 주식회사 엑셀반도체 단전자 트랜지스터를 이용한 다치 ｄｒａｍ 셀 및 다치 ｄｒａｍ 셀 어레이
KR100844946B1 (ko) 2007-01-16 2008-07-09 주식회사 엑셀반도체 단전자 트랜지스터를 이용한 다치 ｄｒａｍ 셀 및 다치 ｄｒａｍ 셀 어레이
KR101596034B1 (ko) * 2008-12-18 2016-02-19 충북대학교 산학협력단 단전자 트랜지스터의 드레인 전압을 제어가능한 ｓｅｔ ｕｌｇ회로 및 그 회로를 이용한 단전자 트랜지스터 드레인전압의 제어방법
KR101748726B1 (ko) * 2015-07-01 2017-06-19 엘에스산전 주식회사 회로차단기의 정전압 공급회로

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4984204A (en) * 1988-01-28 1991-01-08 Hitachi, Ltd. High speed sensor system using a level shift circuit
US5677637A (en) * 1992-03-25 1997-10-14 Hitachi, Ltd. Logic device using single electron coulomb blockade techniques
US5852575A (en) * 1993-07-12 1998-12-22 Kabushiki Kaisha Toshiba Apparatus and method for reading multi-level data stored in a semiconductor memory
US5889697A (en) * 1997-10-08 1999-03-30 Advanced Micro Devices Memory cell for storing at least three logic states
US6538923B1 (en) * 2001-02-26 2003-03-25 Advanced Micro Devices, Inc. Staircase program verify for multi-level cell flash memory designs

Family Cites Families (4)

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JPH0830250A (ja) * 1994-07-20 1996-02-02 Fujitsu Ltd 文章処理装置
US5640350A (en) * 1996-05-01 1997-06-17 Iga; Adam Sempa Multi-bit dynamic random access memory cell storage
JP3415502B2 (ja) * 1999-07-30 2003-06-09 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置
US6282115B1 (en) * 1999-12-22 2001-08-28 International Business Machines Corporation Multi-level DRAM trench store utilizing two capacitors and two plates

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4984204A (en) * 1988-01-28 1991-01-08 Hitachi, Ltd. High speed sensor system using a level shift circuit
US5677637A (en) * 1992-03-25 1997-10-14 Hitachi, Ltd. Logic device using single electron coulomb blockade techniques
US5852575A (en) * 1993-07-12 1998-12-22 Kabushiki Kaisha Toshiba Apparatus and method for reading multi-level data stored in a semiconductor memory
US5889697A (en) * 1997-10-08 1999-03-30 Advanced Micro Devices Memory cell for storing at least three logic states
US6538923B1 (en) * 2001-02-26 2003-03-25 Advanced Micro Devices, Inc. Staircase program verify for multi-level cell flash memory designs

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Publication number Publication date
WO2007029992A1 (fr) 2007-03-15
KR100714823B1 (ko) 2007-05-07
KR20070029862A (ko) 2007-03-15

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