WO2007025859A3 - Structure de semi-conducteur a montage fonctionnel lateral - Google Patents
Structure de semi-conducteur a montage fonctionnel lateral Download PDFInfo
- Publication number
- WO2007025859A3 WO2007025859A3 PCT/EP2006/065363 EP2006065363W WO2007025859A3 WO 2007025859 A3 WO2007025859 A3 WO 2007025859A3 EP 2006065363 W EP2006065363 W EP 2006065363W WO 2007025859 A3 WO2007025859 A3 WO 2007025859A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor structure
- functional construction
- lateral area
- laterally
- arrangement
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2401—Structure
- H01L2224/24011—Deposited, e.g. MCM-D type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2401—Structure
- H01L2224/2402—Laminated, e.g. MCM-L type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2405—Shape
- H01L2224/24051—Conformal with the semiconductor or solid-state device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/76—Apparatus for connecting with build-up interconnects
- H01L2224/7615—Means for depositing
- H01L2224/76151—Means for direct writing
- H01L2224/76155—Jetting means, e.g. ink jet
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/821—Forming a build-up interconnect
- H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
- H01L2224/82102—Forming a build-up interconnect by additive methods, e.g. direct writing using jetting, e.g. ink jet
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83194—Lateral distribution of the layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Photovoltaic Devices (AREA)
- Weting (AREA)
- Thin Film Transistor (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
La présente invention concerne un dispositif comprenant un substrat (1) qui présente au moins un composant électronique (2). Une couche (3), notamment un film, s'étend latéralement le long de la surface du substrat et/ou du composant. Le dispositif selon cette invention est caractérisé en ce que la couche (3) d'une région latérale (4) présente respectivement des caractéristiques homogènes définies qui sont variables de région latérale (4) en région latérale (4).
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE200510041100 DE102005041100A1 (de) | 2005-08-30 | 2005-08-30 | Halbleiterstruktur mit einem lateral funktionalen Aufbau |
DE102005041100.2 | 2005-08-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2007025859A2 WO2007025859A2 (fr) | 2007-03-08 |
WO2007025859A3 true WO2007025859A3 (fr) | 2007-04-26 |
Family
ID=37398874
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2006/065363 WO2007025859A2 (fr) | 2005-08-30 | 2006-08-16 | Structure de semi-conducteur a montage fonctionnel lateral |
Country Status (2)
Country | Link |
---|---|
DE (1) | DE102005041100A1 (fr) |
WO (1) | WO2007025859A2 (fr) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0465197A2 (fr) * | 1990-07-02 | 1992-01-08 | General Electric Company | Structure diélectrique à multicouches |
DE4321053A1 (de) * | 1992-06-26 | 1994-01-05 | Mitsubishi Electric Corp | Druckverpackungstyp-Halbleitervorrichtung und Verfahren zu deren Herstellung und Wärmekompensator |
WO2002050904A1 (fr) * | 2000-12-21 | 2002-06-27 | Gemplus | Connexion par organe deformable a cordons imprimés |
DE10235771A1 (de) * | 2002-08-05 | 2004-02-26 | Texas Instruments Deutschland Gmbh | Gekapselter Chip und Verfahren zu seiner Herstellung |
WO2005027222A2 (fr) * | 2003-09-12 | 2005-03-24 | Siemens Aktiengesellschaft | Composant electrique comportant une feuille d'isolation electrique disposee sur un substrat et procede de fabrication dudit dispositif |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3442131A1 (de) * | 1984-11-17 | 1986-05-22 | Messerschmitt-Bölkow-Blohm GmbH, 8012 Ottobrunn | Verfahren zum einkapseln von mikroelektronischen halbleiter- und schichtschaltungen |
US7402457B2 (en) * | 2001-09-28 | 2008-07-22 | Siemens Aktiengesellschaft | Method for making contact with electrical contact with electrical contact surfaces of substrate and device with substrate having electrical contact surfaces |
DE10335155B4 (de) * | 2003-07-31 | 2006-11-30 | Infineon Technologies Ag | Verfahren zum Herstellen einer Anordnung eines elektrischen Bauelements auf einem Substrat |
-
2005
- 2005-08-30 DE DE200510041100 patent/DE102005041100A1/de not_active Withdrawn
-
2006
- 2006-08-16 WO PCT/EP2006/065363 patent/WO2007025859A2/fr active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0465197A2 (fr) * | 1990-07-02 | 1992-01-08 | General Electric Company | Structure diélectrique à multicouches |
DE4321053A1 (de) * | 1992-06-26 | 1994-01-05 | Mitsubishi Electric Corp | Druckverpackungstyp-Halbleitervorrichtung und Verfahren zu deren Herstellung und Wärmekompensator |
WO2002050904A1 (fr) * | 2000-12-21 | 2002-06-27 | Gemplus | Connexion par organe deformable a cordons imprimés |
DE10235771A1 (de) * | 2002-08-05 | 2004-02-26 | Texas Instruments Deutschland Gmbh | Gekapselter Chip und Verfahren zu seiner Herstellung |
WO2005027222A2 (fr) * | 2003-09-12 | 2005-03-24 | Siemens Aktiengesellschaft | Composant electrique comportant une feuille d'isolation electrique disposee sur un substrat et procede de fabrication dudit dispositif |
Also Published As
Publication number | Publication date |
---|---|
WO2007025859A2 (fr) | 2007-03-08 |
DE102005041100A1 (de) | 2007-03-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW200729436A (en) | Integrated circuit device | |
WO2006138426A3 (fr) | Structure de contacts pour microcircuit | |
WO2009021741A3 (fr) | Composants électroniques organiques | |
WO2007051718A3 (fr) | Structure et procede de regulation de la degradation induite par des contraintes d'interconnexions conductrices | |
WO2008078788A1 (fr) | Substrat de dissipation de chaleur et dispositif électronique utilisant un tel substrat | |
EP2477215A3 (fr) | Composition de résine, matière incorporé, couche isolante et dispositif semi-conducteur | |
WO2006023894A3 (fr) | Composants pour le traitement de semi-conducteurs et traitement de semi-conducteurs dans lequel sont utilises ces composants | |
TW200731537A (en) | Semiconductor device and manufacturing method thereof | |
WO2005100021A3 (fr) | Structure comportant un dispositif electronique, notamment pour la fabrication d'un document de securite ou de valeur | |
TW200642526A (en) | Light-emitting device | |
EP1760800A3 (fr) | Dispositif émetteur de rayonnement et procédé de fabrication de celui-ci | |
WO2009038950A3 (fr) | Carte de circuits imprimés souple, son procédé de fabrication et dispositif électronique l'utilisant | |
EP1786249A4 (fr) | Substrat de ceramique sur lequel est fixe un composant electronique de type puce et son processus de fabrication | |
WO2005082851A3 (fr) | Composes de transport de charge et dispositifs electroniques fabriques avec de tels composes | |
TW200723422A (en) | Relay board provided in semiconductor device, semiconductor device, and manufacturing method of semiconductor device | |
WO2008149508A1 (fr) | Module à semi-conducteur et dispositifs portables | |
TW200705582A (en) | Semiconductor device and manufacturing method therefor | |
WO2006036751A3 (fr) | Circuit integre et procede de production associe | |
WO2006025571A3 (fr) | Dispositif luminescent a semiconducteur compose | |
WO2010007560A3 (fr) | Dispositif semi-conducteur et procédé de fabrication | |
WO2007075560A3 (fr) | Composant electronique presentant une faible luminescence d'arriere plan, une couche noire ou toute combinaison de celles-ci | |
WO2008108172A1 (fr) | Substrat de câblage multicouche | |
WO2009071645A3 (fr) | Substrat composite silicium-céramique | |
TW200713617A (en) | Chip package and substrate thereof | |
TW200505256A (en) | Electroluminescent device with improved light decoupling |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 06792844 Country of ref document: EP Kind code of ref document: A2 |